[PATCH v6 06/17] powerpc/vas: Define helpers to alloc/free windows

Define helpers to allocate/free VAS window objects. These will be used in follow-on patches when opening/closing windows. Signed-off-by: Sukadev Bhattiprolu --- arch/powerpc/platforms/powernv/vas-window.c | 70 + 1 file changed, 70

[PATCH v6 11/17] powerpc/vas: Define vas_win_close() interface

Define the vas_win_close() interface which should be used to close a send or receive windows. While the hardware configurations required to open send and receive windows differ, the configuration to close a window is the same for both. So we use a single interface to close the window.

[PATCH v6 15/17] powerpc/vas: Define window open ioctls API

Define the VAS_TX_WIN_OPEN and VAS_RX_WIN_OPEN ioctl interface. Each user of VAS, like the NX-FTW driver in a follow-on patch, should implement these ioctls. Signed-off-by: Sukadev Bhattiprolu --- arch/powerpc/include/uapi/asm/vas.h | 30

[PATCH v6 17/17] powerpc/vas: Document FTW API/usage

Document the usage of the VAS Fast thread-wakeup API. Thanks for input/comments from Benjamin Herrenschmidt, Michael Neuling, Michael Ellerman, Robert Blackmore, Ian Munsie, Haren Myneni, Paul Mackerras. Cc:Ian Munsie Cc:Paul Mackerras Signed-off-by:

[PATCH v6 00/17] powerpc/vas: Enable VAS

POWER9 introduces a hardware subsystem referred to as the Virtual Accelerator Switchboard (VAS). VAS allows kernel subsystems and user space processes to directly access the Nest Accelerator (NX) engines which implement compression and encryption algorithms in the hardware. NX has been in Power

[PATCH v6 04/17] powerpc/vas: Define helpers to access MMIO regions

Define some helper functions to access the MMIO regions. We use these in follow-on patches to read/write VAS hardware registers. They are also used to later issue 'paste' instructions to submit requests to the NX hardware engines. Signed-off-by: Sukadev Bhattiprolu

[PATCH v6 09/17] powerpc/vas: Define vas_rx_win_open() interface

Define the vas_rx_win_open() interface. This interface is intended to be used by the Nest Accelerator (NX) driver(s) to setup receive windows for one or more NX engines (which implement compression/encryption algorithms in the hardware). Follow-on patches will provide an interface to close the

[PATCH v6 10/17] powerpc/vas: Define vas_rx_win_open() interface

Define the vas_rx_win_open() interface. This interface is intended to be used by the Nest Accelerator (NX) driver(s) to setup receive windows for one or more NX engines (which implement compression/encryption algorithms in the hardware). Follow-on patches will provide an interface to close the

[PATCH v6 14/17] powerpc: Add support for setting SPRN_TIDR

We need the SPRN_TIDR to bet set for use with fast thread-wakeup (core-to-core wakeup). Each thread in a process needs to have a unique id within the process but as explained below, for now, we assign globally unique thread ids to all threads in the system. Signed-off-by: Sukadev Bhattiprolu

[PATCH v6 01/17] powerpc/vas: Define macros, register fields and structures

Define macros for the VAS hardware registers and bit-fields as well as couple of data structures needed by the VAS driver. Signed-off-by: Sukadev Bhattiprolu --- Changelog[v6] - Add some fields for FTW windows Changelog[v4] - [Michael Neuling] Move

[PATCH v6 05/17] powerpc/vas: Define helpers to init window context

Define helpers to initialize window context registers of the VAS hardware. These will be used in follow-on patches when opening/closing VAS windows. Signed-off-by: Sukadev Bhattiprolu --- Changelog[v6] - Add support for FTW windows and drop the fault window id

[PATCH v6 12/17] powerpc/vas: Define vas_tx_win_open()

Define an interface to open a VAS send window. This interface is intended to be used the Nest Accelerator (NX) driver(s) to open a send window and use it to submit compression/encryption requests to a VAS receive window. The receive window, identified by the [vasid, cop] parameters, must already

[PATCH v6 16/17] powerpc/vas: Implement a simple FTW driver

The Fast Thread Wake-up (FTW) driver provides user space applications an interface to the Core-to-Core functionality in POWER9. The driver provides the device node/ioctl API to applications and uses the external interfaces to the VAS driver to interact with the VAS hardware. A follow-on patch

[PATCH v6 03/17] powerpc/vas: Define vas_init() and vas_exit()

Implement vas_init() and vas_exit() functions for a new VAS module. This VAS module is essentially a library for other device drivers and kernel users of the NX coprocessors like NX-842 and NX-GZIP. In the future this will be extended to add support for user space to access the NX coprocessors.

[PATCH v6 02/17] powerpc/vas: Move GET_FIELD/SET_FIELD to vas.h

Move the GET_FIELD and SET_FIELD macros to vas.h as VAS and other users of VAS, including NX-842 can use those macros. There is a lot of related code between the VAS/NX kernel drivers and skiboot. For consistency switch the order of parameters in SET_FIELD to match the order in skiboot.

[PATCH v6 13/17] powerpc/vas: Define copy/paste interfaces

Define interfaces (wrappers) to the 'copy' and 'paste' instructions (which are new in PowerISA 3.0). These are intended to be used to by NX driver(s) to submit Coprocessor Request Blocks (CRBs) to the NX hardware engines. Signed-off-by: Sukadev Bhattiprolu ---

[PATCH v6 08/17] powerpc/vas: Define vas_win_id()

Define an interface to return a system-wide unique id for a given VAS window. The vas_win_id() will be used in a follow-on patch to generate an unique handle for a user space receive window. Applications can use this handle to pair send and receive windows for fast thread-wakeup. The hardware

[PATCH v6 07/17] powerpc/vas: Define vas_win_paste_addr()

Define an interface that the NX drivers can use to find the physical paste address of a send window. This interface is expected to be used with the mmap() operation of the NX driver's device. i.e the user space process can use driver's mmap() operation to map the send window's paste address into

Re: [PATCH] powerpc: xive: ensure active irqd when setting affinity

Michael Ellerman [m...@ellerman.id.au] wrote: > Sukadev Bhattiprolu writes: > > > From fd0abf5c61b6041fdb75296e8580b86dc91d08d6 Mon Sep 17 00:00:00 2001 > > From: Benjamin Herrenschmidt > > Date: Tue, 1 Aug 2017 20:54:41 -0500 > > Subject:

[PATCH 8/9] powerpc/mce: Move 64-bit machine check code into mce.c

We already have mce.c which is built for 64bit and contains other parts of the machine check code, so move these bits in there too. Signed-off-by: Michael Ellerman --- arch/powerpc/kernel/mce.c | 33 + arch/powerpc/kernel/traps.c | 33

[PATCH] powerpc/iommu: Avoid undefined right shift in iommu_range_alloc()

In iommu_range_alloc() we generate a mask by right shifting ~0, however if the specified alignment is 0 then we right shift by 64, which is undefined. UBSAN tells us so: UBSAN: Undefined behaviour in ../arch/powerpc/kernel/iommu.c:193:35 shift exponent 64 is too large for 64-bit type 'long

[PATCH 10/10] powerpc/xive: fix the size of the cpumask used in xive_find_target_in_mask()

When called from xive_irq_startup(), the size of the cpumask can be larger than nr_cpu_ids. Most of time, its value is NR_CPUS (2048). This can result in such WARNINGs in xive_find_target_in_mask(): [0.094480] WARNING: CPU: 10 PID: 1 at ../arch/powerpc/sysdev/xive/common.c:476

[PATCH 00/10] guest exploitation of the XIVE interrupt controller

Hello, On a POWER9 sPAPR machine, the Client Architecture Support (CAS) negotiation process determines whether the guest operates with an interrupt controller using the legacy model, as found on POWER8, or in XIVE exploitation mode, the newer POWER9 interrupt model. This patchset is a first

[PATCH 01/10] powerpc/xive: fix OV5_XIVE_EXPLOIT bits

Platform Exploitation Mode support is indicated by the property "ibm,arch-vec-5-platform-support-vec-5" : byte 23 bits 0-1 set to 0b01 or 0b10 OS Selection for Exploitation Mode is indicated by the property "ibm,architecture-vec-5" : byte 23 bits 0-1 set to 0b01. A value of 0b00 indicates use of

[PATCH 07/10] powerpc/xive: add XIVE exploitation mode to CAS

On POWER9, the Client Architecture Support (CAS) negotiation process determines whether the guest operates in XIVE Legacy compatibility or in XIVE exploitation mode. Now that we have initial guest support for the XIVE interrupt controller, let's inform the hypervisor what we can do.

Re: block/ps3vram: Delete an error message for a failed memory allocation in ps3vram_cache_init()

>> https://patchwork.ozlabs.org/patch/798575/ > > I submitted your patch Thanks for your constructive feedback. https://patchwork.ozlabs.org/patch/798850/ > and a fix to ps3vram_probe() with the other patches in my queue. I find it nice that you picked this change opportunity up after a bit

[PATCH 08/10] powerpc/xive: take into account '/ibm, plat-res-int-priorities'

'/ibm,plat-res-int-priorities' contains a list of priorities that the hypervisor has reserved for its own use. Scan these ranges to choose the lowest unused priority for the xive spapr backend. Signed-off-by: Cédric Le Goater --- arch/powerpc/sysdev/xive/spapr.c | 62

[PATCH 05/10] powerpc/xive: add the HW IRQ number under xive_irq_data

It will be required later by the H_INT_ESB hcall. Signed-off-by: Cédric Le Goater --- arch/powerpc/include/asm/xive.h | 1 + arch/powerpc/sysdev/xive/native.c | 2 ++ arch/powerpc/sysdev/xive/spapr.c | 2 ++ 3 files changed, 5 insertions(+) diff --git

[PATCH 2/9] powerpc/44x: Simplify CONFIG_44x checks in Makefile

The entire 44x directory is omitted if CONFIG_44x is not enabled, so within the 44x/Makefile CONFIG_44x is always y. So convert obj-$(CONFIG_44x) to the more obvious obj-y. Signed-off-by: Michael Ellerman --- arch/powerpc/platforms/44x/Makefile | 4 ++-- 1 file changed, 2

[PATCH 1/9] powerpc/47x: Guard 47x cputable entries with CONFIG_PPC_47x

Currently we build the 47x cputable entries even when CONFIG_PPC_47x is disabled. That means a kernel built without CONFIG_PPC_47x will claim to support a 47x CPU and start booting, only to break somewhere later because it doesn't have 47x support compiled in. So guard the 47x cputable entries

[PATCH 5/9] powerpc/4xx: Move machine_check_4xx() into platforms/4xx

Now that we have 4xx platform directory we can move the 4xx machine check handler in there. Again we drop get_mc_reason() and replace it with regs->dsisr directly (which is actually SPRN_ESR). Signed-off-by: Michael Ellerman --- arch/powerpc/kernel/traps.c|

[PATCH v5] powerpc/mm: Only read faulting instruction when necessary in do_page_fault()

Commit a7a9dcd882a67 ("powerpc: Avoid taking a data miss on every userspace instruction miss") has shown that limiting the read of faulting instruction to likely cases improves performance. This patch goes further into this direction by limiting the read of the faulting instruction to the only

[PATCH 06/10] powerpc/xive: introduce H_INT_ESB hcall

The H_INT_ESB hcall() is used to issue a load or store to the ESB page instead of using the MMIO pages. This can be used as a workaround on some HW issues. The OS knows that this hcall should be used on an interrupt source when the ESB hcall flag is set to 1 in the hcall H_INT_GET_SOURCE_INFO. To

[PATCH 09/10] powerpc/xive: improve debugging macros

Having the CPU identifier in the debug logs is helpful when tracking issues. Also add some more logging and fix a compile issue in xive_do_source_eoi(). Signed-off-by: Cédric Le Goater --- arch/powerpc/sysdev/xive/common.c | 8 ++-- 1 file changed, 6 insertions(+), 2

Re: [v6 11/15] arm64/kasan: explicitly zero kasan shadow memory

On Mon, Aug 07, 2017 at 04:38:45PM -0400, Pavel Tatashin wrote: > To optimize the performance of struct page initialization, > vmemmap_populate() will no longer zero memory. > > We must explicitly zero the memory that is allocated by vmemmap_populate() > for kasan, as this memory does not go

[PATCH 03/10] powerpc/xive: rename xive_poke_esb in xive_esb_read

xive_poke_esb() is performing a load/read so it is better named as xive_esb_read(). Also introduce a XIVE_ESB_LOAD_EOI read when EOI'ing LSI interrupts. Signed-off-by: Cédric Le Goater --- arch/powerpc/sysdev/xive/common.c | 20 ++-- 1 file changed, 10

[PATCH 6/9] powerpc/traps: Inline get_mc_reason()

get_mc_reason() no longer provides (if it ever really did) any meaningful abstraction, so remove it. Signed-off-by: Michael Ellerman --- arch/powerpc/kernel/traps.c | 14 -- 1 file changed, 4 insertions(+), 10 deletions(-) diff --git

[PATCH 7/9] powerpc/traps: machine_check_generic() is only used on 32-bit

Make it clear that the fallback version of machine_check_generic() is only used on 32-bit configs. Signed-off-by: Michael Ellerman --- arch/powerpc/kernel/traps.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/powerpc/kernel/traps.c

[PATCH 04/10] powerpc/xive: introduce xive_esb_write

Signed-off-by: Cédric Le Goater --- arch/powerpc/sysdev/xive/common.c | 11 ++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/sysdev/xive/common.c b/arch/powerpc/sysdev/xive/common.c index e6b245bb9602..22b6f8954083 100644 ---

[PATCH 3/9] powerpc/44x: Move 44x machine check handlers into platforms/44x

We have several 44x machine check handlers defined in traps.c. It would be preferable if they were split out with the platforms that use them. Do that. In the process, drop get_mc_reason() and instead just open code the lookup of reason from regs->dsisr. This avoids a pointless layer of

[PATCH 4/9] powerpc/4xx: Create 4xx pseudo-platform in platforms/4xx

We have a lot of code in sysdev for supporting 4xx, ie. either 40x or 44x. Instead it would be cleaner if it was all in platforms/4xx. This is slightly odd in that we don't actually define any machines in the 4xx platform, as is usual for a platform directory. But still it seems like a better

Re: [01/24] powerpc/mm: Move exception_enter/exit to a do_page_fault wrapper

Le 08/08/2017 à 04:16, Michael Ellerman a écrit : Christophe LEROY writes: Le 07/08/2017 à 12:41, Michael Ellerman a écrit : On Wed, 2017-07-19 at 04:49:23 UTC, Benjamin Herrenschmidt wrote: This will allow simplifying the returns from do_page_fault

[PATCH 9/9] powerpc/traps: Use SRR1 defines for program check reasons

Currently we open code the reason codes for program checks. Instead use the existing SRR1 defines. Signed-off-by: Michael Ellerman --- arch/powerpc/include/asm/reg.h | 1 + arch/powerpc/kernel/traps.c| 10 +- 2 files changed, 6 insertions(+), 5 deletions(-)

[v2 PATCH] powerpc/powernv/idle: Disable LOSE_FULL_CONTEXT states when stop-api fails

From: "Gautham R. Shenoy" Currently, we use the opal call opal_slw_set_reg() to inform the Sleep-Winkle Engine (SLW) to restore the contents of some of the Hypervisor state on wakeup from deep idle states that lose full hypervisor context (characterized by the flag

[PATCH 02/10] powerpc/xive: guest exploitation of the XIVE interrupt controller

This is the framework for using XIVE in a PowerVM guest. The support is very similar to the native one in a much simpler form. Instead of OPAL calls, a set of Hypervisors call are used to configure the interrupt sources and the event/notification queues of the guest: - H_INT_GET_SOURCE_INFO

RE: [PATCH v10 4/4] irqchip/qeic: remove PPCisms for QEIC

On Mon 8/7/2017 3:02 PM, Michael Ellerman wrote: > -Original Message- > From: Michael Ellerman [mailto:m...@ellerman.id.au] > Sent: Monday, August 07, 2017 3:02 PM > To: Qiang Zhao ; t...@linutronix.de > Cc: o...@buserror.net; Qiang Zhao

[PATCH] powerpc/32: Fix boot failure on non 6xx platforms

commit d300627c6a536 ("powerpc/6xx: Handle DABR match before calling do_page_fault") breaks non 6xx platforms. [6.029556] Failed to execute /init (error -14) [6.034623] Starting init: /bin/sh exists but couldn't execute it (error -14) [6.041489] Kernel panic - not syncing: No working

RE: [PATCH v10 4/4] irqchip/qeic: remove PPCisms for QEIC

On Tue 8/8/2017 6:05 PM, Michael Ellerman wrote: > -Original Message- > From: Michael Ellerman [mailto:m...@ellerman.id.au] > Sent: Tuesday, August 08, 2017 6:05 PM > To: Qiang Zhao ; t...@linutronix.de > Cc: o...@buserror.net;

Re: [PATCH 02/10] powerpc/xive: guest exploitation of the XIVE interrupt controller

On Tue, Aug 08, 2017 at 10:56:12AM +0200, Cédric Le Goater wrote: > This is the framework for using XIVE in a PowerVM guest. The support > is very similar to the native one in a much simpler form. > > Instead of OPAL calls, a set of Hypervisors call are used to configure > the interrupt sources

Re: [PATCH 03/10] powerpc/xive: rename xive_poke_esb in xive_esb_read

On Tue, Aug 08, 2017 at 10:56:13AM +0200, Cédric Le Goater wrote: > xive_poke_esb() is performing a load/read so it is better named as > xive_esb_read(). Uh, patch seems to mismatch the comment here, calling it xive_peek_esb() instead. Does reading the ESB had a side effect on the hardware? If

Re: [PATCH] powerpc/include/asm: Remove unused 64bit cacheflush function

On 20/07/17 16:25, Matt Brown wrote: The flush_dcache_phys_range function is no longer used in the kernel. This patch removes and cleans up the function. Signed-off-by: Matt Brown That does indeed look unused. Reviewed-by: Andrew Donnellan

Re: [PATCH 08/10] powerpc/xive: take into account '/ibm,plat-res-int-priorities'

On Tue, Aug 08, 2017 at 10:56:18AM +0200, Cédric Le Goater wrote: > '/ibm,plat-res-int-priorities' contains a list of priorities that the > hypervisor has reserved for its own use. Scan these ranges to choose > the lowest unused priority for the xive spapr backend. > > Signed-off-by: Cédric Le

Re: [RFC] hwmon: (ibmpowernv) Add support for reset-history sensors

On 07/25/2017 10:55 PM, Shilpasri G Bhat wrote: In P9, OCC allows for clearing the sensor min-max history. This patch exports attribute to reset history when set will clear the history of all the sensors owned by CSM and belonging to the chip. Signed-off-by: Shilpasri G Bhat

Re: [PATCH 3/3] powerpc/mm: Mark __init memory no-execute when STRICT_KERNEL_RWX=y

Christophe LEROY writes: > Le 14/07/2017 à 08:51, Michael Ellerman a écrit : >> diff --git a/arch/powerpc/include/asm/book3s/64/pgtable.h >> b/arch/powerpc/include/asm/book3s/64/pgtable.h >> index c0737c86a362..3d562b210c65 100644 >> ---

Re: [PATCH 16/16] perf tools: Add support for SPF events

On 08/08/2017 08:05 PM, Laurent Dufour wrote: > Add support for the new speculative faults events. > > Signed-off-by: Laurent Dufour > --- > tools/include/uapi/linux/perf_event.h | 2 ++ > tools/perf/util/evsel.c | 2 ++ > tools/perf/util/parse-events.c

[PATCH 01/12] powerpc/8xx: Simplify CONFIG_8xx checks in Makefile

The entire 8xx directory is omitted if CONFIG_8xx is not enabled, so within the 8xx/Makefile CONFIG_8xx is always y. So convert obj-$(CONFIG_8xx) to the more obvious obj-y. Signed-off-by: Christophe Leroy --- This serie applies on top of Michael's serie begining with

[PATCH 03/12] powerpc/8xx: Remove SoftwareEmulation()

Since commit aa42c69c67f82 ("[POWERPC] Add support for FP emulation for the e300c2 core"), program_check_exception() can be called for math emulation. In that case, 'reason' is 0. On the 8xx, there is a Software Emulation interrupt which is called for all unimplemented and illegal instructions.

[PATCH 05/12] powerpc/8xx: Move mpc8xx_pic.c from sysdev to platform/8xx

mpc8xx_pic.c is dedicated to the 8xx, so move it to platform/8xx Signed-off-by: Christophe Leroy --- arch/powerpc/platforms/8xx/Makefile | 2 +- arch/powerpc/platforms/8xx/m8xx_setup.c | 2 +- arch/powerpc/{sysdev/mpc8xx_pic.c =>

[PATCH 08/12] powerpc/8xx: Getting rid of remaining use of CONFIG_8xx

Two config options exist to define powerpc MPC8xx: * CONFIG_PPC_8xx * CONFIG_8xx arch/powerpc/platforms/Kconfig.cputype has contained the following comment about CONFIG_8xx item for some years: "# this is temp to handle compat with arch=ppc" arch/powerpc is now the only place with remaining use

[PATCH 09/12] powerpc/8xx: remove CONFIG_8xx

Two config options exist to define powerpc MPC8xx: * CONFIG_PPC_8xx * CONFIG_8xx arch/powerpc/platforms/Kconfig.cputype has contained the following comment about CONFIG_8xx item for some years: "# this is temp to handle compat with arch=ppc" There is no more users of CONFIG_8xx, so remove it.

[PATCH 11/12] powerpc/8xx: Use symbolic names for DSISR bits in DSI

Use symbolic names for DSISR bits in DSI Signed-off-by: Christophe Leroy --- arch/powerpc/kernel/head_8xx.S | 2 +- arch/powerpc/mm/fault.c| 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/kernel/head_8xx.S

Re: [v6 11/15] arm64/kasan: explicitly zero kasan shadow memory

On Tue, Aug 08, 2017 at 07:49:22AM -0400, Pasha Tatashin wrote: > Hi Will, > > Thank you for looking at this change. What you described was in my previous > iterations of this project. > > See for example here: https://lkml.org/lkml/2017/5/5/369 > > I was asked to remove that flag, and only

Re: [v6 11/15] arm64/kasan: explicitly zero kasan shadow memory

Hi Will, > Damn, I actually prefer the flag :) > > But actually, if you look at our implementation of vmemmap_populate, then we > have our own version of vmemmap_populate_basepages that terminates at the > pmd level anyway if ARM64_SWAPPER_USES_SECTION_MAPS. If there's resistance > to do

[PATCH 04/12] powerpc/cpm1: link to CONFIG_CPM1 instead of CONFIG_8xx

To remain consistent with what is done with CPM2, let's link CPM1 related parts to CONFIG_CPM1 instead of CONFIG_8xx When something depends on both CPM1 and CPM2 we associate it with CONFIG_CPM Signed-off-by: Christophe Leroy --- arch/powerpc/sysdev/Makefile | 3 ++-

[PATCH 06/12] powerpc/time: refactor MFTB() to limit number of ifdefs

The 8xx cannot access the TBL and TBU registers using mfspr/mtspr It must be accessed using mftb/mftbu Due to this, there is a number of places with #ifdef CONFIG_8xx This patch defines new macros MFTBL(x) and MFTBU(x) on the same model as MFTB(x) and tries to make use of them as much as

[PATCH 07/12] powerpc/kconfig: Simplify PCI_QSPAN selection

4xx, CPM2 and 8xx cannot be selected at the same time, so no need to test 8xx && !4xx && !CPM2. Testing 8xx is enough. Signed-off-by: Christophe Leroy --- arch/powerpc/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/Kconfig

[PATCH 10/12] powerpc/8xx: Use symbolic PVR value

For the 8xx, PVR values defined in arch/powerpc/include/asm/reg.h are nowhere used. Remove all defines and add PVR_8xx Use it in arch/powerpc/kernel/cputable.c Signed-off-by: Christophe Leroy --- arch/powerpc/include/asm/reg.h | 6 ++

[PATCH 12/12] powerpc/8xx: Remove cpu dependent macro instructions from head_8xx

head_8xx is dedicated to 8xx so no need to use macros that depends on the CPU Signed-off-by: Christophe Leroy --- arch/powerpc/kernel/head_8xx.S | 5 + 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/arch/powerpc/kernel/head_8xx.S

Re: [PATCH 10/13] powerpc/64s: idle simplify KVM idle on POWER9

On Tue, 8 Aug 2017 16:06:43 +0530 Gautham R Shenoy wrote: > Hi Nicholas, > > On Sun, Aug 06, 2017 at 03:02:38AM +1000, Nicholas Piggin wrote: > > POWER9 CPUs have independent MMU contexts per thread so KVM > > does not have to bring sibling threads into real-mode when >

[PATCH 00/12] powerpc/8xx: Some cleanup

This serie does some cleanup in the area of the 8xx. In the same spirit as what Michael did for 4xx, move 8xx specific stuff into platforms/8xx Then try to reduce the amount of #ifdefs specific to 8xx Remove the CONFIG_8xx which is redundant with CONFIG_PPC_8xx Plus some misc cleanups

[PATCH 02/12] powerpc/8xx: Move 8xx machine check handlers into platforms/8xx

In the same spirit as what was done for 4xx and 44x, move the 8xx machine check into platforms/8xx Signed-off-by: Christophe Leroy --- arch/powerpc/kernel/traps.c| 25 arch/powerpc/platforms/8xx/Makefile| 2 +-

Re: block/ps3vram: Check return of ps3vram_cache_init

> @@ -741,7 +741,11 @@ static int ps3vram_probe(struct ps3_system_bus_device > *dev) > goto out_unmap_reports; > } > > - ps3vram_cache_init(dev); > + error = ps3vram_cache_init(dev); > + if (error < 0) { > + goto out_unmap_reports; > + } > + >

Re: [PATCH 0/3] Minor updates for PS3

Geoff Levand writes: > Hi Michael, > > A few very minor updates for PS3. Please apply. Jens do you want to take the block ones, or should I just take the lot? cheers

Re: [v4] powerpc/powernv: Enable PCI peer-to-peer

On Fri, 2017-08-04 at 09:55:14 UTC, Frederic Barrat wrote: > P9 has support for PCI peer-to-peer, enabling a device to write in the > mmio space of another device directly, without interrupting the CPU. > > This patch adds support for it on powernv, by adding a new API to be > called by drivers.

ksmd circular locking warning, cpu_hotplug_lock vs ksm_thread_mutex

Hi all, Apologies for the large Cc list, but wasn't really sure who to send this to. I've seen this once on a Power8 box, with next-20170807. I think it happened while I was running the memory hoptlug selftests. cheers [ 3532.474435] ==

Re: [PATCH] powerpc: fix invalid use of register expressions

Andreas Schwab writes: > binutils >= 2.26 now warns about misuse of register expressions in > assembler operands that are actually literals, for example: > > arch/powerpc/kernel/entry_64.S:535: Warning: invalid register expression > > Signed-off-by: Andreas Schwab

Re: [PATCH 3/3] powerpc: replace vga_fixup() with generic code

Daniel Axtens writes: > Michael Ellerman writes: > >> Daniel Axtens writes: >> >>> Currently, we do a PCI fixup to mark a default card so that Xorg >>> autoconfiguration works. >>> >>> There is a new generic method to do this sort of vga

Re: [PATCH 11/13] powerpc/64s: idle POWER9 can execute stop without ptesync

On Sun, Aug 06, 2017 at 03:02:39AM +1000, Nicholas Piggin wrote: > Signed-off-by: Nicholas Piggin Reviewed-by: Gautham R. Shenoy -- Thanks and Regards gautham.

Re: [PATCH 12/13] powerpc/64s: idle POWER9 can execute stop in virtual mode

On Sun, Aug 06, 2017 at 03:02:40AM +1000, Nicholas Piggin wrote: > The hardware can execute stop in any context, and KVM does not > require real mode. This saves a switch to real-mode when going > idle. > > Signed-off-by: Nicholas Piggin Acked-by: Gautham R. Shenoy

[PATCH] Revert "powerpc/64: Avoid restore_math call if possible in syscall exit"

This reverts commit bc4f65e4cf9d6cc43e0e9ba0b8648cf9201cd55f. As reported by Andreas, this commit is causing unrecoverable SLB misses in the system call exit path: Unrecoverable exception 4100 at c000a1ec Oops: Unrecoverable exception, sig: 6 [#1] SMP NR_CPUS=2 PowerMac ...

Applied "ASoC: fsl: Convert to using %pOF instead of full_name" to the asoc tree

The patch ASoC: fsl: Convert to using %pOF instead of full_name has been applied to the asoc tree at git://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git All being well this means that it will be integrated into the linux-next tree (usually sometime in the next 24 hours) and

Re: Revert "powerpc/64: Avoid restore_math call if possible in syscall exit"

On Tue, 2017-08-08 at 10:55:57 UTC, Michael Ellerman wrote: > This reverts commit bc4f65e4cf9d6cc43e0e9ba0b8648cf9201cd55f. > > As reported by Andreas, this commit is causing unrecoverable SLB misses in the > system call exit path: > > Unrecoverable exception 4100 at c000a1ec > Oops:

Re: [01/24] powerpc/mm: Move exception_enter/exit to a do_page_fault wrapper

Christophe LEROY writes: > Le 08/08/2017 à 04:16, Michael Ellerman a écrit : >> Christophe LEROY writes: >> >>> Le 07/08/2017 à 12:41, Michael Ellerman a écrit : On Wed, 2017-07-19 at 04:49:23 UTC, Benjamin Herrenschmidt wrote: > This

Re: [PATCH 13/13] powerpc/64s: idle ESL=0 stop can avoid all save/restore overhead

On Sun, Aug 06, 2017 at 03:02:41AM +1000, Nicholas Piggin wrote: > When stop is executed with EC=ESL=0, it appears to execute like a > normal instruction (resuming from NIP when woken by interrupt). > So all the save/restore handling can be avoided completely. In > particular NV GPRs do not have

Re: powerpc/32: Fix boot failure on non 6xx platforms

On Tue, 2017-08-08 at 06:37:24 UTC, Christophe Leroy wrote: > commit d300627c6a536 ("powerpc/6xx: Handle DABR match before > calling do_page_fault") breaks non 6xx platforms. > > [6.029556] Failed to execute /init (error -14) > [6.034623] Starting init: /bin/sh exists but couldn't execute

[PATCH] powerpc/mm: Fix section mismatch warning in early_check_vec5()

early_check_vec5() is called from and calls __init routines, so should also be __init. Signed-off-by: Michael Ellerman --- arch/powerpc/mm/init_64.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/powerpc/mm/init_64.c b/arch/powerpc/mm/init_64.c

Re: [v6 11/15] arm64/kasan: explicitly zero kasan shadow memory

Hi Will, Thank you for looking at this change. What you described was in my previous iterations of this project. See for example here: https://lkml.org/lkml/2017/5/5/369 I was asked to remove that flag, and only zero memory in place when needed. Overall the current approach is better

Re: [PATCH] powerpc: xive: ensure active irqd when setting affinity

Sukadev Bhattiprolu writes: > From fd0abf5c61b6041fdb75296e8580b86dc91d08d6 Mon Sep 17 00:00:00 2001 > From: Benjamin Herrenschmidt > Date: Tue, 1 Aug 2017 20:54:41 -0500 > Subject: [PATCH] powerpc: xive: ensure active irqd when setting

Re: [1/3] powerpc/mm/book3s64: Make KERN_IO_START a variable

On Tue, 2017-08-01 at 10:29:22 UTC, Michael Ellerman wrote: > Currently KERN_IO_START is defined as: > > #define KERN_IO_START (KERN_VIRT_START + (KERN_VIRT_SIZE >> 1)) > > Although it looks like a constant, both the components are actually > variables, to allow us to have a different value

RE: [PATCH v10 4/4] irqchip/qeic: remove PPCisms for QEIC

Qiang Zhao writes: > On Mon 8/7/2017 3:02 PM, Michael Ellerman wrote: > >> -Original Message- >> From: Michael Ellerman [mailto:m...@ellerman.id.au] >> Sent: Monday, August 07, 2017 3:02 PM >> To: Qiang Zhao ;

Re: [PATCH 10/13] powerpc/64s: idle simplify KVM idle on POWER9

Hi Nicholas, On Sun, Aug 06, 2017 at 03:02:38AM +1000, Nicholas Piggin wrote: > POWER9 CPUs have independent MMU contexts per thread so KVM > does not have to bring sibling threads into real-mode when > switching MMU mode to guest. This can simplify POWER9 sleep/wake > paths and avoids hwsyncs. >

Re: [PATCH] powerpc/xmon: Exclude all of xmon/ from ftrace

"Naveen N. Rao" writes: > diff --git a/arch/powerpc/xmon/Makefile b/arch/powerpc/xmon/Makefile > index 0b2f771593eb..5f95af64cb8f 100644 > --- a/arch/powerpc/xmon/Makefile > +++ b/arch/powerpc/xmon/Makefile > @@ -7,6 +7,19 @@ UBSAN_SANITIZE := n > >

Re: [v3] powerpc/powernv: Use darn instr for random_seed on p9

On Fri, 2017-08-04 at 01:12:18 UTC, Matt Brown wrote: > This adds the powernv_get_random_darn function which utilises the darn > instruction, introduced in POWER9. The powernv_get_random_darn function > is used as the ppc_md.get_random_seed on P9. > > The DARN instruction can potentially throw an

[PATCH] powerpc/xive: Fix section mismatch warnings

Both xive_core_init() and xive_native_init() are called from and call __init routines, so they should also be __init. Signed-off-by: Michael Ellerman --- arch/powerpc/sysdev/xive/common.c | 4 ++-- arch/powerpc/sysdev/xive/native.c | 2 +- 2 files changed, 3 insertions(+),

Re: [PATCH 0/3] Minor updates for PS3

On 08/08/2017 04:16 AM, Michael Ellerman wrote: > Geoff Levand writes: > >> Hi Michael, >> >> A few very minor updates for PS3. Please apply. > > Jens do you want to take the block ones, or should I just take the lot? Up to you, I'm fine either way. -- Jens Axboe

RE: [v6 11/15] arm64/kasan: explicitly zero kasan shadow memory

From: Pasha Tatashin > Sent: 08 August 2017 12:49 > Thank you for looking at this change. What you described was in my > previous iterations of this project. > > See for example here: https://lkml.org/lkml/2017/5/5/369 > > I was asked to remove that flag, and only zero memory in place when >

Re: [v6 11/15] arm64/kasan: explicitly zero kasan shadow memory

On 2017-08-08 09:15, David Laight wrote: From: Pasha Tatashin Sent: 08 August 2017 12:49 Thank you for looking at this change. What you described was in my previous iterations of this project. See for example here: https://lkml.org/lkml/2017/5/5/369 I was asked to remove that flag, and only

[PATCH 02/16] mm: Prepare for FAULT_FLAG_SPECULATIVE

From: Peter Zijlstra When speculating faults (without holding mmap_sem) we need to validate that the vma against which we loaded pages is still valid when we're ready to install the new PTE. Therefore, replace the pte_offset_map_lock() calls that (re)take the PTL with

[PATCH 07/16] mm: Provide speculative fault infrastructure

From: Peter Zijlstra Provide infrastructure to do a speculative fault (not holding mmap_sem). The not holding of mmap_sem means we can race against VMA change/removal and page-table destruction. We use the SRCU VMA freeing to keep the VMA around. We use the VMA seqcount to

[PATCH 11/16] mm: Introduce __page_add_new_anon_rmap()

When dealing with speculative page fault handler, we may race with VMA being split or merged. In this case the vma->vm_start and vm->vm_end fields may not match the address the page fault is occurring. This can only happens when the VMA is split but in that case, the anon_vma pointer of the new

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