The powernv platform maintains 2 TCE tables for VFIO - a hardware TCE
table and a table with userspace addresses. These tables are radix trees,
we allocate indirect levels when they are written to. Since
the memory allocation is problematic in real mode, we have 2 accessors
to the entries:
- for
The powernv platform maintains 2 TCE tables for VFIO - a hardware TCE
table and a table with userspace addresses; the latter is used for
marking pages dirty when corresponging TCEs are unmapped from
the hardware table.
a68bd1267b72 ("powerpc/powernv/ioda: Allocate indirect TCE levels
on demand")
The included opal.h gives a wrong idea that CXL makes PPC OPAL calls
while it does not so let's remote it.
Signed-off-by: Alexey Kardashevskiy
---
drivers/misc/cxl/pci.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/misc/cxl/pci.c b/drivers/misc/cxl/pci.c
index b66d832..8cbcbb7
Hi Nathan,
On Thu, Sep 27, 2018 at 12:31:34PM -0500, Nathan Fontenot wrote:
> On 09/27/2018 11:51 AM, Gautham R. Shenoy wrote:
> > From: "Gautham R. Shenoy"
> >
> > Live Partition Migrations require all the present CPUs to execute the
> > H_JOIN call, and hence rtas_ibm_suspend_me() onlines any
The macro and few headers are not used so remove them.
Signed-off-by: Alexey Kardashevskiy
---
arch/powerpc/platforms/powernv/npu-dma.c | 14 --
1 file changed, 14 deletions(-)
diff --git a/arch/powerpc/platforms/powernv/npu-dma.c
b/arch/powerpc/platforms/powernv/npu-dma.c
index
On Fri, Sep 28, 2018 at 3:07 PM Rob Herring wrote:
>
> On Thu, Sep 27, 2018 at 5:25 PM Li Yang wrote:
> >
> > Hi Rob and Grant,
> >
> > Various device tree specs are recommending to include all the
> > potential compatible strings in the device node, with the order from
> > most specific to most
On Fri, Sep 28, 2018 at 4:00 PM Li Yang wrote:
>
> On Fri, Sep 28, 2018 at 3:07 PM Rob Herring wrote:
> >
> > On Thu, Sep 27, 2018 at 5:25 PM Li Yang wrote:
> > >
> > > Hi Rob and Grant,
> > >
> > > Various device tree specs are recommending to include all the
> > > potential compatible strings
On Mon, Aug 27, 2018 at 8:55 PM Rob Herring wrote:
>
> In preparation to remove the node name pointer from struct device_node,
> convert printf users to use the %pOFn format specifier.
>
> Cc: Greg Kroah-Hartman
> Cc: Jiri Slaby
> Cc: Benjamin Herrenschmidt
> Cc: Paul Mackerras
> Cc: Michael
On Fri, Sep 28, 2018 at 5:09 PM Rob Herring wrote:
>
> On Mon, Aug 27, 2018 at 8:55 PM Rob Herring wrote:
> >
> > In preparation to remove the node name pointer from struct device_node,
> > convert printf users to use the %pOFn format specifier.
> >
> > Cc: Greg Kroah-Hartman
> > Cc: Jiri Slaby
In preparation to remove the node name pointer from struct device_node,
convert printf users to use the %pOFn format specifier.
Cc: Benjamin Herrenschmidt
Cc: Paul Mackerras
Cc: Michael Ellerman
Cc: Peter Rosin
Cc: linux-...@vger.kernel.org
Cc: linuxppc-dev@lists.ozlabs.org
Signed-off-by: Rob
On Fri, Sep 28, 2018 at 09:39:10PM +1000, Michael Ellerman wrote:
> -BEGIN PGP SIGNED MESSAGE-
> Hash: SHA512
>
> Hi Greg,
>
> Please pull some more powerpc fixes for 4.19:
>
> The following changes since commit 11da3a7f84f19c26da6f86af878298694ede0804:
>
> Linux 4.19-rc3 (2018-09-09
Le 28/09/2018 à 05:41, Michael Ellerman a écrit :
Christophe Leroy writes:
Add call to early_memtest() so that kernel compiled with
CONFIG_MEMTEST really perform memtest at startup when requested
via 'memtest' boot parameter.
Signed-off-by: Christophe Leroy
---
The existing code sets portal IRQ affinity to CPU 0 in the
offline hotplug handler. If CPU 0 is offline this is invalid.
Use a different online CPU instead.
Signed-off-by: Madalin Bucur
---
drivers/soc/fsl/qbman/bman_portal.c | 4 +++-
drivers/soc/fsl/qbman/qman_portal.c | 6 --
2 files
Add call to early_memtest() so that kernel compiled with
CONFIG_MEMTEST really perform memtest at startup when requested
via 'memtest' boot parameter.
Signed-off-by: Christophe Leroy
---
v2: moved the test after initmem_init() as PPC64 sets max_low_pfn later than
PPC32.
This pulls out the assembler code that is responsible for saving and
restoring the PMU state for the host and guest into separate functions
so they can be used from an alternate entry path. The calling
convention is made compatible with C.
Reviewed-by: David Gibson
Signed-off-by: Paul Mackerras
From: Suraj Jitindar Singh
Add definition of the LPCR EVIRT (enhanced virtualisation) bit.
Reviewed-by: David Gibson
Signed-off-by: Suraj Jitindar Singh
Signed-off-by: Paul Mackerras
---
arch/powerpc/include/asm/reg.h | 1 +
1 file changed, 1 insertion(+)
diff --git
From: Suraj Jitindar Singh
When destroying a VM we return the LPID to the pool, however we never
zero the partition table entry. This is instead done when we reallocate
the LPID.
Zero the partition table entry on VM teardown before returning the LPID
to the pool. This means if we were running
On 28/9/18 4:38 pm, Alexey Kardashevskiy wrote:
The included opal.h gives a wrong idea that CXL makes PPC OPAL calls
while it does not so let's remote it.
Signed-off-by: Alexey Kardashevskiy
Thanks for catching this
Acked-by: Andrew Donnellan
---
drivers/misc/cxl/pci.c | 1 -
1 file
From: Roy Pledge
The QBMan block is memory mapped on SoCs above a 32 bit (4 Gigabyte)
boundary so enabling 64 bit DMA addressing is needed for QBMan to
be usuable.
Signed-off-by: Roy Pledge
Signed-off-by: Madalin Bucur
---
drivers/soc/fsl/qbman/Kconfig | 2 +-
1 file changed, 1 insertion(+),
Currently we use two bits in the vcpu pending_exceptions bitmap to
indicate that an external interrupt is pending for the guest, one
for "one-shot" interrupts that are cleared when delivered, and one
for interrupts that persist until cleared by an explicit action of
the OS (e.g. an acknowledge to
This removes code that clears the external interrupt pending bit in
the pending_exceptions bitmap. This is left over from an earlier
iteration of the code where this bit was set when an escalation
interrupt arrived in order to wake the vcpu from cede. Currently
we set the vcpu->arch.irq_pending
This streamlines the first part of the code that handles a hypervisor
interrupt that occurred in the guest. With this, all of the real-mode
handling that occurs is done before the "guest_exit_cont" label; once
we get to that label we are committed to exiting to host virtual mode.
Thus the machine
Currently kvmppc_handle_exit_hv() is called with the vcore lock held
because it is called within a for_each_runnable_thread loop.
However, we already unlock the vcore within kvmppc_handle_exit_hv()
under certain circumstances, and this is safe because (a) any vcpus
that become runnable and are
Currently the code for handling hypervisor instruction page faults
passes 0 for the flags indicating the type of fault, which is OK in
the usual case that the page is not mapped in the partition-scoped
page tables. However, there are other causes for hypervisor
instruction page faults, such as
From: Suraj Jitindar Singh
The radix page fault handler accounts for all cases, including just
needing to insert a pte. This breaks it up into separate functions for
the two main cases; setting rc and inserting a pte.
This allows us to make the setting of rc and inserting of a pte
generic for
This patch series implements nested virtualization in the KVM-HV
module for radix guests on POWER9 systems. Unlike PR KVM, nested
guests are able to run in supervisor mode, meaning that performance is
much better than with PR KVM, and is very close to the performance of
a non-nested guests for
This adds a parameter to __kvmppc_save_tm and __kvmppc_restore_tm
which allows the caller to indicate whether it wants the nonvolatile
register state to be preserved across the call, as required by the C
calling conventions. This parameter being non-zero also causes the
MSR bits that enable TM,
This adds a file called 'radix' in the debugfs directory for the
guest, which when read gives all of the valid leaf PTEs in the
partition-scoped radix tree for a radix guest, in human-readable
format. It is analogous to the existing 'htab' file which dumps
the HPT entries for a HPT guest.
From: Suraj Jitindar Singh
kvmppc_mmu_radix_xlate() is used to translate an effective address
through the process tables. The process table and partition tables have
identical layout. Exploit this fact to make the kvmppc_mmu_radix_xlate()
function able to translate either an effective address
From: Roy Pledge
Use the last valid response when determining what valid bit
to use next for management commands. This is needed in the
case that the portal was previously used by other software
like a bootloader or if the kernel is restarted without a
hardware reset.
Signed-off-by: Roy Pledge
Export the API required to control the QMan portal interrupt coalescing
settings.
Signed-off-by: Madalin Bucur
---
drivers/soc/fsl/qbman/qman.c | 31 +++
include/soc/fsl/qman.h | 27 +++
2 files changed, 58 insertions(+)
diff --git
This is based on a patch by Suraj Jitindar Singh.
This moves the code in book3s_hv_rmhandlers.S that generates an
external, decrementer or privileged doorbell interrupt just before
entering the guest to C code in book3s_hv_builtin.c. This is to
make future maintenance and modification easier.
This creates an alternative guest entry/exit path which is used for
radix guests on POWER9 systems when we have indep_threads_mode=Y. In
these circumstances there is exactly one vcpu per vcore and there is
no coordination required between vcpus or vcores; the vcpu can enter
the guest without
When the 'regs' field was added to struct kvm_vcpu_arch, the code
was changed to use several of the fields inside regs (e.g., gpr, lr,
etc.) but not the ccr field, because the ccr field in struct pt_regs
is 64 bits on 64-bit platforms, but the cr field in kvm_vcpu_arch is
only 32 bits. This
From: Roy Pledge
If the CPU to affine the portal interrupt is offline at boot time
affine the portal interrupt to another online CPU. If the CPU is later
brought online the hotplug handler will correctly adjust the affinity.
Moved common code in a function.
Signed-off-by: Roy Pledge
When doing nested virtualization, it is only necessary to do the
transactional memory hypervisor assist at level 0, that is, when
we are in hypervisor mode. Nested hypervisors can just use the TM
facilities as architected. Therefore we should clear the
CPU_FTR_P9_TM_HV_ASSIST bit when we are not
kvmppc_unmap_pte() does a sequence of operations that are open-coded in
kvm_unmap_radix(). This extends kvmppc_unmap_pte() a little so that it
can be used by kvm_unmap_radix(), and makes kvm_unmap_radix() call it.
Reviewed-by: David Gibson
Signed-off-by: Paul Mackerras
---
When we are running as a nested hypervisor, we use a hypercall to
enter the guest rather than code in book3s_hv_rmhandlers.S. This means
that the hypercall handlers listed in hcall_real_table never get called.
There are some hypercalls that are handled there and not in
kvmppc_pseries_do_hcall(),
From: Suraj Jitindar Singh
This is only done at level 0, since only level 0 knows which physical
CPU a vcpu is running on. This does for nested guests what L0 already
did for its own guests, which is to flush the TLB on a pCPU when it
goes to run a vCPU there, and there is another vCPU in the
From: Suraj Jitindar Singh
restore_hv_regs() is used to copy the hv_regs L1 wants to set to run the
nested (L2) guest into the vcpu structure. We need to sanitise these
values to ensure we don't let the L1 guest hypervisor do things we don't
want it to.
We don't let data address watchpoints or
Christophe LEROY writes:
> Le 27/09/2018 à 13:09, Michael Ellerman a écrit :
>> Christophe LEROY writes:
>>> Le 26/09/2018 à 13:11, Daniel Thompson a écrit :
On 16/09/2018 20:06, Daniel Thompson wrote:
> On Fri, Sep 14, 2018 at 12:35:44PM +, Christophe Leroy wrote:
>> On a
This starts the process of adding the code to support nested HV-style
virtualization. It defines a new H_SET_PARTITION_TABLE hypercall which
a nested hypervisor can use to set the base address and size of a
partition table in its memory (analogous to the PTCR register).
On the host (level 0
This adds code to call the H_IPI and H_EOI hypercalls when we are
running as a nested hypervisor (i.e. without the CPU_FTR_HVMODE cpu
feature) and we would otherwise access the XICS interrupt controller
directly or via an OPAL call.
Signed-off-by: Paul Mackerras
---
arch/powerpc/kvm/book3s_hv.c
From: Suraj Jitindar Singh
Consider a normal (L1) guest running under the main hypervisor (L0),
and then a nested guest (L2) running under the L1 guest which is acting
as a nested hypervisor. L0 has page tables to map the address space for
L1 providing the translation from L1 real address -> L0
This adds a one-reg register identifier which can be used to read and
set the virtual PTCR for the guest. This register identifies the
address and size of the virtual partition table for the guest, which
contains information about the nested guests under this guest.
Migrating this value is the
This adds a list of valid shadow PTEs for each nested guest to
the 'radix' file for the guest in debugfs. This can be useful for
debugging.
Reviewed-by: David Gibson
Signed-off-by: Paul Mackerras
---
arch/powerpc/include/asm/kvm_book3s_64.h | 1 +
arch/powerpc/kvm/book3s_64_mmu_radix.c |
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA512
Hi Greg,
Please pull some more powerpc fixes for 4.19:
The following changes since commit 11da3a7f84f19c26da6f86af878298694ede0804:
Linux 4.19-rc3 (2018-09-09 17:26:43 -0700)
are available in the git repository at:
Christophe LEROY writes:
> Le 27/09/2018 à 09:45, Segher Boessenkool a écrit :
>> On Thu, Sep 27, 2018 at 08:20:00AM +0200, Christophe LEROY wrote:
...
>>
>>> However this is the canary for initial startup only. Only idle() still
>>> uses this canary once the system is running. A new canary is
On 09/27/2018 10:52 PM, Michael Ellerman wrote:
> [ + linuxppc-dev ]
>
> Anders Roxell writes:
>> If the kernel headers aren't installed we can't build all the tests.
>> Add a new make target rule 'khdr' in the file lib.mk to generate the
>> kernel headers and that gets include for every
On Fri, Sep 28, 2018 at 12:21 PM Andreas Färber wrote:
>
> Hi Geert,
>
> Am 13.09.18 um 17:51 schrieb Geert Uytterhoeven:
> > On Wed, Sep 12, 2018 at 3:02 AM Masahiro Yamada
> > wrote:
> >> Even x86 can enable OF and OF_UNITTEST.
> >>
> >> Another solution might be,
> >> guard it by 'depends on
Hi,
Am Freitag, den 28.09.2018, 12:43 -0700 schrieb Frank Rowand:
> + Frank
>
> On 09/27/18 15:25, Li Yang wrote:
> > Hi Rob and Grant,
> >
> > Various device tree specs are recommending to include all the
> > potential compatible strings in the device node, with the order from
> > most
+ Frank
On 09/27/18 15:25, Li Yang wrote:
> Hi Rob and Grant,
>
> Various device tree specs are recommending to include all the
> potential compatible strings in the device node, with the order from
> most specific to most general. But it looks like Linux kernel doesn't
> provide a way to
On 09/21/2018 05:37 AM, YueHaibing wrote:
> find_aa_index will return -1 when dlpar_clone_property fails,
> its return value type should be int. Also the caller
> update_lmb_associativity_index should use a int variable to
> get it,then compared with 0.
The aa_index that we are handling here is
On Mon, Sep 24, 2018 at 7:51 AM Vabhav Sharma wrote:
>
> LX2160A reference design board (RDB) is a high-performance
> computing, evaluation, and development platform with LX2160A
> SoC.
Please send next version with Shawn Guo and me in the "to" recipient
so that its less likely we will miss it.
On Thu, Sep 27, 2018 at 5:25 PM Li Yang wrote:
>
> Hi Rob and Grant,
>
> Various device tree specs are recommending to include all the
> potential compatible strings in the device node, with the order from
> most specific to most general. But it looks like Linux kernel doesn't
> provide a way to
On 09/28/2018 02:02 AM, Gautham R Shenoy wrote:
> Hi Nathan,
>
> On Thu, Sep 27, 2018 at 12:31:34PM -0500, Nathan Fontenot wrote:
>> On 09/27/2018 11:51 AM, Gautham R. Shenoy wrote:
>>> From: "Gautham R. Shenoy"
>>>
>>> Live Partition Migrations require all the present CPUs to execute the
>>>
On Mon, Sep 24, 2018 at 7:47 AM Vabhav Sharma wrote:
>
> LX2160A SoC is based on Layerscape Chassis Generation 3.2 Architecture.
>
> LX2160A features an advanced 16 64-bit ARM v8 CortexA72 processor cores
> in 8 cluster, CCN508, GICv3,two 64-bit DDR4 memory controller, 8 I2C
> controllers, 3
Hi all,
This mailing list is now also archived at
https://lore.kernel.org/linuxppc-dev/
--
Cheers,
Stephen Rothwell
pgpCmQ1Stc07B.pgp
Description: OpenPGP digital signature
Hi all,
On Sat, 29 Sep 2018 13:56:28 +1000 Stephen Rothwell
wrote:
>
> This mailing list is now also archived at
> https://lore.kernel.org/linuxppc-dev/
A few of the earliest emails have been misdated in the archive (to today
or yesterday), sorry.
Also, this archive includes as much as we had
On Sat, 29 Sep 2018 11:26:07 +1000
Anton Blanchard wrote:
> If CONFIG_PPC_WATCHDOG is enabled, we always cap the decrementer to
> 0x7fff. As suggested by Nick, add a run time check of the watchdog
> cpumask, so if it is disabled we use the large decrementer.
>
> Signed-off-by: Anton
We currently cap the decrementer clockevent at 4 seconds, even on systems
with large decrementer support. Fix this by converting the code to use
clockevents_register_device() which calculates the upper bound based on
the max_delta passed in.
Signed-off-by: Anton Blanchard
---
If CONFIG_PPC_WATCHDOG is enabled, we always cap the decrementer to
0x7fff. As suggested by Nick, add a run time check of the watchdog
cpumask, so if it is disabled we use the large decrementer.
Signed-off-by: Anton Blanchard
---
arch/powerpc/kernel/time.c | 4 +++-
1 file changed, 3
Hi Anton,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on powerpc/next]
[also build test ERROR on v4.19-rc5 next-20180928]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci/linux
Hi Christophe,
> Add call to early_memtest() so that kernel compiled with
> CONFIG_MEMTEST really perform memtest at startup when requested
> via 'memtest' boot parameter.
>
This works for me on an e6500.
Tested-by: Daniel Axtens
However, you should also change
On Fri, 28 Sep 2018 at 07:43, Michael Ellerman wrote:
>
> Commit b2d35fa5fc80 ("selftests: add headers_install to lib.mk")
> introduced a requirement that Makefiles more than one level below the
> selftests directory need to define top_srcdir, but it didn't update
> any of the powerpc Makefiles.
How to/when to online hotplugged memory is hard to manage for
distributions because different memory types are to be treated differently.
Right now, we need complicated udev rules that e.g. check if we are
running on s390x, on a physical system or on a virtualized system. But
there is also
On Sun, Sep 23, 2018 at 06:31:14AM -0400, Masahiro Yamada wrote:
> 2018-09-13 11:51 GMT-04:00 Geert Uytterhoeven :
> > Hi Yamada-san,
> >
> > On Wed, Sep 12, 2018 at 3:02 AM Masahiro Yamada
> > wrote:
> >> 2018-09-12 0:40 GMT+09:00 Rob Herring :
> >> > On Mon, Sep 10, 2018 at 10:04 AM Rob Herring
On Fri, Sep 28, 2018 at 10:06:48AM +1000, Benjamin Herrenschmidt wrote:
> On Thu, 2018-09-27 at 15:49 +0200, Christoph Hellwig wrote:
> > On Thu, Sep 27, 2018 at 11:45:15AM +1000, Benjamin Herrenschmidt wrote:
> > > I'm not sure this is entirely right.
> > >
> > > Let's say the mask is 30 bits.
Add call to early_memtest() so that kernel compiled with
CONFIG_MEMTEST really perform memtest at startup when requested
via 'memtest' boot parameter.
Tested-by: Daniel Axtens
Signed-off-by: Christophe Leroy
---
v3: updated kernel parameters documentation to mention PPC
v2: moved the test
From: Suraj Jitindar Singh
When running a nested (L2) guest the guest (L1) hypervisor will use
hypervisor privileged tlb invalidation instructions (to manage the
partition scoped page tables) which will result in hypervisor
emulation assistance interrupts. We emulate these instructions on behalf
This adds a new hypercall, H_ENTER_NESTED, which is used by a nested
hypervisor to enter one of its nested guests. The hypercall supplies
register values in two structs. Those values are copied by the level 0
(L0) hypervisor (the one which is running in hypervisor mode) into the
vcpu struct of
From: Suraj Jitindar Singh
When a host (L0) page which is mapped into a (L1) guest is in turn
mapped through to a nested (L2) guest we keep a reverse mapping (rmap)
so that these mappings can be retrieved later.
Whenever we create an entry in a shadow_pgtable for a nested guest we
create a
From: Suraj Jitindar Singh
The hcall H_ENTER_NESTED takes as the two parameters the address in
L1 guest memory of a hv_regs struct and a pt_regs struct which the
L1 guest would like to use to run a L2 guest and in which are returned
the exit state of the L2 guest. For efficiency, these are in
With this, the KVM-HV module can be loaded in a guest running under
KVM-HV, and if the hypervisor supports nested virtualization, this
guest can now act as a nested hypervisor and run nested guests.
This also adds some checks to inform userspace that HPT guests are not
supported by nested
Christophe LEROY writes:
> Le 28/09/2018 à 05:41, Michael Ellerman a écrit :
>> Christophe Leroy writes:
>>> Add call to early_memtest() so that kernel compiled with
>>> CONFIG_MEMTEST really perform memtest at startup when requested
>>> via 'memtest' boot parameter.
>>>
>>> Signed-off-by:
From: Suraj Jitindar Singh
A HEAI (hypervisor emulation assistance interrupt) occurs when a
hypervisor resource or instruction is used in a privileged but
non-hypervisor state and the LPCR_EVIRT bit is set in LPCR. When
this occurs bit 45 is set in HSRR1. Detect the occurrence of this,
and if
When running as a nested hypervisor, this avoids reading hypervisor
privileged registers (specifically HFSCR, LPIDR and LPCR) at startup;
instead reasonable default values are used. This also avoids writing
LPIDR in the single-vcpu entry/exit path.
Also, this removes the check for CPU_FTR_HVMODE
This adds code to call the H_TLB_INVALIDATE hypercall when running as
a guest, in the cases where we need to invalidate TLBs (or other MMU
caches) as part of managing the mappings for a nested guest. Calling
H_TLB_INVALIDATE is an alternative to doing the tlbie instruction and
having it be
On Fri, 2018-09-28 at 05:43:23 UTC, Michael Ellerman wrote:
> Commit b2d35fa5fc80 ("selftests: add headers_install to lib.mk")
> introduced a requirement that Makefiles more than one level below the
> selftests directory need to define top_srcdir, but it didn't update
> any of the powerpc
Anders Roxell writes:
> On Fri, 28 Sep 2018 at 07:43, Michael Ellerman wrote:
>>
>> Commit b2d35fa5fc80 ("selftests: add headers_install to lib.mk")
>> introduced a requirement that Makefiles more than one level below the
>> selftests directory need to define top_srcdir, but it didn't update
>>
Alexey Kardashevskiy writes:
> The included opal.h gives a wrong idea that CXL makes PPC OPAL calls
> while it does not so let's remote it.
But it does use eg.
OPAL_PHB_CAPI_MODE_SNOOP_ON
OPAL_PHB_CAPI_MODE_CAPI
Which come from opal-api.h via opal.h.
So you should at least include
These are some fixes I've got so far to sovle hangs and multi hits
particularly on P8 with 256MB segments (but can also be reproduced
on P9).
I'm not yet sure these solve all the problems, and they need some
good review and testing. So far they have been solid for me.
Thanks,
Nick
Nicholas
struct pt_regs is part of the user ABI and also the fundametal
structure for saving registers at interrupt.
The generic kernel code makes it difficult to completely decouple
these, but it's easy enough to add additional space required to save
more registers. Create a struct int_stack with struct
In several places, more care has to be taken to prevent compiler or
CPU re-ordering of memory accesses into critical sections that must
not take SLB faults.
Fixes: 5e46e29e6a97 ("powerpc/64s/hash: convert SLB miss handlers to C")
Fixes: 89ca4e126a3f ("powerpc/64s/hash: Add a SLB preload cache")
PPR is the odd register out when it comes to interrupt handling,
it is saved in current->thread.ppr while all others are saved on
the stack.
The difficulty with this is that accessing thread.ppr can cause a
SLB fault, but the SLB fault handler implementation in C change had
assumed the normal
slb_setup_new_exec and preload_new_slb_context assumed if an address
missed the preload cache, then it would not be in the SLB and could
be added. This is wrong if the preload cache has started to overflow.
This can cause SLB multi-hits on user addresses.
That assumption came from an earlier
On Fri, Sep 28, 2018 at 10:56:07PM +1000, Michael Ellerman wrote:
> The problem of low entropy at boot on systems without a good hardware
> source is sort of unsolvable.
>
> As you say it's up to the core kernel/random code, we shouldn't be
> trying to do anything tricky in the arch code.
>
>
It's really nice if these kinds of things are broken up. First, replace
the old want_memblock parameter, then add the parameter to the
__add_page() calls.
> +/*
> + * NONE: No memory block is to be created (e.g. device memory).
> + * NORMAL: Memory block that represents normal (boot or
Hi Geert,
Am 13.09.18 um 17:51 schrieb Geert Uytterhoeven:
> On Wed, Sep 12, 2018 at 3:02 AM Masahiro Yamada
> wrote:
>> Even x86 can enable OF and OF_UNITTEST.
>>
>> Another solution might be,
>> guard it by 'depends on ARCH_SUPPORTS_OF'.
>>
>> This is actually what ACPI does.
>>
>> menuconfig
On Thu, Sep 27, 2018 at 06:52:21AM +, YueHaibing wrote:
> Use kmemdup rather than duplicating its implementation
>
> Signed-off-by: YueHaibing
Applied with Michael's ack to pci/hotplug for v4.20, thanks!
> ---
> drivers/pci/hotplug/pnv_php.c | 3 +--
> 1 file changed, 1 insertion(+), 2
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