With the strict dma mask checking introduced with the switch to
the generic DMA direct code common wifi chips on 32-bit powerbooks
stopped working. Add a 30-bit ZONE_DMA to the 32-bit pmac builds
to allow them to reliably allocate dma coherent memory.
Fixes: 65a21b71f948 ("powerpc/dma: remove
The CPM registers RCCR and CPMCR1..4 registers has to be set in
accordance with the microcode patch beeing programmed. Lets
define them as part of the patch set and refactor their
programming from that definition.
Signed-off-by: Christophe Leroy
---
arch/powerpc/platforms/8xx/micropatch.c | 45
The default DMA mode is PASSTHROUGH on powernv, this patch make it can be
set to STRICT at build time. It can be overridden by boot option.
There is no functional change.
Signed-off-by: Zhen Lei
---
arch/powerpc/platforms/powernv/pci-ioda.c | 3 ++-
drivers/iommu/Kconfig |
[ Upstream commit 2b8358a951b1e2a534a54924cd8245e58a1c5fb8 ]
The mpc85xx EDAC driver can be configured as a module but then fails to
build because it uses two unexported symbols:
ERROR: ".pci_find_hose_for_OF_device" [drivers/edac/mpc85xx_edac_mod.ko]
undefined!
ERROR:
Only 8xx selects CPM1 and related CONFIG options are already
in platforms/8xx/Kconfig
Move the related C files to platforms/8xx/.
Signed-off-by: Christophe Leroy
---
arch/powerpc/platforms/8xx/Makefile | 3 +++
arch/powerpc/{sysdev => platforms/8xx}/cpm1.c | 0
Define patch name together with the patch code, and refactor
the associated printk() while replacing it by a pr_info()
Signed-off-by: Christophe Leroy
---
arch/powerpc/platforms/8xx/micropatch.c | 14 --
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git
On 6/11/2019 5:39 PM, Christophe Leroy wrote:
> Next patch will require struct talitos_edesc to be defined
> earlier in talitos.c
>
> This patch moves it into talitos.h so that it can be used
> from any place in talitos.c
>
> Fixes: 37b5e8897eb5 ("crypto: talitos - chain in buffered data for
[ Upstream commit 2b8358a951b1e2a534a54924cd8245e58a1c5fb8 ]
The mpc85xx EDAC driver can be configured as a module but then fails to
build because it uses two unexported symbols:
ERROR: ".pci_find_hose_for_OF_device" [drivers/edac/mpc85xx_edac_mod.ko]
undefined!
ERROR:
Compact obscure microcode arrays by putting 4 values per line
in order to reduce number of lines in the file to increase
readability.
Signed-off-by: Christophe Leroy
---
arch/powerpc/platforms/8xx/micropatch.c | 699 +++-
1 file changed, 140 insertions(+), 559
The default DMA mode of AMD IOMMU is LAZY, this patch make it can be set
to STRICT at build time. It can be overridden by boot option.
There is no functional change.
Signed-off-by: Zhen Lei
---
drivers/iommu/Kconfig | 2 +-
drivers/iommu/amd_iommu_init.c | 2 +-
2 files changed, 2
The removal of CONFIG_LBDAF changed the type of sector_t from "unsigned
long" to "u64" aka "unsigned long long" on 64-bit platforms, leading to
a compiler warning regression:
drivers/block/ps3vram.c: In function ‘ps3vram_probe’:
drivers/block/ps3vram.c:770:23: warning: format ‘%lu’
Change microcode functions to use IO accessors and get rid
of volatile attributes.
Signed-off-by: Christophe Leroy
---
arch/powerpc/platforms/8xx/micropatch.c | 34 -
1 file changed, 16 insertions(+), 18 deletions(-)
diff --git
On 6/11/2019 5:39 PM, Christophe Leroy wrote:
> When building for SEC1 only, talitos2_done functions are unneeded
> and should go away.
>
> For this, use has_ftr_sec1() which will always return true when only
> SEC1 support is being built, allowing GCC to drop TALITOS2 functions.
>
>
v8--> v9
1. Fix some text editing errors
v7--> v8
1. Split into multiple small patches base on ARCHs or IOMMU drivers.
2. Hide the unsupported build options on the related ARCH or IOMMU.
v6 --> v7:
1. Fix some text editing errors
v5 --> v6:
1. give up adding boot option iommu.dma_mode
v4 -->
The default DMA mode of INTEL IOMMU is LAZY, this patch make it can be
set to STRICT at build time. It can be overridden by boot option.
There is no functional change.
Signed-off-by: Zhen Lei
---
drivers/iommu/Kconfig | 2 +-
drivers/iommu/intel-iommu.c | 2 +-
2 files changed, 2
Some SCC functions like the QMC requires an extended parameter RAM.
On modern 8xx (ie 866 and 885), SPI area can already be relocated,
allowing the use of those functions on SCC2. But SCC3 and SCC4
parameter RAM collide with SMC1 and SMC2 parameter RAMs.
This patch adds microcode to allow the
On 6/13/2019 3:16 PM, Christophe Leroy wrote:
>
>
> Le 13/06/2019 à 14:13, Horia Geanta a écrit :
>> On 6/11/2019 5:39 PM, Christophe Leroy wrote:
>>> Next patch will require struct talitos_edesc to be defined
>>> earlier in talitos.c
>>>
>>> This patch moves it into talitos.h so that it can be
Radu Rendec writes:
> Hi Everyone,
>
> I'm following up on the ptrace() problem that I reported a few days ago.
> I believe my version of the code handles all cases correctly. While the
> problem essentially boils down to dividing the fpidx by 2 on PPC32, it
> becomes tricky when the same code
First, add build option IOMMU_DEFAULT_{LAZY|STRICT}, so that we have the
opportunity to set {lazy|strict} mode as default at build time. Then put
the three config options in an choice, make people can only choose one of
the three at a time.
Signed-off-by: Zhen Lei
---
drivers/iommu/Kconfig | 44
Create a function to refactor the writing of CPM microcode arrays.
Signed-off-by: Christophe Leroy
---
arch/powerpc/platforms/8xx/micropatch.c | 35 -
1 file changed, 13 insertions(+), 22 deletions(-)
diff --git a/arch/powerpc/platforms/8xx/micropatch.c
Oops, I resent v1 together with v2. Sorry for the noise.
Le 13/06/2019 à 11:11, Christophe Leroy a écrit :
Only 8xx selects CPM1 and related CONFIG options are already
in platforms/8xx/Kconfig
This patch moves the related C files to platforms/8xx/.
Signed-off-by: Christophe Leroy
---
Architectures which support kprobes have very similar boilerplate around
calling kprobe_fault_handler(). Use a helper function in kprobes.h to unify
them, based on the x86 code.
This changes the behaviour for other architectures when preemption is
enabled. Previously, they would have disabled
On 6/11/2019 5:39 PM, Christophe Leroy wrote:
> icv_ool is not used anymore, drop it.
>
> Fixes: 9cc87bc3613b ("crypto: talitos - fix AEAD processing")
I can't find this SHA1.
Are you referring to commit e345177ded17 ("crypto: talitos - fix AEAD
processing.")?
Horia
Remove the ifdefs around CONFIG_IOMMU_DEFAULT_PASSTHROUGH to improve
readablity.
Signed-off-by: Zhen Lei
---
arch/x86/kernel/pci-dma.c | 6 +-
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/arch/x86/kernel/pci-dma.c b/arch/x86/kernel/pci-dma.c
index
verify_patch() has been opted out since many years, and
the comment suggests it doesn't work. So drop it.
Signed-off-by: Christophe Leroy
---
arch/powerpc/platforms/8xx/micropatch.c | 40 -
1 file changed, 40 deletions(-)
diff --git
[ Upstream commit 2b8358a951b1e2a534a54924cd8245e58a1c5fb8 ]
The mpc85xx EDAC driver can be configured as a module but then fails to
build because it uses two unexported symbols:
ERROR: ".pci_find_hose_for_OF_device" [drivers/edac/mpc85xx_edac_mod.ko]
undefined!
ERROR:
The DMA mode PASSTHROUGH is not used on ia64.
Signed-off-by: Zhen Lei
---
drivers/iommu/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/iommu/Kconfig b/drivers/iommu/Kconfig
index 70741fd73b07785..63506f1cad3d149 100644
--- a/drivers/iommu/Kconfig
+++
Add empty microcode tables so that all tables are defined
all the time. Regroup the writing of the 3 tables regardless
of the selected microcode.
Signed-off-by: Christophe Leroy
---
arch/powerpc/platforms/8xx/micropatch.c | 15 ++-
1 file changed, 6 insertions(+), 9 deletions(-)
On 6/13/19 1:30 AM, Geert Uytterhoeven wrote:
> The removal of CONFIG_LBDAF changed the type of sector_t from "unsigned
> long" to "u64" aka "unsigned long long" on 64-bit platforms, leading to
> a compiler warning regression:
>
> drivers/block/ps3vram.c: In function ‘ps3vram_probe’:
>
Le 13/06/2019 à 14:13, Horia Geanta a écrit :
On 6/11/2019 5:39 PM, Christophe Leroy wrote:
Next patch will require struct talitos_edesc to be defined
earlier in talitos.c
This patch moves it into talitos.h so that it can be used
from any place in talitos.c
Fixes: 37b5e8897eb5 ("crypto:
On 2019/5/31 18:42, John Garry wrote:
>
-config IOMMU_DEFAULT_PASSTHROUGH
- bool "IOMMU passthrough by default"
+choice
+ prompt "IOMMU default DMA mode"
depends on IOMMU_API
- help
- Enable passthrough by default, removing the need to
The default DMA mode is LAZY on s390, this patch make it can be set to
STRICT at build time. It can be overridden by boot option.
There is no functional change.
Signed-off-by: Zhen Lei
Acked-by: Sebastian Ott
---
arch/s390/pci/pci_dma.c | 2 +-
drivers/iommu/Kconfig | 2 ++
2 files changed,
Reduce #ifdef mess by using IS_ENABLED() instead.
Signed-off-by: Christophe Leroy
---
arch/powerpc/platforms/8xx/micropatch.c | 33 +
1 file changed, 13 insertions(+), 20 deletions(-)
diff --git a/arch/powerpc/platforms/8xx/micropatch.c
Daniel Axtens writes:
> Pawel Dembicki writes:
>
>> Enable kernel XZ compression option on PPC_85xx. Tested with
>> simpleImage on TP-Link TL-WDR4900 (Freescale P1014 processor).
>>
>> Suggested-by: Christian Lamparter
>> Signed-off-by: Pawel Dembicki
>> ---
>> arch/powerpc/Kconfig | 2 +-
>>
On 6/13/2019 3:32 PM, Christophe Leroy wrote:
>
>
> Le 13/06/2019 à 14:24, Horia Geanta a écrit :
>> On 6/13/2019 3:16 PM, Christophe Leroy wrote:
>>>
>>>
>>> Le 13/06/2019 à 14:13, Horia Geanta a écrit :
On 6/11/2019 5:39 PM, Christophe Leroy wrote:
> Next patch will require struct
On Thu, Jun 13, 2019 at 02:28:51PM +0200, Christophe Leroy wrote:
>
>
> Le 13/06/2019 à 14:21, Horia Geanta a écrit :
> > On 6/11/2019 5:39 PM, Christophe Leroy wrote:
> > > icv_ool is not used anymore, drop it.
> > >
> > > Fixes: 9cc87bc3613b ("crypto: talitos - fix AEAD processing")
> > I
Moves it into talitos.h so that it can be used
from any place in talitos.c
This will be required for next
patch ("crypto: talitos - fix hash on SEC1")
Signed-off-by: Christophe Leroy
---
drivers/crypto/talitos.c | 30 --
drivers/crypto/talitos.h | 30
Use r10 instead of r9 to calculate CPU offset as r9 contains
the value from SRR1 which is used later.
Fixes: 1a4b739bbb4f ("powerpc/32: implement fast entry for syscalls on BOOKE")
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_booke.h | 6 +++---
1 file changed, 3 insertions(+),
Le 13/06/2019 à 14:21, Horia Geanta a écrit :
On 6/11/2019 5:39 PM, Christophe Leroy wrote:
icv_ool is not used anymore, drop it.
Fixes: 9cc87bc3613b ("crypto: talitos - fix AEAD processing")
I can't find this SHA1.
Are you referring to commit e345177ded17 ("crypto: talitos - fix AEAD
Le 13/06/2019 à 14:24, Horia Geanta a écrit :
On 6/13/2019 3:16 PM, Christophe Leroy wrote:
Le 13/06/2019 à 14:13, Horia Geanta a écrit :
On 6/11/2019 5:39 PM, Christophe Leroy wrote:
Next patch will require struct talitos_edesc to be defined
earlier in talitos.c
This patch moves it
icv_ool is not used anymore, drop it.
Fixes: e345177ded17 ("crypto: talitos - fix AEAD processing.")
Signed-off-by: Christophe Leroy
---
drivers/crypto/talitos.c | 3 ---
drivers/crypto/talitos.h | 2 --
2 files changed, 5 deletions(-)
diff --git a/drivers/crypto/talitos.c
Hi Michael,
I wanted to check with you if you had time to have a look at my new version (v5)
of the patches with the fixed test, and if they are ready to be merged or if
there is anything else I can do.
Thanks and Regards,
Vincenzo
On 28/05/2019 12:57, Vincenzo Frascino wrote:
> Hi Michael,
>
When building for SEC1 only, talitos2_done functions are unneeded
and should go away.
For this, use has_ftr_sec1() which will always return true when only
SEC1 support is being built, allowing GCC to drop TALITOS2 functions.
Signed-off-by: Christophe Leroy
Reviewed-by: Horia Geantă
---
Le 13/06/2019 à 14:48, Christophe Leroy a écrit :
Moves it into talitos.h so that it can be used
from any place in talitos.c
This will be required for next
patch ("crypto: talitos - fix hash on SEC1")
Signed-off-by: Christophe Leroy
Cc: sta...@vger.kernel.org
---
This series is the last set of fixes for the Talitos driver.
We now get a fully clean boot on both SEC1 (SEC1.2 on mpc885) and
SEC2 (SEC2.2 on mpc8321E) with CONFIG_CRYPTO_MANAGER_EXTRA_TESTS:
[3.385197] bus: 'platform': really_probe: probing driver talitos with
device ff02.crypto
[
/linux/commits/Christophe-Leroy/powerpc-8xx-move-CPM1-related-files-from-sysdev-to-platforms-8xx/20190613-182651
base: https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git next
config: powerpc-ep8248e_defconfig (attached as .config)
compiler: powerpc-linux-gcc (GCC) 7.4.0
reproduce
On SEC1, hash provides wrong result when performing hashing in several
steps with input data SG list has more than one element. This was
detected with CONFIG_CRYPTO_MANAGER_EXTRA_TESTS:
[ 44.185947] alg: hash: md5-talitos test failed (wrong result) on test vector
6, cfg="random: may_sleep
Le 13/06/2019 à 14:39, Horia Geanta a écrit :
On 6/13/2019 3:32 PM, Christophe Leroy wrote:
Le 13/06/2019 à 14:24, Horia Geanta a écrit :
On 6/13/2019 3:16 PM, Christophe Leroy wrote:
Le 13/06/2019 à 14:13, Horia Geanta a écrit :
On 6/11/2019 5:39 PM, Christophe Leroy wrote:
Next
Sorry, there is a typo on my commit message.
's/BIT_MASK/BIT/'
On Thu, 2019-06-13 at 15:02 -0300, Leonardo Bras wrote:
> The main reason of this change is to make these bitmasks more readable.
>
> The macro ASM_CONST() just appends an UL to it's parameter, so it can be
> easily replaced by
On Thu, 13 Jun 2019 15:37:24 +0530 Anshuman Khandual
wrote:
> Architectures which support kprobes have very similar boilerplate around
> calling kprobe_fault_handler(). Use a helper function in kprobes.h to unify
> them, based on the x86 code.
>
> This changes the behaviour for other
On Wed, 15 May 2019 15:27:45 +0800, Xiaowei Bao wrote:
> Add the PCIe compatible string for LS1028A
>
> Signed-off-by: Xiaowei Bao
> ---
> .../devicetree/bindings/pci/layerscape-pci.txt |1 +
> 1 files changed, 1 insertions(+), 0 deletions(-)
>
Reviewed-by: Rob Herring
From: Claudio Carvalho
The X.509 certificates trusted by the platform and other information
required to secure boot the OS kernel are wrapped in secure variables,
which are controlled by OPAL. These variables are manipulated by
userspace tools using filesystem interface. This patch adds support
As part of PowerNV secure boot support, OS verification keys are stored
and controlled by OPAL as secure variables. These need to be exposed to
the userspace so that sysadmins can perform key management tasks.
This patch adds the support to expose secure variables via a sysfs
interface It reuses
On 6/12/19 1:32 AM, Naveen N. Rao wrote:
> Paul Clarke wrote:
>> What are the circumstances in which raw_syscalls:sys_exit reports "-1" for
>> the syscall ID?
>>
>> perf 5375 [007] 59632.478528: raw_syscalls:sys_enter: NR 1 (3,
>> 9fb888, 8, 2d83740, 1, 7)
>> perf 5375 [007]
On 6/13/19 4:00 PM, Paul Clarke wrote:
> On 6/12/19 1:32 AM, Naveen N. Rao wrote:
>> Paul Clarke wrote:
>>> What are the circumstances in which raw_syscalls:sys_exit reports "-1" for
>>> the syscall ID?
>>>
>>> perf 5375 [007] 59632.478528: raw_syscalls:sys_enter: NR 1 (3,
>>> 9fb888, 8,
On 06/12/2019 08:51 PM, Naveen N. Rao wrote:
> The first patch updates DIV64 overflow tests to properly detect error
> conditions. The second patch fixes powerpc64 JIT to generate the proper
> unsigned division instruction for BPF_ALU64.
>
> - Naveen
>
> Naveen N. Rao (2):
> bpf: fix div64
This patch set is part of a series that implements secure boot on PowerNV
systems[1]. The original series had been split into two patchsets:
1. powerpc: enable ima arch specific policies[2]
2. powerpc/powernv: expose secure variables to userspace, which is this
patchset.
Since there are major
Hello Nathan,
On Wed, Jun 12, 2019 at 10:19 AM Nathan Lynch wrote:
>
> CPU online/offline code paths are sensitive to parts of the device
> tree (various cpu node properties, cache nodes) that can be changed as
> a result of a migration.
>
> Prevent CPU hotplug while the device tree potentially
The main reason of this change is to make these bitmasks more readable.
The macro ASM_CONST() just appends an UL to it's parameter, so it can be
easily replaced by BIT_MASK, that already uses a UL representation.
ASM_CONST() in this file may behave different if __ASSEMBLY__ is defined,
as it is
On 6/13/19 3:24 AM, Christoph Hellwig wrote:
With the strict dma mask checking introduced with the switch to
the generic DMA direct code common wifi chips on 32-bit powerbooks
stopped working. Add a 30-bit ZONE_DMA to the 32-bit pmac builds
to allow them to reliably allocate dma coherent
Le 12/06/2019 à 17:54, Greg Kroah-Hartman a écrit :
When calling debugfs functions, there is no need to ever check the
return value. The function can work or not, but the code logic should
never do something different based on this.
Because there's no need to check, also make the return
On 6/13/2019 3:48 PM, Christophe Leroy wrote:
> On SEC1, hash provides wrong result when performing hashing in several
> steps with input data SG list has more than one element. This was
> detected with CONFIG_CRYPTO_MANAGER_EXTRA_TESTS:
>
> [ 44.185947] alg: hash: md5-talitos test failed
On Fri, 17 May 2019 10:47:47 +0800, Ran Wang wrote:
> By default, QorIQ SoC's RCPM register block is Big Endian. But
> there are some exceptions, such as LS1088A and LS2088A, are Little
> Endian. So add this optional property to help identify them.
>
> Actually LS2021A and other Layerscapes won't
> -Original Message-
> From: Rob Herring
> Sent: 2019年6月14日 5:00
> To: Xiaowei Bao
> Cc: bhelg...@google.com; robh...@kernel.org; mark.rutl...@arm.com;
> shawn...@kernel.org; Leo Li ; kis...@ti.com;
> lorenzo.pieral...@arm.com; a...@arndb.de; gre...@linuxfoundation.org;
> M.h. Lian ;
The pseries platform uses the PCI_PROBE_DEVTREE method of PCI probing
which is basically reading "assigned-addresses" of every PCI device.
However if the property is missing or zero sized, then there is
no fallback of any kind and the PCI resources remain undiscovered, i.e.
pdev->resource[] array
I'm seeing another asymmetry, this one is on powerpc:
--
perf 30179 [001] 10374622.667436: raw_syscalls:sys_enter: NR 11
(3fffe16ef55e, [...])
ls 30179 [002] 10374622.667921: raw_syscalls:sys_exit: NR 0 = 0
--
Syscall "11" is "execve", but is it expected that the sys_exit will report the
On Mon, 20 May 2019 17:52:37 +0800, Ran Wang wrote:
> By default, QorIQ SoC's RCPM register block is Big Endian. But
> there are some exceptions, such as LS1088A and LS2088A, are Little
> Endian. So add this optional property to help identify them.
>
> Actually LS2021A and other Layerscapes won't
From: Mauro Carvalho Chehab
On those three files, the ABI representation described at
README are violated.
- at sysfs-bus-iio-proximity-as3935:
a ':' character is missing after "What"
- at sysfs-class-devfreq:
there's a typo at Description
- at sysfs-class-cxl, it is using the
Nathan Lynch writes:
> Tyrel Datwyler writes:
>
>> Maybe we are ok with this behavior as I haven't dug deep enough into the
>> memory
>> subsystem here to really understand what the memory code is updating, but it
>> is
>> concerning that we are doing it in some cases, but not all.
>
> I hope
Greg,
As promised, I'm resending the patch series with adds the Kernel ABI to
Documentation/admin-guide.
Those patches are basically the version 3 patchset I sent back in 2017,
rebased on the top of linux-next (next-20190613), and with some fixes
in order for it to work.
- The 4 initial patches
On Wed, Jun 12, 2019 at 10:15 AM Nathan Lynch wrote:
>
> Allow external callers to force the cacheinfo code to release all its
> references to cache nodes, e.g. before processing device tree updates
> post-migration, and to rebuild the hierarchy afterward.
>
> CPU online/offline must be blocked
On Thu, Jun 13, 2019 at 07:59:51AM +1000, Benjamin Herrenschmidt wrote:
> > With the patch for Kconfig above, and the original patch setting
> > ARCH_ZONE_DMA_BITS to 30, everything works.
> >
> > Do you have any ideas on what should trigger the change in ARCH_ZONE_BITS?
> > Should it be
On 14/06/2019 12:59, Alexey Kardashevskiy wrote:
> The pseries platform uses the PCI_PROBE_DEVTREE method of PCI probing
> which is basically reading "assigned-addresses" of every PCI device.
> However if the property is missing or zero sized, then there is
> no fallback of any kind and the PCI
On 06/14/2019 01:34 AM, Andrew Morton wrote:
> On Thu, 13 Jun 2019 15:37:24 +0530 Anshuman Khandual
> wrote:
>
>> Architectures which support kprobes have very similar boilerplate around
>> calling kprobe_fault_handler(). Use a helper function in kprobes.h to unify
>> them, based on the x86
On Wed, Jun 12, 2019 at 10:17 AM Nathan Lynch wrote:
>
> It's common for the platform to replace the cache device nodes after a
> migration. Since the cacheinfo code is never informed about this, it
> never drops its references to the source system's cache nodes, causing
> it to wind up in an
Strict module RWX is just like strict kernel RWX, but for modules - so
loadable modules aren't marked both writable and executable at the same
time. This is handled by the generic code in kernel/module.c, and
simply requires the architecture to implement the set_memory() set of
functions,
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