[PATCH v5 3/3] PCI: layerscape: Add LS1028a support

2019-09-01 Thread Xiaowei Bao
Add support for the LS1028a PCIe controller. Signed-off-by: Xiaowei Bao Signed-off-by: Hou Zhiqiang --- v2: - No change. v3: - Reuse the ls2088 driver data structurt. v4: - No change. v5: - No change. drivers/pci/controller/dwc/pci-layerscape.c | 1 + 1 file changed, 1 insertion(+) diff -

[PATCH v5 2/3] arm64: dts: ls1028a: Add PCIe controller DT nodes

2019-09-01 Thread Xiaowei Bao
LS1028a implements 2 PCIe 3.0 controllers. Signed-off-by: Xiaowei Bao Signed-off-by: Hou Zhiqiang --- v2: - Fix up the legacy INTx allocate failed issue. v3: - No change. v4: - Remove the num-lanes property. v5: - Add the num-viewport property. arch/arm64/boot/dts/freescale/fsl-ls1028a.dts

[PATCH v5 1/3] dt-bindings: pci: layerscape-pci: add compatible strings "fsl, ls1028a-pcie"

2019-09-01 Thread Xiaowei Bao
Add the PCIe compatible string for LS1028A Signed-off-by: Xiaowei Bao Signed-off-by: Hou Zhiqiang Reviewed-by: Rob Herring --- v2: - No change. v3: - No change. v4: - No change. v5: - No change. Documentation/devicetree/bindings/pci/layerscape-pci.txt | 1 + 1 file changed, 1 insertion(+)

linux-next: manual merge of the powerpc tree with the arm64 tree

2019-09-01 Thread Stephen Rothwell
Hi all, Today's linux-next merge of the powerpc tree got a conflict in: arch/Kconfig between commit: 5cf896fb6be3 ("arm64: Add support for relocating the kernel with RELR relocations") from the arm64 tree and commit: 0c9c1d563975 ("x86, s390: Move ARCH_HAS_MEM_ENCRYPT definition to ar

RE: [PATCH] powerpc: Perform a bounds check in arch_add_memory

2019-09-01 Thread Alastair D'Silva
On Tue, 2019-08-27 at 09:13 +0200, David Hildenbrand wrote: > On 27.08.19 08:39, Alastair D'Silva wrote: > > On Tue, 2019-08-27 at 08:28 +0200, Michal Hocko wrote: > > > On Tue 27-08-19 15:20:46, Alastair D'Silva wrote: > > > > From: Alastair D'Silva > > > > > > > > It is possible for firmware to

Re: linux-next: manual merge of the powerpc tree with the arm64 tree

2019-09-01 Thread Michael Ellerman
Stephen Rothwell writes: > Hi all, > > Today's linux-next merge of the powerpc tree got a conflict in: > > arch/Kconfig > > between commit: > > 5cf896fb6be3 ("arm64: Add support for relocating the kernel with RELR > relocations") > > from the arm64 tree and commit: > > 0c9c1d563975 ("x86, s

RE: [RFC PATCH] powerpc: Convert ____flush_dcache_icache_phys() to C

2019-09-01 Thread Michael Ellerman
"Alastair D'Silva" writes: > On Wed, 2019-08-21 at 22:27 +0200, Christophe Leroy wrote: >> >> Le 20/08/2019 à 06:36, Alastair D'Silva a écrit : >> > On Fri, 2019-08-16 at 15:52 +, Christophe Leroy wrote: >> >> [...] >> >> > >> > Thanks Christophe, >> > >> > I'm trying a somewhat different

Re: [PATCH v7 5/6] powerpc/64: Make COMPAT user-selectable disabled on littleendian by default.

2019-09-01 Thread Michael Ellerman
Michal Suchanek writes: > On bigendian ppc64 it is common to have 32bit legacy binaries but much > less so on littleendian. I think the toolchain people will tell you that there is no 32-bit little endian ABI defined at all, if anything works it's by accident. So I think we should not make this

Re: [PATCH v6 6/6] powerpc/perf: split callchain.c by bitness

2019-09-01 Thread Michael Ellerman
Michal Suchánek writes: > On Fri, 30 Aug 2019 20:57:57 +0200 > Michal Suchanek wrote: > >> Building callchain.c with !COMPAT proved quite ugly with all the >> defines. Splitting out the 32bit and 64bit parts looks better. >> > > BTW the powerpc callchain.c does not match any of the patterns of P

Re: [PATCH v6 1/7] Documentation/powerpc: Ultravisor API

2019-09-01 Thread Michael Ellerman
On Thu, 2019-08-22 at 03:48:32 UTC, Claudio Carvalho wrote: > From: Sukadev Bhattiprolu > > Protected Execution Facility (PEF) is an architectural change for > POWER 9 that enables Secure Virtual Machines (SVMs). When enabled, > PEF adds a new higher privileged mode, called Ultravisor mode, to PO

Re: [PATCH kernel] KVM: PPC: Fix incorrect guest-to-user-translation error handling

2019-09-01 Thread Michael Ellerman
On Mon, 2019-08-26 at 04:55:20 UTC, Alexey Kardashevskiy wrote: > H_PUT_TCE_INDIRECT handlers receive a page with up to 512 TCEs from > a guest. Although we verify correctness of TCEs before we do anything > with the existing tables, there is a small window when a check in > kvmppc_tce_validate mig

Re: [PATCH v4 1/2] powerpc/powernv/opal-msglog: Refactor memcons code

2019-09-01 Thread Michael Ellerman
On Wed, 2019-08-28 at 13:05:20 UTC, Michael Ellerman wrote: > From: Claudio Carvalho > > This patch refactors the code in opal-msglog that operates on the OPAL > memory console in order to make it cleaner and also allow the reuse of > the new memcons_* functions. > > Signed-off-by: Claudio Carva

Re: [PATCH kernel v3 1/5] powerpc/powernv/ioda: Split out TCE invalidation from TCE updates

2019-09-01 Thread Michael Ellerman
On Thu, 2019-08-29 at 08:52:48 UTC, Alexey Kardashevskiy wrote: > At the moment updates in a TCE table are made by iommu_table_ops::exchange > which update one TCE and invalidates an entry in the PHB/NPU TCE cache > via set of registers called "TCE Kill" (hence the naming). > Writing a TCE is a sim

Re: [PATCH v2 1/2] powerpc: Add PowerPC Capabilities ELF note

2019-09-01 Thread Michael Ellerman
On Thu, 2019-08-29 at 15:50:20 UTC, "Maxiwell S. Garcia" wrote: > From: Claudio Carvalho > > Add the PowerPC name and the PPC_ELFNOTE_CAPABILITIES type in the > kernel binary ELF note. This type is a bitmap that can be used to > advertise kernel capabilities to userland. > > This patch also defi

Re: [PATCH v4 1/6] x86, s390: Move ARCH_HAS_MEM_ENCRYPT definition to arch/Kconfig

2019-09-01 Thread Michael Ellerman
On Tue, 2019-08-06 at 04:49:14 UTC, Thiago Jung Bauermann wrote: > powerpc is also going to use this feature, so put it in a generic location. > > Signed-off-by: Thiago Jung Bauermann > Reviewed-by: Thomas Gleixner > Reviewed-by: Christoph Hellwig Series applied to powerpc topic/mem-encrypt, t

[PATCH v3 00/11] *** SUBJECT HERE ***

2019-09-01 Thread Xiaowei Bao
*** BLURB HERE *** Xiaowei Bao (11): PCI: designware-ep: Add multiple PFs support for DWC PCI: designware-ep: Add the doorbell mode of MSI-X in EP mode PCI: designware-ep: Move the function of getting MSI capability forward PCI: designware-ep: Modify MSI and MSIX CAP way of finding d

[PATCH v3 02/11] PCI: designware-ep: Add the doorbell mode of MSI-X in EP mode

2019-09-01 Thread Xiaowei Bao
Add the doorbell mode of MSI-X in EP mode. Signed-off-by: Xiaowei Bao Reviewed-by: Andrew Murray --- v2: - Remove the macro of no used. v3: - No change. drivers/pci/controller/dwc/pcie-designware-ep.c | 14 ++ drivers/pci/controller/dwc/pcie-designware.h| 12 2 f

[PATCH v3 01/11] PCI: designware-ep: Add multiple PFs support for DWC

2019-09-01 Thread Xiaowei Bao
Add multiple PFs support for DWC, different PF have different config space we use pf-offset property which get from the DTS to access the different pF config space. Signed-off-by: Xiaowei Bao --- v2: - Remove duplicate redundant code. - Reimplement the PF config space access way. v3: - Integra

[PATCH v3 03/11] PCI: designware-ep: Move the function of getting MSI capability forward

2019-09-01 Thread Xiaowei Bao
Move the function of getting MSI capability to the front of init function, because the init function of the EP platform driver will use the return value by the function of getting MSI capability. Signed-off-by: Xiaowei Bao Reviewed-by: Andrew Murray --- v2: - No change. v3: - No change. driv

[PATCH v3 04/11] PCI: designware-ep: Modify MSI and MSIX CAP way of finding

2019-09-01 Thread Xiaowei Bao
Each PF of EP device should have it's own MSI or MSIX capabitily struct, so create a dw_pcie_ep_func struct and remover the msi_cap and msix_cap to this struce, and manage the PFs with a list. Signed-off-by: Xiaowei Bao --- v1: - This is a new patch, to fix the issue of MSI and MSIX CAP way of

[PATCH v3 05/11] dt-bindings: pci: layerscape-pci: add compatible strings for ls1088a and ls2088a

2019-09-01 Thread Xiaowei Bao
Add compatible strings for ls1088a and ls2088a. Signed-off-by: Xiaowei Bao --- v2: - No change. v3: - Use one valid combination of compatible strings. Documentation/devicetree/bindings/pci/layerscape-pci.txt | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/

[PATCH v3 06/11] PCI: layerscape: Fix some format issue of the code

2019-09-01 Thread Xiaowei Bao
Fix some format issue of the code in EP driver. Signed-off-by: Xiaowei Bao Reviewed-by: Andrew Murray --- v2: - No change. v3: - No change. drivers/pci/controller/dwc/pci-layerscape-ep.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-la

[PATCH v3 07/11] PCI: layerscape: Modify the way of getting capability with different PEX

2019-09-01 Thread Xiaowei Bao
The different PCIe controller in one board may be have different capability of MSI or MSIX, so change the way of getting the MSI capability, make it more flexible. Signed-off-by: Xiaowei Bao --- v2: - Remove the repeated assignment code. v3: - Use ep_func msi_cap and msix_cap to decide the msi_

[PATCH v3 08/11] PCI: layerscape: Modify the MSIX to the doorbell mode

2019-09-01 Thread Xiaowei Bao
dw_pcie_ep_raise_msix_irq was never called in the exisitng driver before, because the ls1046a platform don't support the MSIX feature and msix_capable was always set to false. Now that add the ls1088a platform with MSIX support, but the existing dw_pcie_ep_raise_msix_irq doesn't work, so use the do

[PATCH v3 09/11] PCI: layerscape: Add EP mode support for ls1088a and ls2088a

2019-09-01 Thread Xiaowei Bao
Add PCIe EP mode support for ls1088a and ls2088a, there are some difference between LS1 and LS2 platform, so refactor the code of the EP driver. Signed-off-by: Xiaowei Bao --- v2: - This is a new patch for supporting the ls1088a and ls2088a platform. v3: - Adjust the some struct assignment ord

[PATCH v3 10/11] arm64: dts: layerscape: Add PCIe EP node for ls1088a

2019-09-01 Thread Xiaowei Bao
Add PCIe EP node for ls1088a to support EP mode. Signed-off-by: Xiaowei Bao --- v2: - Remove the pf-offset proparty. v3: - No change. arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 31 ++ 1 file changed, 31 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/f

[PATCH v3 11/11] misc: pci_endpoint_test: Add LS1088a in pci_device_id table

2019-09-01 Thread Xiaowei Bao
Add LS1088a in pci_device_id table so that pci-epf-test can be used for testing PCIe EP in LS1088a. Signed-off-by: Xiaowei Bao --- v2: - No change. v3: - No change. drivers/misc/pci_endpoint_test.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/misc/pci_endpoint_test.c b/drivers

Re: [PATCH v2 01/44] powerpc/64s/exception: machine check fwnmi remove HV case

2019-09-01 Thread Michael Ellerman
On Fri, 2019-08-02 at 10:56:26 UTC, Nicholas Piggin wrote: > fwnmi does not trigger in HV mode, so remove always-true feature test. > > Signed-off-by: Nicholas Piggin Patches 1-36 applied to powerpc next, thanks. https://git.kernel.org/powerpc/c/0be9f7fd5d8fd984b34ad98838ef7cfd0079ddae cheers

Re: [PATCH] powerpc: use the generic dma coherent remap allocator

2019-09-01 Thread Michael Ellerman
On Wed, 2019-08-14 at 13:22:30 UTC, Christoph Hellwig wrote: > This switches to using common code for the DMA allocations, including > potential use of the CMA allocator if configured. > > Switching to the generic code enables DMA allocations from atomic > context, which is required by the DMA API

Re: [PATCH] powerpc/8xx: drop unused self-modifying code alternative to FixupDAR.

2019-09-01 Thread Michael Ellerman
On Wed, 2019-08-21 at 20:00:34 UTC, Christophe Leroy wrote: > The code which fixups the DAR on TLB errors for dbcX instructions > has a self-modifying code alternative that has never been used. > > Drop it. > > Signed-off-by: Christophe Leroy Applied to powerpc next, thanks. https://git.kernel

Re: [PATCH] powerpc/8xx: set STACK_END_MAGIC earlier on the init_stack

2019-09-01 Thread Michael Ellerman
On Wed, 2019-08-21 at 10:20:51 UTC, Christophe Leroy wrote: > Today, the STACK_END_MAGIC is set on init_stack in start_kernel(). > > To avoid a false 'Thread overran stack, or stack corrupted' message > on early Oopses, setup STACK_END_MAGIC as soon as possible. > > Signed-off-by: Christophe Lero

Re: [PATCH v4 02/16] powerpc/pseries: Introduce option to build secure virtual machines

2019-09-01 Thread Michael Ellerman
On Tue, 2019-08-20 at 02:13:12 UTC, Thiago Jung Bauermann wrote: > Introduce CONFIG_PPC_SVM to control support for secure guests and include > Ultravisor-related helpers when it is selected > > Signed-off-by: Thiago Jung Bauermann Patch 2-14 & 16 applied to powerpc next, thanks. https://git.ker

Re: [PATCH] powerpc/prom: convert PROM_BUG() to standard trap

2019-09-01 Thread Michael Ellerman
On Mon, 2019-08-26 at 11:10:23 UTC, Christophe Leroy wrote: > Prior to commit 1bd98d7fbaf5 ("ppc64: Update BUG handling based on > ppc32"), BUG() family was using BUG_ILLEGAL_INSTRUCTION which > was an invalid instruction opcode to trap into program check > exception. > > That commit converted the

Re: [PATCH 1/4] powerpc: convert to copy_thread_tls

2019-09-01 Thread Michael Ellerman
On Tue, 2019-08-27 at 03:30:06 UTC, Nicholas Piggin wrote: > Commit 3033f14ab78c3 ("clone: support passing tls argument via C rather > than pt_regs magic") introduced the HAVE_COPY_THREAD_TLS option. Use it > to avoid a subtle assumption about the argument ordering of clone type > syscalls. > > Si

Re: [PATCH 1/6] powerpc/32s: add an option to exclusively select powerpc 601

2019-09-01 Thread Michael Ellerman
On Mon, 2019-08-26 at 15:52:13 UTC, Christophe Leroy wrote: > Powerpc 601 is rather old powerpc which as some important > limitations compared to other book3s/32 powerpcs: > - No Timebase. > - Common BATs for instruction and data. > - No execution protection in segment registers. > - No RI bit in M

Re: [PATCH kernel v2] powerpc/of/pci: Rewrite pci_parse_of_flags

2019-09-01 Thread Michael Ellerman
On Thu, 2019-08-29 at 08:44:17 UTC, Alexey Kardashevskiy wrote: > The existing code uses bunch of hardcoded values from the PCI Bus Binding > to IEEE Std 1275 spec; and it does so in quite non-obvious way. > > This defines fields from the cell#0 of the "reg" property of a PCI device > and uses the

Re: [PATCH] powerpc/64s/exceptions: Use keyword params to shorten arg lists

2019-09-01 Thread Michael Ellerman
On Fri, 2019-08-30 at 01:14:26 UTC, Michael Ellerman wrote: > The argument lists for the INT_HANDLER macro are getting a bit > unwieldy. Use keyword parameters with default values to shorten them. > > Signed-off-by: Michael Ellerman Applied to powerpc next. https://git.kernel.org/powerpc/c/9b40

Re: [PATCH v2] powerpc/32: Add VDSO version of getcpu

2019-09-01 Thread kbuild test robot
Hi Christophe, Thank you for the patch! Yet something to improve: [auto build test ERROR on linus/master] [cannot apply to v5.3-rc6 next-20190830] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system] url: https://github.com/0day-ci/linux/commits

RE: [PATCH v3 00/11] *** SUBJECT HERE ***

2019-09-01 Thread Z.q. Hou
Xiaowei, > -Original Message- > From: Xiaowei Bao > Sent: 2019年9月2日 11:17 > To: robh...@kernel.org; mark.rutl...@arm.com; shawn...@kernel.org; > Leo Li ; kis...@ti.com; lorenzo.pieral...@arm.com; > M.h. Lian ; Mingkai Hu ; > Roy Zang ; jingooh...@gmail.com; > gustavo.pimen...@synopsys.com

Re: [PATCH v7 3/6] powerpc/perf: consolidate read_user_stack_32

2019-09-01 Thread Michael Ellerman
Michal Suchanek writes: > There are two almost identical copies for 32bit and 64bit. > > The function is used only in 32bit code which will be split out in next > patch so consolidate to one function. > > Signed-off-by: Michal Suchanek > Reviewed-by: Christophe Leroy > --- > new patch in v6 > -

[PATCH v6 1/3] dt-bindings: pci: layerscape-pci: add compatible strings "fsl, ls1028a-pcie"

2019-09-01 Thread Xiaowei Bao
Add the PCIe compatible string for LS1028A Signed-off-by: Xiaowei Bao Signed-off-by: Hou Zhiqiang Reviewed-by: Rob Herring --- v2: - No change. v3: - No change. v4: - No change. v5: - No change. v6: - No change. Documentation/devicetree/bindings/pci/layerscape-pci.txt | 1 + 1 file chang

[PATCH v6 2/3] arm64: dts: ls1028a: Add PCIe controller DT nodes

2019-09-01 Thread Xiaowei Bao
LS1028a implements 2 PCIe 3.0 controllers. Signed-off-by: Xiaowei Bao Signed-off-by: Hou Zhiqiang --- v2: - Fix up the legacy INTx allocate failed issue. v3: - No change. v4: - Remove the num-lanes property. v5: - Add the num-viewport property. v6: - move num-viewport to 8. arch/arm64/boo

[PATCH v6 3/3] PCI: layerscape: Add LS1028a support

2019-09-01 Thread Xiaowei Bao
Add support for the LS1028a PCIe controller. Signed-off-by: Xiaowei Bao Signed-off-by: Hou Zhiqiang --- v2: - No change. v3: - Reuse the ls2088 driver data structurt. v4: - No change. v5: - No change. v6: - No change. drivers/pci/controller/dwc/pci-layerscape.c | 1 + 1 file changed, 1 in

RE: [PATCH v3 00/11] *** SUBJECT HERE ***

2019-09-01 Thread Xiaowei Bao
> -Original Message- > From: Z.q. Hou > Sent: 2019年9月2日 11:52 > To: Xiaowei Bao ; robh...@kernel.org; > mark.rutl...@arm.com; shawn...@kernel.org; Leo Li > ; kis...@ti.com; lorenzo.pieral...@arm.com; M.h. Lian > ; Mingkai Hu ; Roy Zang > ; jingooh...@gmail.com; > gustavo.pimen...@synopsys

Re: [PATCH v7 3/6] powerpc/perf: consolidate read_user_stack_32

2019-09-01 Thread Michael Ellerman
Michael Ellerman writes: > Michal Suchanek writes: ... >> @@ -295,6 +279,12 @@ static inline int current_is_64bit(void) >> } >> >> #else /* CONFIG_PPC64 */ >> +static int read_user_stack_slow(void __user *ptr, void *buf, int nb) >> +{ >> +return 0; >> +} >> +#endif /* CONFIG_PPC64 */ > >

Re: [PATCH v2 5/9] s390: numa: check the node id consistently for s390

2019-09-01 Thread kbuild test robot
/Yunsheng-Lin/check-the-node-id-consistently-across-different-arches/20190901-143722 config: s390-allmodconfig (attached as .config) compiler: s390-linux-gcc (GCC) 7.4.0 reproduce: wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross

Re: [PATCH v2 2/9] x86: numa: check the node id consistently for x86

2019-09-01 Thread Yunsheng Lin
On 2019/9/1 0:12, Peter Zijlstra wrote: > On Sat, Aug 31, 2019 at 06:09:39PM +0800, Yunsheng Lin wrote: >> >> >> On 2019/8/31 16:55, Peter Zijlstra wrote: >>> On Sat, Aug 31, 2019 at 01:58:16PM +0800, Yunsheng Lin wrote: According to Section 6.2.14 from ACPI spec 6.3 [1], the setting of p

Re: [PATCH v2 7/9] sparc64: numa: check the node id consistently for sparc64

2019-09-01 Thread Yunsheng Lin
On 2019/9/1 4:02, David Miller wrote: > From: Yunsheng Lin > Date: Sat, 31 Aug 2019 16:57:04 +0800 > >> Did you mean sparc64 system does not has ACPI, the device's node id will >> not specified by ACPI, so the ACPI is unrelated here? > > Yes, sparc64 never has and never will have ACPI. > > This

Re: [PATCH v2 8/9] mips: numa: check the node id consistently for mips ip27

2019-09-01 Thread Yunsheng Lin
On 2019/8/31 23:45, Paul Burton wrote: > Hi Yunsheng, > > On Sat, Aug 31, 2019 at 01:58:22PM +0800, Yunsheng Lin wrote: >> According to Section 6.2.14 from ACPI spec 6.3 [1], the setting >> of proximity domain is optional, as below: >> >> This optional object is used to describe proximity domain >