On Tue, Sep 10, 2019 at 06:49:34PM +0200, Greg Kurz wrote:
> Each vCPU of a VM allocates a XIVE VP in OPAL which is associated with
> 8 event queue (EQ) descriptors, one for each priority. A POWER9 socket
> can handle a maximum of 1M event queues.
>
> The powernv platform allocates NR_CPUS (==
MQS (medium quality sound), is used to generate medium quality
audio via a standard digital output pin. It can be used to
connect stereo speakers or headphones simply via power amplifier
stages without an additional DAC chip. It only accepts 2-channel,
LSB-valid 16bit, MSB shift-out first, frame
Add the DT binding documentation for NXP MQS driver
Signed-off-by: Shengjiu Wang
---
.../devicetree/bindings/sound/fsl,mqs.txt | 20 +++
1 file changed, 20 insertions(+)
create mode 100644 Documentation/devicetree/bindings/sound/fsl,mqs.txt
diff --git
If a tracer sets the syscall number to an invalid one, allow the return
value set by the tracer to be returned the tracee.
The test for NR_syscalls is already at entry_64.S, and it's at
do_syscall_trace_enter only to skip audit and trace.
After this, seccomp_bpf selftests complete just fine, as
Nathan Lynch writes:
> Nathan Lynch writes:
>
>> I'm hoping for some help investigating a behavior I see when doing cpu
>> hotplug under load on P9 and P8 LPARs. Occasionally, while coming online
>> a cpu will seem to get "stuck" in idle, with a pending doorbell
>> interrupt unserviced (cpu 12
prep_irq_for_idle() is intended to be called before entering
H_CEDE (and it is used by the pseries cpuidle driver). However the
default pseries idle routine does not call it, leading to mismanaged
lazy irq state when the cpuidle driver isn't in use. Manifestations of
this include:
* Dropped IPIs
Quoting Michael Roth (2019-09-05 18:21:22)
> Quoting Michael Ellerman (2019-09-04 22:04:48)
> > That raises the question of whether this needs to be a full barrier or
> > just a write barrier, and where is the matching barrier on the reading
> > side?
>
> For this particular case I think the same
On Wed, Sep 11, 2019 at 04:30:38AM +1000, Michael Ellerman wrote:
> Nathan Chancellor writes:
> > On Wed, Sep 04, 2019 at 08:01:35AM -0500, Segher Boessenkool wrote:
> >> On Wed, Sep 04, 2019 at 08:16:45AM +, David Laight wrote:
> >> > From: Nathan Chancellor [mailto:natechancel...@gmail.com]
Nathan Chancellor writes:
> On Wed, Sep 04, 2019 at 08:01:35AM -0500, Segher Boessenkool wrote:
>> On Wed, Sep 04, 2019 at 08:16:45AM +, David Laight wrote:
>> > From: Nathan Chancellor [mailto:natechancel...@gmail.com]
>> > > Fair enough so I guess we are back to just outright disabling the
On 10/09/2019 15:53, Greg Kurz wrote:
> There's a bug in skiboot that causes the OPAL_XIVE_ALLOCATE_IRQ call
> to return the 32-bit value 0x when OPAL has run out of IRQs.
> Unfortunatelty, OPAL return values are signed 64-bit entities and
> errors are supposed to be negative. If that
Each vCPU of a VM allocates a XIVE VP in OPAL which is associated with
8 event queue (EQ) descriptors, one for each priority. A POWER9 socket
can handle a maximum of 1M event queues.
The powernv platform allocates NR_CPUS (== 2048) VPs for the hypervisor,
and each XIVE KVM device allocates
We can simply store the pages in a list (page->lru), no need for a
separate data structure (+ complicated handling). This is how most
other balloon drivers store allocated pages without additional tracking
data.
For the notifiers, use page_to_pfn() to check if a page is in the
applicable range.
arch/powerpc/kernel/ contains 8 files dedicated to kexec.
Move them into a dedicated subdirectory.
Signed-off-by: Christophe Leroy
---
v2: moved crash.c as well as it's part of kexec suite.
v3: renamed files to remove 'kexec' keyword from names.
---
arch/powerpc/kernel/Makefile
Almost half of misc_32.S is dedicated to kexec.
That's the relocation function for kexec.
Drop it into a dedicated kexec_relocate_32.S
Signed-off-by: Christophe Leroy
---
v2: no change
v3: renamed kexec_32.S to kexec_relocate_32.S
---
arch/powerpc/kernel/Makefile| 1 +
On 10/09/19 7:35 PM, Michael Ellerman wrote:
> Hari Bathini writes:
>> On 09/09/19 9:03 PM, Oliver O'Halloran wrote:
>>> On Mon, Sep 9, 2019 at 11:23 PM Hari Bathini wrote:
On 04/09/19 5:50 PM, Michael Ellerman wrote:
> Hari Bathini writes:
[...]
>> +/*
>> + * CPU
On Tue, Sep 10, 2019 at 02:55:27PM +, Christophe Leroy wrote:
> arch/powerpc/kernel/ contains 7 files dedicated to kexec.
>
> Move them into a dedicated subdirectory.
> arch/powerpc/kernel/{ => kexec}/ima_kexec.c| 0
> arch/powerpc/kernel/{ => kexec}/kexec_32.S | 2 +-
>
arch/powerpc/kernel/ contains 7 files dedicated to kexec.
Move them into a dedicated subdirectory.
Signed-off-by: Christophe Leroy
---
v2: moved crash.c as well as it's part of kexec suite.
---
arch/powerpc/kernel/Makefile | 19 +---
Almost half of misc_32.S is dedicated to kexec.
Drop it into a dedicated kexec_32.S
Signed-off-by: Christophe Leroy
---
v2: no change
---
arch/powerpc/kernel/Makefile | 1 +
arch/powerpc/kernel/kexec_32.S | 500 +
arch/powerpc/kernel/misc_32.S |
Almost half of misc_32.S is dedicated to kexec.
Drop it into a dedicated kexec_32.S
Signed-off-by: Christophe Leroy
---
v2: no change
---
arch/powerpc/kernel/Makefile | 1 +
arch/powerpc/kernel/kexec_32.S | 500 +
arch/powerpc/kernel/misc_32.S |
We want to throw out the attrbute if it refers to the mounted on fileid,
and not the real fileid. However we do not want to block cache consistency
updates from NFSv4 writes.
Reported-by: Murphy Zhou
Fixes: 7e10cc25bfa0 ("NFS: Don't refresh attributes with mounted-on-file...")
Signed-off-by:
Hi Qian,
Sorry I haven't replied sooner, I've been travelling.
Qian Cai writes:
> The commit 108c14858b9e ("locking/lockdep: Add support for dynamic
> keys") introduced a boot warning on powerpc below, because since the
> commit 2d4f567103ff ("KVM: PPC: Introduce kvm_tmp framework") adds
>
Hari Bathini writes:
> On 09/09/19 9:03 PM, Oliver O'Halloran wrote:
>> On Mon, Sep 9, 2019 at 11:23 PM Hari Bathini wrote:
>>> On 04/09/19 5:50 PM, Michael Ellerman wrote:
Hari Bathini writes:
>>> [...]
>>>
> +/*
> + * CPU state data is provided by f/w. Below are the definitions
There's a bug in skiboot that causes the OPAL_XIVE_ALLOCATE_IRQ call
to return the 32-bit value 0x when OPAL has run out of IRQs.
Unfortunatelty, OPAL return values are signed 64-bit entities and
errors are supposed to be negative. If that happens, the linux code
confusingly treats
The Linux kernel for powerpc since v4.15 has a bug in it's TM handling during
interrupts where any user can read the FP/VMX registers of a difference user's
process. Users of TM + FP/VMX can also experience corruption of their FP/VMX
state.
To trigger the bug, a process starts a transaction with
The Linux kernel for powerpc since v4.12 has a bug in it's TM handling where any
user can read the FP/VMX registers of a difference user's process. Users of TM +
FP/VMX can also experience corruption of their FP/VMX state.
To trigger the bug, a process starts a transaction and reads a FP/VMX
If watchpoint exception is generated by larx/stcx instructions, the
reservation created by larx gets lost while handling exception, and
thus stcx instruction always fails. Generally these instructions are
used in a while(1) loop, for example spinlocks. And because stcx
never succeeds, it loops
arch/powerpc/kernel/ contains 7 files dedicated to kexec.
Move them into a dedicated subdirectory.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/Makefile | 16 +---
arch/powerpc/kernel/kexec/Makefile | 22 ++
Almost half of misc_32.S is dedicated to kexec.
Drop it into a dedicated kexec_32.S
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/Makefile | 1 +
arch/powerpc/kernel/kexec_32.S | 500 +
arch/powerpc/kernel/misc_32.S | 491
Ravi Bangoria wrote:
If watchpoint exception is generated by larx/stcx instructions, the
reservation created by larx gets lost while handling exception, and
thus stcx instruction always fails. Generally these instructions are
used in a while(1) loop, for example spinlocks. And because stcx
never
Le 10/09/2019 à 12:24, Ravi Bangoria a écrit :
I've prepared my patch on top of Christophe's patch as it's easy
to change stepping_handler() rather than hw_breakpoint_handler().
2nd patch is the actual fix.
Anyway, my patch is already commited on powerpc/next
If watchpoint exception is generated by larx/stcx instructions, the
reservation created by larx gets lost while handling exception, and
thus stcx instruction always fails. Generally these instructions are
used in a while(1) loop, for example spinlocks. And because stcx
never succeeds, it loops
From: Christophe Leroy
On 8xx, breakpoints stop after executing the instruction, so
stepping/emulation is not needed. Move it into a sub-function and
remove the #ifdefs.
Signed-off-by: Christophe Leroy
Reviewed-by: Ravi Bangoria
---
arch/powerpc/kernel/hw_breakpoint.c | 60
I've prepared my patch on top of Christophe's patch as it's easy
to change stepping_handler() rather than hw_breakpoint_handler().
2nd patch is the actual fix.
Christophe Leroy (1):
powerpc/hw_breakpoint: move instruction stepping out of
hw_breakpoint_handler()
Ravi Bangoria (1):
On Tue, Sep 10, 2019 at 01:59:40PM +0530, Bharata B Rao wrote:
> +static struct page *kvmppc_uvmem_get_page(unsigned long *rmap,
> + unsigned long gpa, unsigned int lpid)
> +{
> + struct page *dpage = NULL;
> + unsigned long bit, uvmem_pfn;
> +
>
> With PFN_MODE_PMEM namespace, the memmap area is allocated from the device
> area. Some architectures map the memmap area with large page size. On
> architectures like ppc64, 16MB page for memap mapping can map 262144 pfns.
> This maps a namespace size of 16G.
>
> When populating memmap
A few changes to retrieve DAR and DSISR from struct regs
instead of retrieving them directly, as they may have
changed due to a TLB miss.
Also modifies hash_page() and friends to work with virtual
data addresses instead of physical ones.
Signed-off-by: Christophe Leroy
---
The part decidated to handling hash_page() is fully unneeded for
processors not having real hash pages like the 603.
Lets enlarge the content of the feature fixup, and provide
an alternative which jumps directly instead of getting NIPs.
Also, in preparation of VMAP stacks, the end of DSI handler
In preparation of handling CONFIG_VMAP_STACK, DTLB miss handler need
to use different scratch registers than other exception handlers in
order to not jeopardise exception entry on stack DTLB misses.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_8xx.S | 27
Move DataStoreTLBMiss perf handler in order to cope
with future growing exception prolog.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_8xx.S | 24
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/arch/powerpc/kernel/head_8xx.S
To support CONFIG_VMAP_STACK, the kernel has to activate Data MMU
Translation for accessing the stack. Before doing that it must save
SRR0, SRR1 and also DAR and DSISR when relevant, in order to not
loose them in case there is a Data TLB Miss once the translation is
reactivated.
This patch adds
In order to ease stack overflow detection, align
stack to 2 * THREAD_SIZE when using VMAP_STACK.
This allows overflow detection using a single bit check.
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/thread_info.h | 13 +
arch/powerpc/kernel/setup_32.c | 2 +-
Refactor reading and saving of DAR and DSISR in exception vectors.
This will ease the implementation of VMAP stack.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_32.S | 5 +
arch/powerpc/kernel/head_32.h | 11 +++
arch/powerpc/kernel/head_8xx.S | 23
This patch enables CONFIG_VMAP_STACK. For that, a few changes are
done in head_8xx.S.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_8xx.S | 34 --
arch/powerpc/platforms/Kconfig.cputype | 1 +
2 files changed, 29 insertions(+), 6
head_8xx.S has entries for all exceptions from 0x100 to 0x1f00.
Several of them do not exist and are never generated by the 8xx
in accordance with the documentation.
Remove those entry points to make some room for future growing
exception code.
Signed-off-by: Christophe Leroy
---
To avoid recursive faults, stack overflow detection has to be
performed before writing in the stack in exception prologs.
Do it by checking the alignment. If the stack pointer alignment is
wrong, it means it is pointing to the following or preceding page.
Without VMAP stack, a stack overflow is
Breakpoint exception is big.
Split it to support future growth on exception prolog.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_8xx.S | 19 ++-
1 file changed, 10 insertions(+), 9 deletions(-)
diff --git a/arch/powerpc/kernel/head_8xx.S
handle_page_fault() is the only function that save DAR/DEAR itself.
Save DAR/DEAR before calling handle_page_fault() to prepare for
VMAP stack which will require to save even before.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/entry_32.S | 1 -
arch/powerpc/kernel/head_32.S
On PPC32, MTMSRD() is simply defined as mtmsr.
Replace MTMSRD(reg) by mtmsr reg in files dedicated to PPC32,
this makes the code less obscure.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/entry_32.S | 18 +-
arch/powerpc/kernel/head_32.h | 4 ++--
2 files changed,
In order to simplify VMAP stack implementation, move
MSR_PR test into EXCEPTION_PROLOG_0.
This requires to not modify cr0 between EXCEPTION_PROLOG_0
and EXCEPTION_PROLOG_1.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_32.h | 4 ++--
arch/powerpc/kernel/head_8xx.S | 39
The purpose of this serie is to enable CONFIG_VMAP_STACK on PPC32.
rfc v1: initial support on 8xx
rfc v2: added stack overflow detection.
v3:
- Stack overflow detection works, tested with LKDTM STACK_EXHAUST test
- Support for book3s32 added
Christophe Leroy (15):
powerpc/32: replace
This patch creates a macro for the very first part of
exception prolog, this will help when implementing
CONFIG_VMAP_STACK
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_32.S | 4 +---
arch/powerpc/kernel/head_32.h | 9 ++---
arch/powerpc/kernel/head_8xx.S | 9 ++---
3
On Tue, Sep 10, 2019 at 1:31 AM Aneesh Kumar K.V
wrote:
>
> On 9/10/19 1:40 PM, Dan Williams wrote:
> > On Mon, Sep 9, 2019 at 11:29 PM Aneesh Kumar K.V
> > wrote:
> >>
> >> With PFN_MODE_PMEM namespace, the memmap area is allocated from the device
> >> area. Some architectures map the memmap
When looping on the list of interrupts, add the current value of the
PQ bits with a load on the ESB page. This has the side effect of
faulting the ESB page of all interrupts.
Signed-off-by: Cédric Le Goater
---
arch/powerpc/include/asm/xive.h | 3 +--
arch/powerpc/sysdev/xive/common.c | 29
When dumping the XIVE state of an CPU IPI, xmon does not check if the
CPU is started or not which can cause an error. Add a check for that
and change the output to be on one line just as the XIVE interrupts of
the machine.
Signed-off-by: Cédric Le Goater
---
arch/powerpc/sysdev/xive/common.c |
Hello,
This series extend the interrupt command output with the PQ bit value
and reworks the CPU command output to check that a CPU is started.
Thanks,
C.
Cédric Le Goater (2):
powerpc/xmon: Improve output of XIVE interrupts
powerpc/xmon: Fix output of XIVE IPI
On 09/09/19 9:03 PM, Oliver O'Halloran wrote:
> On Mon, Sep 9, 2019 at 11:23 PM Hari Bathini wrote:
>>
>> On 04/09/19 5:50 PM, Michael Ellerman wrote:
>>> Hari Bathini writes:
>>>
>>
>> [...]
>>
+/*
+ * CPU state data is provided by f/w. Below are the definitions
+ * provided
On 9/10/19 1:40 PM, Dan Williams wrote:
On Mon, Sep 9, 2019 at 11:29 PM Aneesh Kumar K.V
wrote:
With PFN_MODE_PMEM namespace, the memmap area is allocated from the device
area. Some architectures map the memmap area with large page size. On
architectures like ppc64, 16MB page for memap
From: Anshuman Khandual
CONFIG_PPC_UV adds support for ultravisor.
Signed-off-by: Anshuman Khandual
Signed-off-by: Bharata B Rao
Signed-off-by: Ram Pai
[ Update config help and commit message ]
Signed-off-by: Claudio Carvalho
---
arch/powerpc/Kconfig | 17 +
1 file changed,
Add support for reset of secure guest via a new ioctl KVM_PPC_SVM_OFF.
This ioctl will be issued by QEMU during reset and includes the
the following steps:
- Ask UV to terminate the guest via UV_SVM_TERMINATE ucall
- Unpin the VPA pages so that they can be migrated back to secure
side when
- After the guest becomes secure, when we handle a page fault of a page
belonging to SVM in HV, send that page to UV via UV_PAGE_IN.
- Whenever a page is unmapped on the HV side, inform UV via UV_PAGE_INVAL.
- Ensure all those routines that walk the secondary page tables of
the guest don't do
Register the new memslot with UV during plug and unregister
the memslot during unplug.
Signed-off-by: Bharata B Rao
Acked-by: Paul Mackerras
---
arch/powerpc/include/asm/ultravisor-api.h | 1 +
arch/powerpc/include/asm/ultravisor.h | 5 +
arch/powerpc/kvm/book3s_hv.c |
Manage migration of pages betwen normal and secure memory of secure
guest by implementing H_SVM_PAGE_IN and H_SVM_PAGE_OUT hcalls.
H_SVM_PAGE_IN: Move the content of a normal page to secure page
H_SVM_PAGE_OUT: Move the content of a secure page to normal page
Private ZONE_DEVICE memory equal to
H_SVM_INIT_START: Initiate securing a VM
H_SVM_INIT_DONE: Conclude securing a VM
As part of H_SVM_INIT_START, register all existing memslots with
the UV. H_SVM_INIT_DONE call by UV informs HV that transition of
the guest to secure mode is complete.
These two states (transition to secure mode
A secure guest will share some of its pages with hypervisor (Eg. virtio
bounce buffers etc). Support sharing of pages between hypervisor and
ultravisor.
Once a secure page is converted to shared page, the device page is
unmapped from the HV side page tables.
Signed-off-by: Bharata B Rao
---
From: Suraj Jitindar Singh
The rmap array in the guest memslot is an array of size number of guest
pages, allocated at memslot creation time. Each rmap entry in this array
is used to store information about the guest page to which it
corresponds. For example for a hpt guest it is used to store a
Hi,
A pseries guest can be run as a secure guest on Ultravisor-enabled
POWER platforms. On such platforms, this driver will be used to manage
the movement of guest pages between the normal memory managed by
hypervisor(HV) and secure memory managed by Ultravisor(UV).
Private ZONE_DEVICE memory
"Aneesh Kumar K.V" writes:
> With PFN_MODE_PMEM namespace, the memmap area is allocated from the device
> area. Some architectures map the memmap area with large page size. On
> architectures like ppc64, 16MB page for memap mapping can map 262144 pfns.
> This maps a namespace size of 16G.
>
>
On Mon, Sep 9, 2019 at 11:29 PM Aneesh Kumar K.V
wrote:
>
> With PFN_MODE_PMEM namespace, the memmap area is allocated from the device
> area. Some architectures map the memmap area with large page size. On
> architectures like ppc64, 16MB page for memap mapping can map 262144 pfns.
> This maps a
From: Michal Suchanek
Date: Mon, 9 Sep 2019 22:44:51 +0200
> Commit 1c2977c09499 ("net/ibmvnic: free reset work of removed device from
> queue")
> adds a } without corresponding { causing build break.
>
> Fixes: 1c2977c09499 ("net/ibmvnic: free reset work of removed device from
> queue")
>
* Linus Torvalds wrote:
> On Sat, Sep 7, 2019 at 10:42 AM Andy Lutomirski wrote:
> >
> > Linus, you rejected resolveat() because you wanted a *nice* API
>
> No. I rejected resoveat() because it was a completely broken garbage
> API that couldn't do even basic stuff right (like O_CREAT).
>
>
With PFN_MODE_PMEM namespace, the memmap area is allocated from the device
area. Some architectures map the memmap area with large page size. On
architectures like ppc64, 16MB page for memap mapping can map 262144 pfns.
This maps a namespace size of 16G.
When populating memmap region with 16MB
With commit: 7cc7867fb061 ("mm/devm_memremap_pages: enable sub-section remap")
pmem namespaces are remapped in 2M chunks. On architectures like ppc64 we
can map the memmap area using 16MB hugepage size and that can cover
a memory range of 16G.
While enabling new pmem namespaces, since memory is
When VMAP_STACK is selected, stack cannot be DMA-mapped.
Therefore, the hash result has to be DMA-mapped in the request
context and copied into areq->result at completion.
Signed-off-by: Christophe Leroy
---
drivers/crypto/talitos.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
Currently the reserved bits of the Processor Compatibility Register
(PCR) are cleared as per the Programming Note in Section 1.3.3 of
version 3.0B of the Power ISA. This causes all new architecture
features to be made available when running on newer processors with
new architecture features added
74 matches
Mail list logo
