On Fri, 2020-03-27 at 09:53:19 UTC, Michael Ellerman wrote:
> We added a usage of try-run to pmu/ebb/Makefile to detect if the
> toolchain supported the -no-pie option.
>
> This fails if we build out-of-tree and the source tree is not
> writable, as try-run tries to write its temporary files to
From: Vlastimil Babka
commit 0715e6c516f106ed553828a671d30ad9a3431536 upstream.
Sachin reports [1] a crash in SLUB __slab_alloc():
BUG: Kernel NULL pointer dereference on read at 0x73b0
Faulting instruction address: 0xc03d55f4
Oops: Kernel access of bad area, sig: 11 [#1]
On Sun, Mar 29, 2020 at 10:23 PM Alastair D'Silva wrote:
>
> This series adds support for OpenCAPI Persistent Memory devices on bare metal
> (arch/powernv), exposing them as nvdimms so that we can make use of the
> existing infrastructure. There already exists a driver for the same devices
>
On Sun, Mar 29, 2020 at 10:23 PM Alastair D'Silva wrote:
>
> Add OPAL calls for LPC memory alloc/release
>
This seems to be referencing an existing api definition, can you
include a pointer to the spec in case someone wanted to understand
what these routines do? I suspect this is not allocating
On Sun, Mar 29, 2020 at 10:23 PM Alastair D'Silva wrote:
>
> When setting up OpenCAPI connected persistent memory, the range check may
> not be performed until quite late (or perhaps not at all, if the user does
> not establish a DAX device).
>
> This patch makes the range check callable so we
On Sun, Mar 29, 2020 at 10:23 PM Alastair D'Silva wrote:
>
> This patch adds OPAL calls to powernv so that the OpenCAPI
> driver can map & release LPC (Lowest Point of Coherency) memory.
>
> Signed-off-by: Alastair D'Silva
> Reviewed-by: Andrew Donnellan
> ---
>
On Sun, Mar 29, 2020 at 10:23 PM Alastair D'Silva wrote:
>
> Function declarations don't need externs, remove the existing ones
> so they are consistent with newer code
>
> Signed-off-by: Alastair D'Silva
> Acked-by: Andrew Donnellan
> Acked-by: Frederic Barrat
Looks good.
> ---
>
On Sun, Mar 29, 2020 at 10:53 PM Alastair D'Silva wrote:
>
> OpenCAPI LPC memory is allocated per link, but each link supports
> multiple AFUs, and each AFU can have LPC memory assigned to it.
Is there an OpenCAPI primer to decode these objects and their
associations that I can reference?
>
>
On 4/1/20 12:33 PM, Christophe Leroy wrote:
Le 01/04/2020 à 08:12, Ravi Bangoria a écrit :
Introduce new parameter 'nr' to __set_breakpoint() which indicates
which DAWR should be programed. Also convert current_brk variable
to an array.
Signed-off-by: Ravi Bangoria
---
Le 01/04/2020 à 10:57, Ravi Bangoria a écrit :
On 4/1/20 12:33 PM, Christophe Leroy wrote:
Le 01/04/2020 à 08:12, Ravi Bangoria a écrit :
Introduce new parameter 'nr' to __set_breakpoint() which indicates
which DAWR should be programed. Also convert current_brk variable
to an array.
When we enter into fadump crash path via system reset we fail to update
the pstore.
On the system reset path we first update the pstore then we go for fadump
crash. But the problem here is when all the CPUs try to get the pstore
lock to initiate the pstore write, only one CPUs will acquire the
On 01. 04. 20 12:38, Takashi Iwai wrote:
> On Wed, 01 Apr 2020 12:35:16 +0200,
> Michael Ellerman wrote:
>>
>> Michal Simek writes:
>>> On 01. 04. 20 4:07, Michael Ellerman wrote:
Michal Simek writes:
> Hi,
>
> recently we wanted to update xilinx intc driver and we found that
On Sat, 2020-02-15 at 05:36:37 UTC, Leonardo Bras wrote:
> Before checking for cpu_type == NULL, this same copy happens, so doing
> it here will just write the same value to the t->oprofile_type
> again.
>
> Remove the repeated copy, as it is unnecessary.
>
> Signed-off-by: Leonardo Bras
On Thu, 2020-02-27 at 04:59:32 UTC, Michael Ellerman wrote:
> Relocatable kernel builds produce a warning about .gnu.hash being an
> orphan section:
>
> ld: warning: orphan section `.gnu.hash' from `linker stubs' being placed in
> section `.gnu.hash'
>
> If we try to discard it the build
In order to align with new ESARC, we add new property fsl,asrc-format.
The fsl,asrc-format can replace the fsl,asrc-width, driver
can accept format from devicetree, don't need to convert it to
format through width.
Signed-off-by: Shengjiu Wang
---
sound/soc/fsl/fsl-asoc-card.c | 21
Le 01/04/2020 à 11:13, Ravi Bangoria a écrit :
On 4/1/20 12:20 PM, Christophe Leroy wrote:
Le 01/04/2020 à 08:13, Ravi Bangoria a écrit :
Currently we assume that we have only one watchpoint supported by hw.
Get rid of that assumption and use dynamic loop instead. This should
make
Gautham R. Shenoy wrote:
From: "Gautham R. Shenoy"
Add documentation for the following sysfs interfaces:
/sys/devices/system/cpu/cpuX/purr
/sys/devices/system/cpu/cpuX/spurr
/sys/devices/system/cpu/cpuX/idle_purr
/sys/devices/system/cpu/cpuX/idle_spurr
Signed-off-by: Gautham R. Shenoy
---
On Wed, 01 Apr 2020 12:35:16 +0200,
Michael Ellerman wrote:
>
> Michal Simek writes:
> > On 01. 04. 20 4:07, Michael Ellerman wrote:
> >> Michal Simek writes:
> >>> Hi,
> >>>
> >>> recently we wanted to update xilinx intc driver and we found that function
> >>> which we wanted to remove is
Balamuruhan S wrote:
add testcases for divde, divde., divdeu, divdeu. emulated
instructions to cover few scenarios,
* with same dividend and divisor to have undefine RT
for divdeu[.]
* with divide by zero to have undefine RT for both
divde[.] and divdeu[.]
On Fri, 2020-02-28 at 00:14:37 UTC, Christophe Leroy wrote:
> In order to allow splitting of ptrace depending on the
> different CONFIG_ options, create a subdirectory dedicated to
> ptrace and move ptrace.c and ptrace32.c into it.
>
> Signed-off-by: Christophe Leroy
Series applied to powerpc
On Fri, 2020-03-20 at 10:32:42 UTC, "Aneesh Kumar K.V" wrote:
> As per ISA and isync is only needed on instruction cache
> block invalidate. Remove the same from dcache invalidate.
>
> Signed-off-by: Aneesh Kumar K.V
Applied to powerpc next, thanks.
On Sun, Mar 29, 2020 at 10:23 PM Alastair D'Silva wrote:
>
> This driver exposes LPC memory on OpenCAPI pmem cards
> as an NVDIMM, allowing the existing nvram infrastructure
> to be used.
>
> Namespace metadata is stored on the media itself, so
> scm_reserve_metadata() maps 1 section's worth of
In order to move common structure to fsl_asrc_common.h
we change the name of asrc_priv to asrc, the asrc_priv
will be used by new struct fsl_asrc_priv.
Signed-off-by: Shengjiu Wang
---
sound/soc/fsl/fsl_asrc.c | 298 +--
sound/soc/fsl/fsl_asrc.h | 4 +-
On Wed, Apr 01, 2020 at 04:45:34PM +0800, Shengjiu Wang wrote:
> In order to move common structure to fsl_asrc_common.h
> we change the name of asrc_priv to asrc, the asrc_priv
> will be used by new struct fsl_asrc_priv.
>
> Signed-off-by: Shengjiu Wang
Acked-by: Nicolin Chen
static void set_debug_reg_defaults(struct thread_struct *thread)
{
- thread->hw_brk.address = 0;
- thread->hw_brk.type = 0;
- thread->hw_brk.len = 0;
- thread->hw_brk.hw_len = 0;
- if (ppc_breakpoint_available())
- set_breakpoint(>hw_brk);
+ int i;
+
+ for (i =
On 4/1/20 12:02 PM, Christophe Leroy wrote:
Le 01/04/2020 à 08:13, Ravi Bangoria a écrit :
Instead of disabling only one watchpoint, get num of available
watchpoints dynamically and disable all of them.
Signed-off-by: Ravi Bangoria
---
arch/powerpc/include/asm/hw_breakpoint.h | 15
Le 31/03/2020 à 17:22, Christophe Leroy a écrit :
That's first try to port PPC64 syscall entry/exit logic in C to PPC32.
I've do the minimum to get it work. I have not reworked calls
to sys_fork() and friends for instance.
For the time being, it seems to work more or less but:
- ping reports
On Mon, 2019-11-25 at 09:20:33 UTC, Mike Rapoport wrote:
> From: Mike Rapoport
>
> The ISA_DMA_THRESHOLD variable is set by several platforms but never
> referenced.
> Remove it.
>
> Signed-off-by: Mike Rapoport
Applied to powerpc next, thanks.
On Sun, Mar 29, 2020 at 10:23 PM Alastair D'Silva wrote:
>
> This patch emits a message showing how much LPC memory & special purpose
> memory was detected on an OCXL device.
>
> Signed-off-by: Alastair D'Silva
> Acked-by: Frederic Barrat
> Acked-by: Andrew Donnellan
> ---
>
On Sun, Mar 29, 2020 at 10:23 PM Alastair D'Silva wrote:
>
> Add functions to map/unmap LPC memory
>
"map memory" is an overloaded term. I'm guessing this patch has
nothing to do with mapping memory in the MMU. Is it updating hardware
resource decoders to start claiming address space that was
There is a new ASRC included in i.MX serial platform, there
are some common definition can be shared with each other.
So move the common definition to a separate header file.
And add fsl_asrc_pair_priv and fsl_asrc_priv for
the variable specific for the module, which can be used
internally.
In order to align with new ESARC, we add new property fsl,asrc-format.
The fsl,asrc-format can replace the fsl,asrc-width, driver
can accept format from devicetree, don't need to convert it to
format through width.
Signed-off-by: Shengjiu Wang
---
sound/soc/fsl/fsl_asrc.c | 40
Gautham R. Shenoy wrote:
From: "Gautham R. Shenoy"
Currently purr, spurr, idle_purr, idle_spurr are exposed for every CPU
via the sysfs interface
/sys/devices/system/cpu/cpuX/[idle_][s]purr. Each sysfs read currently
generates an IPI to obtain the desired value from the target CPU X.
Since
Add new module driver for new ASRC in i.MX8MN, several commits
are added for new property fsl,asrc-format
Shengjiu Wang (7):
ASoC: fsl_asrc: rename asrc_priv to asrc
ASoC: dt-bindings: fsl_asrc: Add new property fsl,asrc-format
ASoC: fsl-asoc-card: Support new property fsl,asrc-format
EASRC (Enhanced Asynchronous Sample Rate Converter) is a new IP module
found on i.MX8MN. It is different with old ASRC module.
The primary features for the EASRC are as follows:
- 4 Contexts - groups of channels with an independent time base
- Fully independent and concurrent context control
-
On 4/1/20 2:50 PM, Christophe Leroy wrote:
Le 01/04/2020 à 11:13, Ravi Bangoria a écrit :
On 4/1/20 12:20 PM, Christophe Leroy wrote:
Le 01/04/2020 à 08:13, Ravi Bangoria a écrit :
Currently we assume that we have only one watchpoint supported by hw.
Get rid of that assumption and
On Tue, Mar 31, 2020 at 09:00:21PM -0300, Leonardo Bras wrote:
> During a crash, there is chance that the cpus that handle the NMI IPI
> are holding a spin_lock. If this spin_lock is needed by crashing_cpu it
> will cause a deadlock. (rtas.lock and printk logbuf_lock as of today)
>
> This is a
Hello Naveen,
On Wed, Apr 01, 2020 at 03:28:48PM +0530, Naveen N. Rao wrote:
> Gautham R. Shenoy wrote:
> >From: "Gautham R. Shenoy"
> >
[..snip..]
> >-static DEVICE_ATTR(spurr, 0400, show_spurr, NULL);
> >-static DEVICE_ATTR(purr, 0400, show_purr, store_purr);
> > static DEVICE_ATTR(pir,
On Fri, 2020-03-13 at 11:20:19 UTC, Michael Ellerman wrote:
> We don't need the NULL check of np, the result is the same because the
> OF helpers cope with NULL, of_node_to_nid(NULL) == NUMA_NO_NODE (-1).
>
> Signed-off-by: Michael Ellerman
Series applied to powerpc next.
On Sun, Mar 29, 2020 at 10:23 PM Alastair D'Silva wrote:
>
> This patch addresses warnings and errors from the kernel doc scripts for
> the OpenCAPI driver.
>
> It also makes minor tweaks to make the docs more consistent.
>
> Signed-off-by: Alastair D'Silva
> Acked-by: Andrew Donnellan
> ---
>
On 4/1/20 12:03 PM, Christophe Leroy wrote:
Le 01/04/2020 à 08:13, Ravi Bangoria a écrit :
Instead of disabling only first watchpoint, disable all available
watchpoints while clearing dawr_force_enable.
Can you also explain why you change the function name ?
Right. I should have. Will
Le 01/04/2020 à 11:11, Christophe Leroy a écrit :
Le 01/04/2020 à 10:57, Ravi Bangoria a écrit :
On 4/1/20 12:33 PM, Christophe Leroy wrote:
Le 01/04/2020 à 08:12, Ravi Bangoria a écrit :
Introduce new parameter 'nr' to __set_breakpoint() which indicates
which DAWR should be
Michal Simek writes:
> On 01. 04. 20 4:07, Michael Ellerman wrote:
>> Michal Simek writes:
>>> Hi,
>>>
>>> recently we wanted to update xilinx intc driver and we found that function
>>> which we wanted to remove is still wired by ancient Xilinx PowerPC
>>> platforms. Here is the thread about it.
In order to support new EASRC and simplify the code structure,
We decide to share the common structure between them. This bring
a problem that EASRC accept format directly from devicetree, but
ASRC accept width from devicetree.
In order to align with new ESARC, we add new property
On Fri, 2020-03-20 at 16:17 +1100, Jordan Niethe wrote:
> Currently unsigned ints are used to represent instructions on powerpc.
> This has worked well as instructions have always been 4 byte words.
> However, a future ISA version will introduce some changes to
> instructions that mean this scheme
On Wed, 2020-04-01 at 16:26 +0530, Naveen N. Rao wrote:
> Balamuruhan S wrote:
> > add testcases for divde, divde., divdeu, divdeu. emulated
> > instructions to cover few scenarios,
> > * with same dividend and divisor to have undefine RT
> > for divdeu[.]
> > * with
On Mon, 2019-08-12 at 21:50:43 UTC, Nick Desaulniers wrote:
> Reported-by: Sedat Dilek
> Suggested-by: Josh Poimboeuf
> Signed-off-by: Nick Desaulniers
Applied to powerpc next, thanks.
https://git.kernel.org/powerpc/c/a7032637b54186e5649917679727d7feaec932b1
cheers
On Tue, 2020-02-25 at 17:35:10 UTC, Nicholas Piggin wrote:
> The code generation macro arguments are difficult to read, and
> defaults can't easily be used.
>
> This introduces a block where parameters can be set for interrupt
> handler code generation by the subsequent macros, and adds the first
On Mon, 2020-02-24 at 23:31:39 UTC, Michael Ellerman wrote:
> A while back Paul pointed out I'd been maintaining the tree more or
> less solo for over five years, so perhaps it's time to update the
> MAINTAINERS entry.
>
> Ben & Paul still wrote most of the code, so keep them as Reviewers so
>
On Thu, 2020-03-05 at 14:35:29 UTC, "Naveen N. Rao" wrote:
> The original commit/discussion adding -fno-dwarf2-cfi-asm refers to
> R_PPC64_REL32 relocations not being handled by our module loader:
> http://lkml.kernel.org/r/20090224065112.ga6...@bombadil.infradead.org
>
> However, that is now
EASRC (Enhanced Asynchronous Sample Rate Converter) is a new
IP module found on i.MX8MN.
Signed-off-by: Shengjiu Wang
---
.../devicetree/bindings/sound/fsl,easrc.yaml | 101 ++
1 file changed, 101 insertions(+)
create mode 100644
On 4/1/20 12:20 PM, Christophe Leroy wrote:
Le 01/04/2020 à 08:13, Ravi Bangoria a écrit :
Currently we assume that we have only one watchpoint supported by hw.
Get rid of that assumption and use dynamic loop instead. This should
make supporting more watchpoints very easy.
With more than
On Tue, 2019-11-26 at 13:51:14 UTC, "Gautham R. Shenoy" wrote:
> From: Shilpasri G Bhat
>
> Commit bf9571550f52 ("powerpc/powernv: Add support to clear sensor
> groups data") added a mechanism to clear sensor-group data via a sysfs
> interface. However, the ABI for that interface has not been
>
> On 20-Mar-2020, at 1:27 AM, Jarkko Sakkinen
> wrote:
>
> On Wed, Mar 18, 2020 at 09:00:17PM -0400, Stefan Berger wrote:
>> From: Stefan Berger
>>
>> This patch fixes the following problem when the ibmvtpm driver
>> is built as a module:
>>
>> ERROR: modpost: "tpm2_get_cc_attrs_tbl"
Hi Gautham,
Gautham R. Shenoy wrote:
From: "Gautham R. Shenoy"
Currently when CPU goes idle, we take a snapshot of PURR via
pseries_idle_prolog() which is used at the CPU idle exit to compute
the idle PURR cycles via the function pseries_idle_epilog(). Thus,
the value of idle PURR cycle thus
On Fri, 2020-03-06 at 15:01:40 UTC, =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= wrote:
> When a CPU is brought up, an IPI number is allocated and recorded
> under the XIVE CPU structure. Invalid IPI numbers are tracked with
> interrupt number 0x0.
>
> On the PowerNV platform, the interrupt number space
On 01. 04. 20 4:07, Michael Ellerman wrote:
> Michal Simek writes:
>> Hi,
>>
>> recently we wanted to update xilinx intc driver and we found that function
>> which we wanted to remove is still wired by ancient Xilinx PowerPC
>> platforms. Here is the thread about it.
>>
So far, powerpc Book3S code has been written with an assumption of only
one watchpoint. But future power architecture is introducing second
watchpoint register (DAWR). Even though this patchset does not enable
2nd DAWR, it make the infrastructure ready so that enabling 2nd DAWR
should just be a
Future Power architecture is introducing second DAWR. Use real
register names from ISA for current macros:
s/SPRN_DAWR/SPRN_DAWR0/
s/SPRN_DAWRX/SPRN_DAWRX0/
Signed-off-by: Ravi Bangoria
---
arch/powerpc/include/asm/reg.h | 4 ++--
arch/powerpc/kernel/dawr.c | 4 ++--
Future Power architecture is introducing second DAWR. Add SPRN_ macros
for the same.
Signed-off-by: Ravi Bangoria
---
arch/powerpc/include/asm/reg.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index
So far we had only one watchpoint, so we have hardcoded HBP_NUM to 1.
But future Power architecture is introducing 2nd DAWR and thus kernel
should be able to dynamically find actual number of watchpoints
supported by hw it's running on. Introduce function for the same.
Also convert HBP_NUM macro
User can ask for num of available watchpoints(dbginfo.num_data_bps)
using ptrace(PPC_PTRACE_GETHWDBGINFO). Return actual number of
available watchpoints on the machine rather than hardcoded 1.
Signed-off-by: Ravi Bangoria
---
arch/powerpc/kernel/ptrace/ptrace-noadv.c | 2 +-
1 file changed, 1
Introduce new parameter 'nr' to set_dawr() which indicates which DAWR
should be programed.
Signed-off-by: Ravi Bangoria
---
arch/powerpc/include/asm/hw_breakpoint.h | 4 ++--
arch/powerpc/kernel/dawr.c | 15 ++-
arch/powerpc/kernel/process.c| 2 +-
3
Instead of disabling only one watchpoint, get num of available
watchpoints dynamically and disable all of them.
Signed-off-by: Ravi Bangoria
---
arch/powerpc/include/asm/hw_breakpoint.h | 15 +++
1 file changed, 7 insertions(+), 8 deletions(-)
diff --git
Introduce new parameter 'nr' to __set_breakpoint() which indicates
which DAWR should be programed. Also convert current_brk variable
to an array.
Signed-off-by: Ravi Bangoria
---
arch/powerpc/include/asm/debug.h | 2 +-
arch/powerpc/include/asm/hw_breakpoint.h | 2 +-
Instead of disabling only first watchpoint, disable all available
watchpoints while clearing dawr_force_enable.
Signed-off-by: Ravi Bangoria
---
arch/powerpc/kernel/dawr.c | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/kernel/dawr.c
Currently we assume that we have only one watchpoint supported by hw.
Get rid of that assumption and use dynamic loop instead. This should
make supporting more watchpoints very easy.
With more than one watchpoint, exception handler need to know which
DAWR caused the exception, and hw currently
Currently we calculate hw aligned start and end addresses manually.
Replace them with builtin ALIGN_DOWN() and ALIGN() macros.
Signed-off-by: Ravi Bangoria
---
arch/powerpc/include/asm/hw_breakpoint.h | 5 +++--
arch/powerpc/kernel/hw_breakpoint.c | 6 +++---
Add support for 2nd DAWR in xmon. With this, we can have two
simultaneous breakpoints from xmon.
Signed-off-by: Ravi Bangoria
---
arch/powerpc/xmon/xmon.c | 101 ++-
1 file changed, 69 insertions(+), 32 deletions(-)
diff --git a/arch/powerpc/xmon/xmon.c
Le 01/04/2020 à 08:12, Ravi Bangoria a écrit :
So far we had only one watchpoint, so we have hardcoded HBP_NUM to 1.
But future Power architecture is introducing 2nd DAWR and thus kernel
should be able to dynamically find actual number of watchpoints
supported by hw it's running on. Introduce
Le 01/04/2020 à 08:13, Ravi Bangoria a écrit :
Instead of disabling only first watchpoint, disable all available
watchpoints while clearing dawr_force_enable.
Can you also explain why you change the function name ?
Signed-off-by: Ravi Bangoria
---
arch/powerpc/kernel/dawr.c | 10
Le 01/04/2020 à 08:13, Ravi Bangoria a écrit :
Currently we assume that we have only one watchpoint supported by hw.
Get rid of that assumption and use dynamic loop instead. This should
make supporting more watchpoints very easy.
With more than one watchpoint, exception handler need to know
On 4/1/20 11:59 AM, Christophe Leroy wrote:
Le 01/04/2020 à 08:12, Ravi Bangoria a écrit :
So far we had only one watchpoint, so we have hardcoded HBP_NUM to 1.
But future Power architecture is introducing 2nd DAWR and thus kernel
should be able to dynamically find actual number of
Hi,
On Wed, Apr 01, 2020 at 01:42:27PM +0800, Baoquan He wrote:
> On 04/01/20 at 12:56am, Mike Rapoport wrote:
> > On Mon, Mar 30, 2020 at 11:58:43AM +0200, Michal Hocko wrote:
> > >
> > > What would it take to make ia64 use HAVE_MEMBLOCK_NODE_MAP? I would
> > > really love to see that thing go
Introduce is_ptrace_bp() function and move the check inside the
function. We will utilize it more in later set of patches.
Signed-off-by: Ravi Bangoria
---
arch/powerpc/kernel/hw_breakpoint.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git
ptrace_bps is already an array of size HBP_NUM_MAX. But we use
hardcoded index 0 while fetching/updating it. Convert such code
to loop over array.
Signed-off-by: Ravi Bangoria
---
arch/powerpc/kernel/hw_breakpoint.c | 7 --
arch/powerpc/kernel/process.c | 6 -
So far powerpc hw supported only one watchpoint. But Future Power
architecture is introducing 2nd DAWR. Convert thread_struct->hw_brk
into an array.
Signed-off-by: Ravi Bangoria
---
arch/powerpc/include/asm/processor.h | 2 +-
arch/powerpc/kernel/process.c | 61
With Book3s DAWR, ptrace and perf watchpoints on powerpc behaves
differently. Ptrace watchpoint works in one-shot mode and generates
signal before executing instruction. It's ptrace user's job to
single-step the instruction and re-enable the watchpoint. OTOH, in
case of perf watchpoint, kernel
Xmon allows overwriting breakpoints because it's supported by only
one dawr. But with multiple dawrs, overwriting becomes ambiguous
or unnecessary complicated. So let's not allow it.
Signed-off-by: Ravi Bangoria
---
arch/powerpc/xmon/xmon.c | 4
1 file changed, 4 insertions(+)
diff --git
Le 01/04/2020 à 08:13, Ravi Bangoria a écrit :
Instead of disabling only one watchpoint, get num of available
watchpoints dynamically and disable all of them.
Signed-off-by: Ravi Bangoria
---
arch/powerpc/include/asm/hw_breakpoint.h | 15 +++
1 file changed, 7 insertions(+),
Le 01/04/2020 à 08:13, Ravi Bangoria a écrit :
So far powerpc hw supported only one watchpoint. But Future Power
architecture is introducing 2nd DAWR. Convert thread_struct->hw_brk
into an array.
Signed-off-by: Ravi Bangoria
---
arch/powerpc/include/asm/processor.h | 2 +-
Le 01/04/2020 à 08:13, Ravi Bangoria a écrit :
With Book3s DAWR, ptrace and perf watchpoints on powerpc behaves
differently. Ptrace watchpoint works in one-shot mode and generates
signal before executing instruction. It's ptrace user's job to
single-step the instruction and re-enable the
Le 01/04/2020 à 08:12, Ravi Bangoria a écrit :
Introduce new parameter 'nr' to set_dawr() which indicates which DAWR
should be programed.
Signed-off-by: Ravi Bangoria
---
arch/powerpc/include/asm/hw_breakpoint.h | 4 ++--
arch/powerpc/kernel/dawr.c | 15 ++-
Le 01/04/2020 à 08:50, Ravi Bangoria a écrit :
On 4/1/20 11:59 AM, Christophe Leroy wrote:
Le 01/04/2020 à 08:12, Ravi Bangoria a écrit :
So far we had only one watchpoint, so we have hardcoded HBP_NUM to 1.
But future Power architecture is introducing 2nd DAWR and thus kernel
should be
Le 01/04/2020 à 08:12, Ravi Bangoria a écrit :
Introduce new parameter 'nr' to __set_breakpoint() which indicates
which DAWR should be programed. Also convert current_brk variable
to an array.
Signed-off-by: Ravi Bangoria
---
arch/powerpc/include/asm/debug.h | 2 +-
Subscribe to the MCE notification and add the physical address which
generated a memory error to nvdimm bad range.
Signed-off-by: Santosh Sivaraj
---
This patch depends on "powerpc/mce: Add MCE notification chain" [1].
Unlike the previous series[2], the patch adds badblock registration only
Hi Michael,
On Wed, Apr 1, 2020 at 2:53 PM Michael Ellerman
wrote:
>
> On Mon, 2019-08-12 at 21:50:43 UTC, Nick Desaulniers wrote:
> > Reported-by: Sedat Dilek
> > Suggested-by: Josh Poimboeuf
> > Signed-off-by: Nick Desaulniers
>
> Applied to powerpc next, thanks.
Missed this one from
From: Vlastimil Babka
commit 0715e6c516f106ed553828a671d30ad9a3431536 upstream.
Sachin reports [1] a crash in SLUB __slab_alloc():
BUG: Kernel NULL pointer dereference on read at 0x73b0
Faulting instruction address: 0xc03d55f4
Oops: Kernel access of bad area, sig: 11 [#1]
Balamuruhan S wrote:
Few ppc instructions are encoded in test_emulate_step.c, consolidate them to
ppc-opcode.h, fix redefintion errors in bpf_jit caused due to this
consolidation.
Reuse the macros from ppc-opcode.h
Signed-off-by: Balamuruhan S
---
arch/powerpc/include/asm/ppc-opcode.h | 34
On Thu, 2020-03-26 at 18:49:16 UTC, Ganesh Goudar wrote:
> memcpy_mcsafe has been implemented for power machines which is used
> by pmem infrastructure, so that an UE encountered during memcpy from
> pmem devices would not result in panic instead a right error code
> is returned. The
Free function kfree() already does NULL check, so the additional
check is unnecessary, just remove it.
Signed-off-by: Chen Zhou
---
arch/powerpc/kvm/book3s_hv_nested.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/arch/powerpc/kvm/book3s_hv_nested.c
From: Vlastimil Babka
commit 0715e6c516f106ed553828a671d30ad9a3431536 upstream.
Sachin reports [1] a crash in SLUB __slab_alloc():
BUG: Kernel NULL pointer dereference on read at 0x73b0
Faulting instruction address: 0xc03d55f4
Oops: Kernel access of bad area, sig: 11 [#1]
On Wed, 2020-03-25 at 10:41:44 UTC, Nicholas Piggin wrote:
> Before:
>
> WARNING: CPU: 0 PID: 494 at arch/powerpc/kernel/irq.c:343
> CPU: 0 PID: 494 Comm: a Tainted: GW
> NIP: c001ed2c LR: c0d13190 CTR: c003f910
> REGS: c001fffd3870 TRAP: 0700
On Mon, 2020-03-30 at 08:03:56 UTC, Clement Courbet wrote:
> Declaring setjmp()/longjmp() as taking longs makes the signature
> non-standard, and makes clang complain. In the past, this has been
> worked around by adding -ffreestanding to the compile flags.
>
> The implementation looks like it
'mem=" option is an easy way to put high pressure on memory during some
test. Hence after applying the memory limit, instead of total mem, the
actual usable memory should be considered when reserving mem for
crashkernel. Otherwise the boot up may experience OOM issue.
E.g. it would reserve 4G
On Thu, 2020-03-05 at 20:32 -0300, Leonardo Bras wrote:
> ---
> The new flag was already proposed on Power Architecture documentation,
> and it's waiting for approval.
>
> I would like to get your comments on this change, but it's still not
> ready for being merged.
New flag got approved on the
On Wed, 2020-03-25 at 16:42:57 UTC, Fangrui Song wrote:
> .globl sets the symbol binding to STB_GLOBAL while .weak sets the
> binding to STB_WEAK. GNU as let .weak override .globl since binutils-gdb
> 5ca547dc2399a0a5d9f20626d4bf5547c3ccfddd (1996). Clang integrated
> assembler let the last win
On Wed, 2020-04-01 at 02:38:36 UTC, Michael Ellerman wrote:
> In restore_tm_sigcontexts() we take the trap value directly from the
> user sigcontext with no checking:
>
> err |= __get_user(regs->trap, >gp_regs[PT_TRAP]);
>
> This means we can be in the kernel with an arbitrary regs->trap
The hv_24×7 feature in IBM® POWER9™ processor-based servers provide the
facility to continuously collect large numbers of hardware performance
metrics efficiently and accurately.
This patch adds hv_24x7 metric file for different Socket/chip
resources.
Result:
power9 platform:
command:# ./perf
With all hugetlb page processing done in a single file clean up code.
- Make code match desired semantics
- Update documentation with semantics
- Make all warnings and errors messages start with 'HugeTLB:'.
- Consistently name command line parsing routines.
- Check for hugepages_supported()
1 - 100 of 164 matches
Mail list logo
