Hi all,
flush_icache_range is mostly used for kernel address, except for the following
cases:
- the nommu brk and mmap implementations,
- the read_code helper that is only used for binfmt_flat, binfmt_elf_fdpic,
and binfmt_aout including the broken ia32 compat version
- binfmt_flat itself,
The arguments passed look bogus, try to fix them to something that seems
to make sense.
Signed-off-by: Christoph Hellwig
---
arch/arm/kernel/fiq.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/kernel/fiq.c b/arch/arm/kernel/fiq.c
index cd1234c103fcd..98ca3e3fa8
The second argument is the end "pointer", not the length.
Signed-off-by: Christoph Hellwig
---
arch/arm64/kernel/machine_kexec.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/kernel/machine_kexec.c
b/arch/arm64/kernel/machine_kexec.c
index 8e9c924423b4e..a0b144cfaea71 100644
--
__flush_icache_user_range is not used in modular code, so unexport it.
Signed-off-by: Christoph Hellwig
---
arch/mips/mm/cache.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/mips/mm/cache.c b/arch/mips/mm/cache.c
index 33b409391ddb6..ad6df1cea866f 100644
--- a/arch/mips/mm/cache.c
+++
flush_icache_page is only used by mm/memory.c.
Signed-off-by: Christoph Hellwig
---
arch/nds32/mm/cacheflush.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/nds32/mm/cacheflush.c b/arch/nds32/mm/cacheflush.c
index 254703653b6f5..8f168b33065fa 100644
--- a/arch/nds32/mm/cacheflush.c
+++
flush_icache_user_range is only used by copy_to_user_page, which is
only used by core VM code.
Signed-off-by: Christoph Hellwig
---
arch/powerpc/mm/mem.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/powerpc/mm/mem.c b/arch/powerpc/mm/mem.c
index 041ed7cfd341a..f0d1bf0a8e14f 100644
---
flush_cache_user_range is an ARMism not used by any generic or unicore32
specific code.
Signed-off-by: Christoph Hellwig
---
arch/unicore32/include/asm/cacheflush.h | 8
1 file changed, 8 deletions(-)
diff --git a/arch/unicore32/include/asm/cacheflush.h
b/arch/unicore32/include/asm/ca
cacheflush.h uses a somewhat to generic include guard name that clashes
with various arch files. Use a more specific one.
Signed-off-by: Christoph Hellwig
---
include/asm-generic/cacheflush.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/include/asm-generic/cacheflus
This seems to lead to some crazy include loops when using
asm-generic/cacheflush.h on more architectures, so leave it
to the arch header for now.
Signed-off-by: Christoph Hellwig
---
arch/um/include/asm/tlb.h | 2 ++
arch/x86/include/asm/cacheflush.h | 2 ++
include/asm-generic/cacheflus
There is a magic ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE cpp symbol that
guards non-stub availability of flush_dcache_pagge. Use that to
check if flush_dcache_pagg is implemented.
Signed-off-by: Christoph Hellwig
---
include/asm-generic/cacheflush.h | 6 +++---
1 file changed, 3 insertions(+), 3 dele
Alpha needs almost no cache flushing routines of its own. Rely on
asm-generic/cacheflush.h for the defaults.
Signed-off-by: Christoph Hellwig
---
arch/alpha/include/asm/cacheflush.h | 28 ++--
1 file changed, 6 insertions(+), 22 deletions(-)
diff --git a/arch/alpha/incl
ARM64 needs almost no cache flushing routines of its own. Rely on
asm-generic/cacheflush.h for the defaults.
Signed-off-by: Christoph Hellwig
---
arch/arm64/include/asm/cacheflush.h | 46 -
1 file changed, 5 insertions(+), 41 deletions(-)
diff --git a/arch/arm64/inc
C6x needs almost no cache flushing routines of its own. Rely on
asm-generic/cacheflush.h for the defaults.
Signed-off-by: Christoph Hellwig
---
arch/c6x/include/asm/cacheflush.h | 19 +--
1 file changed, 1 insertion(+), 18 deletions(-)
diff --git a/arch/c6x/include/asm/cacheflu
Hexagon needs almost no cache flushing routines of its own. Rely on
asm-generic/cacheflush.h for the defaults.
Signed-off-by: Christoph Hellwig
---
arch/hexagon/include/asm/cacheflush.h | 19 +--
1 file changed, 5 insertions(+), 14 deletions(-)
diff --git a/arch/hexagon/include
IA64 needs almost no cache flushing routines of its own. Rely on
asm-generic/cacheflush.h for the defaults.
Signed-off-by: Christoph Hellwig
---
arch/ia64/include/asm/cacheflush.h | 28 +++-
1 file changed, 3 insertions(+), 25 deletions(-)
diff --git a/arch/ia64/include
Microblaze needs almost no cache flushing routines of its own. Rely on
asm-generic/cacheflush.h for the defaults.
Signed-off-by: Christoph Hellwig
---
arch/microblaze/include/asm/cacheflush.h | 29 ++--
1 file changed, 2 insertions(+), 27 deletions(-)
diff --git a/arch/micr
m68knommu needs almost no cache flushing routines of its own. Rely on
asm-generic/cacheflush.h for the defaults.
Signed-off-by: Christoph Hellwig
---
arch/m68k/include/asm/cacheflush_no.h | 19 ++-
1 file changed, 2 insertions(+), 17 deletions(-)
diff --git a/arch/m68k/include/
OpenRISC needs almost no cache flushing routines of its own. Rely on
asm-generic/cacheflush.h for the defaults.
Signed-off-by: Christoph Hellwig
---
arch/openrisc/include/asm/cacheflush.h | 31 +-
1 file changed, 6 insertions(+), 25 deletions(-)
diff --git a/arch/openri
Power needs almost no cache flushing routines of its own. Rely on
asm-generic/cacheflush.h for the defaults.
Also remove the pointless __KERNEL__ ifdef while we're at it.
Signed-off-by: Christoph Hellwig
---
arch/powerpc/include/asm/cacheflush.h | 42 +++
1 file changed
RISC-V needs almost no cache flushing routines of its own. Rely on
asm-generic/cacheflush.h for the defaults.
Also remove the pointless __KERNEL__ ifdef while we're at it.
---
arch/riscv/include/asm/cacheflush.h | 62 ++---
1 file changed, 3 insertions(+), 59 deletions(-)
flush_icache_user_range is only used by , so
remove it from the architectures that implement it, but don't use
.
Signed-off-by: Christoph Hellwig
---
arch/arm/include/asm/cacheflush.h | 3 ---
arch/sparc/include/asm/cacheflush_32.h | 2 --
arch/sparc/include/asm/cacheflush_64.h | 1 -
ar
The function currently known as flush_icache_user_range only operates
on a single page. Rename it to flush_icache_user_page as we'll need
the name flush_icache_user_range for something else soon.
Signed-off-by: Christoph Hellwig
---
arch/alpha/include/asm/cacheflush.h| 10 +-
arch/a
Define flush_icache_user_range to flush_icache_range unless the
architecture provides its own implementation.
Signed-off-by: Christoph Hellwig
---
include/asm-generic/cacheflush.h | 4
1 file changed, 4 insertions(+)
diff --git a/include/asm-generic/cacheflush.h b/include/asm-generic/cache
The SuperH implementation of flush_icache_range seems to be able to
cope with user addresses. Just define flush_icache_user_range to
flush_icache_range.
Signed-off-by: Christoph Hellwig
---
arch/sh/include/asm/cacheflush.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/sh/include/asm/
The Xtensa implementation of flush_icache_range seems to be able to
cope with user addresses. Just define flush_icache_user_range to
flush_icache_range.
Signed-off-by: Christoph Hellwig
---
arch/xtensa/include/asm/cacheflush.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/xtensa/in
flush_icache_user_range will be the name for a generic primitive.
Move the arm name so that arm already has an implementation.
Signed-off-by: Christoph Hellwig
---
arch/arm/include/asm/cacheflush.h | 4 ++--
arch/arm/kernel/traps.c | 2 +-
2 files changed, 3 insertions(+), 3 deletions(
Rename the current flush_icache_range to flush_icache_user_range as
per commit ae92ef8a4424 ("PATCH] flush icache in correct context") there
seems to be an assumption that it operates on user addresses. Add a
flush_icache_range around it that for now is a no-op.
Signed-off-by: Christoph Hellwig
Only build read_code when binary formats that use it are built into the
kernel.
Signed-off-by: Christoph Hellwig
---
fs/exec.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/fs/exec.c b/fs/exec.c
index 06b4c550af5d9..a4f766f296f8f 100644
--- a/fs/exec.c
+++ b/fs/exec.c
@@ -1027,6 +1027,8
read_code operates on user addresses.
Signed-off-by: Christoph Hellwig
---
fs/exec.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/fs/exec.c b/fs/exec.c
index a4f766f296f8f..c541867316a63 100644
--- a/fs/exec.c
+++ b/fs/exec.c
@@ -1033,7 +1033,7 @@ ssize_t read_code(struct
load_flat_file works on user addresses.
Signed-off-by: Christoph Hellwig
---
fs/binfmt_flat.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/fs/binfmt_flat.c b/fs/binfmt_flat.c
index 831a2b25ba79f..6f0aca5379da2 100644
--- a/fs/binfmt_flat.c
+++ b/fs/binfmt_flat.c
@@ -854,7
These obviously operate on user addresses.
Signed-off-by: Christoph Hellwig
---
mm/nommu.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/mm/nommu.c b/mm/nommu.c
index 318df4e236c99..aed7acaed2383 100644
--- a/mm/nommu.c
+++ b/mm/nommu.c
@@ -443,7 +443,7 @@ SYSCALL_DEFIN
flush_icache_range generally operates on kernel addresses, but for some
reason m68k needed a set_fs override. Move that into the m68k code
insted of keeping it in the module loader.
Signed-off-by: Christoph Hellwig
---
arch/m68k/mm/cache.c | 4
kernel/module.c | 8
2 files ch
Hi Joe,
Joe Perches writes:
> On Fri, 2020-05-08 at 17:30 +0530, Vaibhav Jain wrote:
>> Hi Boris,
>>
>> Borislav Petkov writes:
>>
>> > On Fri, May 08, 2020 at 04:19:19PM +0530, Vaibhav Jain wrote:
>> > > 'seq_buf' provides a very useful abstraction for writing to a string
>> > > buffer witho
Hi Boris,
Borislav Petkov writes:
> On Fri, May 08, 2020 at 05:30:31PM +0530, Vaibhav Jain wrote:
>> I am referring to Kernel Loadable Modules with MODULE_LICENSE("GPL")
>> here.
>
> And what does "external" refer to? Because if it is out-of-tree, we
> don't export symbols for out-of-tree module
Michael Ellerman writes:
> Borislav Petkov writes:
>> On Fri, May 08, 2020 at 04:19:19PM +0530, Vaibhav Jain wrote:
>>> 'seq_buf' provides a very useful abstraction for writing to a string
>>> buffer without needing to worry about it over-flowing. However even
>>> though the API has been stable
Hi Santosh,
Thanks for the updated patch. Minor review comment below:
Santosh Sivaraj writes:
> Subscribe to the MCE notification and add the physical address which
> generated a memory error to nvdimm bad range.
>
> Reviewed-by: Mahesh Salgaonkar
> Signed-off-by: Santosh Sivaraj
> ---
> arc
> Remove duplicate memory allocation failure error messages.
Will another background information be relevant for the final commit message?
ps3: Delete an error message for a failed memory allocation in two functions
https://lore.kernel.org/linuxppc-dev/58807b28-b2b9-7e77-11b8-21db43c9d...@users.s
> Remove an extra message for a memory allocation failure in
> function gelic_descr_prepare_rx().
Will another background information be relevant for the final commit message?
ps3_gelic_net: Delete an error message for a failed memory allocation in
gelic_descr_prepare_rx()
https://lore.kernel.or
> Typical usage in the backend source file would be:
Is there any information missing in this change description accidentally?
Regards,
Markus
Hi,
On 2020-05-09 09:42, Christophe Leroy wrote:
> There are other clocks than the standard ones, for instance
> per process clocks. Therefore, being above the last standard clock
> doesn't mean it is a bad clock. So, fallback to syscall instead
> of returning -EINVAL inconditionaly.
>
> Fixes: e
To allow HVC backends to set the I/O buffer sizes to values
that are most efficient for the backend, change the macro
definitions where the buffer sizes are set to be conditional
on whether or not the macros are already defined. Also,
rename the macros from N_OUTBUF to HVC_N_OUBUF and from
N_INBUF
On Fri, May 8, 2020 at 5:17 PM Christophe Leroy
wrote:
>
>
>
> Le 08/05/2020 à 03:51, Jordan Niethe a écrit :
> > On Wed, May 6, 2020 at 1:45 PM Jordan Niethe wrote:
> >>
> >> Currently unsigned ints are used to represent instructions on powerpc.
> >> This has worked well as instructions have alw
Power10 is introducing second DAWR. Use real register names from ISA
for current macros:
s/SPRN_DAWR/SPRN_DAWR0/
s/SPRN_DAWRX/SPRN_DAWRX0/
Signed-off-by: Ravi Bangoria
Reviewed-by: Michael Neuling
---
arch/powerpc/include/asm/reg.h | 4 ++--
arch/powerpc/kernel/dawr.c
Power10 is introducing second DAWR. Add SPRN_ macros for the same.
Signed-off-by: Ravi Bangoria
Reviewed-by: Michael Neuling
---
arch/powerpc/include/asm/reg.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index 156ee89fa9b
So far, powerpc Book3S code has been written with an assumption of
only one watchpoint. But Power10[1] is introducing second watchpoint
register (DAWR). Even though this patchset does not enable 2nd DAWR,
it makes the infrastructure ready so that enabling 2nd DAWR should
just be a matter of changin
So far we had only one watchpoint, so we have hardcoded HBP_NUM to 1.
But Power10 is introducing 2nd DAWR and thus kernel should be able to
dynamically find actual number of watchpoints supported by hw it's
running on. Introduce function for the same. Also convert HBP_NUM macro
to HBP_NUM_MAX, whic
User can ask for num of available watchpoints(dbginfo.num_data_bps)
using ptrace(PPC_PTRACE_GETHWDBGINFO). Return actual number of
available watchpoints on the machine rather than hardcoded 1.
Signed-off-by: Ravi Bangoria
Reviewed-by: Michael Neuling
---
arch/powerpc/kernel/ptrace/ptrace-noadv.
Introduce new parameter 'nr' to set_dawr() which indicates which DAWR
should be programed.
Signed-off-by: Ravi Bangoria
Reviewed-by: Michael Neuling
---
arch/powerpc/include/asm/hw_breakpoint.h | 4 ++--
arch/powerpc/kernel/dawr.c | 15 ++-
arch/powerpc/kernel/process
Introduce new parameter 'nr' to __set_breakpoint() which indicates
which DAWR should be programed. Also convert current_brk variable
to an array.
Signed-off-by: Ravi Bangoria
Reviewed-by: Michael Neuling
---
arch/powerpc/include/asm/debug.h | 2 +-
arch/powerpc/include/asm/hw_breakpoin
Instead of disabling only one watchpoint, get num of available
watchpoints dynamically and disable all of them.
Signed-off-by: Ravi Bangoria
Reviewed-by: Michael Neuling
---
arch/powerpc/include/asm/hw_breakpoint.h | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --g
Instead of disabling only first watchpoint, disable all available
watchpoints while clearing dawr_force_enable.
Callback function is used only for disabling watchpoint, rename it
to disable_dawrs_cb(). And null_brk parameter is not really required
while disabling watchpoint, remove it.
Signed-off
So far powerpc hw supported only one watchpoint. But Power10 is
introducing 2nd DAWR. Convert thread_struct->hw_brk into an array.
Signed-off-by: Ravi Bangoria
Reviewed-by: Michael Neuling
---
arch/powerpc/include/asm/processor.h | 2 +-
arch/powerpc/kernel/process.c | 60
ptrace_bps is already an array of size HBP_NUM_MAX. But we use
hardcoded index 0 while fetching/updating it. Convert such code
to loop over array.
ptrace interface to use multiple watchpoint remains same. eg:
two PPC_PTRACE_SETHWDEBUG calls will create two watchpoint if
underneath hw supports it.
Introduce is_ptrace_bp() function and move the check inside the
function. It will be utilize more in later set of patches.
Signed-off-by: Ravi Bangoria
Reviewed-by: Michael Neuling
---
arch/powerpc/kernel/hw_breakpoint.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/
Currently we calculate hw aligned start and end addresses manually.
Replace them with builtin ALIGN_DOWN() and ALIGN() macros.
So far end_addr was inclusive but this patch makes it exclusive (by
avoiding -1) for better readability.
Suggested-by: Christophe Leroy
Signed-off-by: Ravi Bangoria
Rev
Currently we assume that we have only one watchpoint supported by hw.
Get rid of that assumption and use dynamic loop instead. This should
make supporting more watchpoints very easy.
With more than one watchpoint, exception handler needs to know which
DAWR caused the exception, and hw currently do
With Book3s DAWR, ptrace and perf watchpoints on powerpc behaves
differently. Ptrace watchpoint works in one-shot mode and generates
signal before executing instruction. It's ptrace user's job to
single-step the instruction and re-enable the watchpoint. OTOH, in
case of perf watchpoint, kernel emul
Xmon allows overwriting breakpoints because it's supported by only
one DAWR. But with multiple DAWRs, overwriting becomes ambiguous
or unnecessary complicated. So let's not allow it.
Signed-off-by: Ravi Bangoria
Reviewed-by: Michael Neuling
---
arch/powerpc/xmon/xmon.c | 4
1 file changed,
Add support for 2nd DAWR in xmon. With this, we can have two
simultaneous breakpoints from xmon.
Signed-off-by: Ravi Bangoria
Reviewed-by: Michael Neuling
---
arch/powerpc/xmon/xmon.c | 101 ++-
1 file changed, 69 insertions(+), 32 deletions(-)
diff --git a/
On 05/09/2020 03:52 AM, Mike Kravetz wrote:
> On 5/7/20 8:07 PM, Anshuman Khandual wrote:
>> There are multiple similar definitions for is_hugepage_only_range() on
>> various platforms. Lets just add it's generic fallback definition for
>> platforms that do not override. This help reduce code du
Hi Mike,
On 08.05.2020 19:42, Mike Rapoport wrote:
> On Fri, May 08, 2020 at 08:53:27AM +0200, Marek Szyprowski wrote:
>> On 07.05.2020 18:11, Mike Rapoport wrote:
>>> On Thu, May 07, 2020 at 02:16:56PM +0200, Marek Szyprowski wrote:
On 14.04.2020 17:34, Mike Rapoport wrote:
> From: Mike
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