Michael Ellerman writes:
> Christophe Leroy writes:
>> Hi Michael,
>>
>> I see this patch is marked as "defered" in patchwork, but I can't see
>> any related discussion. Is it normal ?
>
> Because it uses the "m<>" constraint which didn't work on GCC 4.6.
>
>
Joel Stanley writes:
> It's not done anything for a long time. Save the percpu variable, and
> emit a warning to remind users to not expect it to do anything.
>
> Signed-off-by: Joel Stanley
> ---
> arch/powerpc/kernel/sysfs.c | 41 +
> 1 file changed, 14
On Mon, Jun 29, 2020 at 6:58 AM Aneesh Kumar K.V
wrote:
>
> We only support persistent memory on P8 and above. This is enforced by the
> firmware and further checked on virtualzied platform during platform init.
> Add WARN_ONCE in pmem flush routines to catch the wrong usage of these.
>
>
On 06/29/2020 01:55 PM, Hari Bathini wrote:
>
>
> On 28/06/20 7:44 am, piliu wrote:
>> Hi Hari,
>
> Hi Pingfan,
>
>>
>> After a quick through for this series, I have a few question/comment on
>> this patch for the time being. Pls see comment inline.
>>
>> On 06/27/2020 03:05 AM, Hari
VSX vector paired instructions operates with octword (32-byte) operand
for loads and stores between storage and a pair of two sequential Vector-Scalar
Registers (VSRs). There are 4 word instructions and 2 prefixed instructions
that provides this 32-byte storage access operations - lxvp, lxvpx,
On Mon, 29 Jun 2020 at 10:42, Gautham R Shenoy wrote:
>
> On Thu, Jun 25, 2020 at 07:33:49PM +0930, Joel Stanley wrote:
> > It's not done anything for a long time. Save the percpu variable, and
> > emit a warning to remind users to not expect it to do anything.
> >
> > Signed-off-by: Joel Stanley
On Sun, Jun 28, 2020 at 01:04:28AM +1000, Nicholas Piggin wrote:
> KVM guests have certain restrictions and performance quirks when
> using doorbells. This patch tests for KVM environment in doorbell
> setup, and optimises IPI performance:
>
> - PowerVM guests may now use doorbells even if they
On 06/24/2020 08:43 AM, Anshuman Khandual wrote:
>
>
> On 06/15/2020 09:07 AM, Anshuman Khandual wrote:
>> This series adds some more arch page table helper validation tests which
>> are related to core and advanced memory functions. This also creates a
>> documentation, enlisting expected
kernel test robot writes:
> Hi Nicholas,
>
> I love your patch! Yet something to improve:
>
> [auto build test ERROR on powerpc/next]
> [also build test ERROR on scottwood/next v5.8-rc2 next-20200626]
> [cannot apply to kvm-ppc/kvm-ppc-next]
> [If your patch is applied to the wrong git tree,
Dan Williams writes:
> On Mon, Jun 29, 2020 at 6:58 AM Aneesh Kumar K.V
> wrote:
>>
>> of_pmem on POWER10 can now use phwsync instead of hwsync to ensure
>> all previous writes are architecturally visible for the platform
>> buffer flush.
>>
>> Signed-off-by: Aneesh Kumar K.V
>> ---
>>
Bharata B Rao writes:
> From: Nicholas Piggin
>
> When platform doesn't support GTSE, let TLB invalidation requests
> for radix guests be off-loaded to the host using H_RPT_INVALIDATE
> hcall.
>
Reviewed-by: Aneesh Kumar K.V
> Signed-off-by: Nicholas Piggin
> Signed-off-by: Bharata B Rao
>
On Tue, Jun 30, 2020 at 4:09 AM Nicolin Chen wrote:
>
> On Mon, Jun 29, 2020 at 09:58:35PM +0800, Shengjiu Wang wrote:
> > The ASRC not only supports ideal ratio mode, but also supports
> > internal ratio mode.
> >
> > For internal rato mode, the rate of clock source should be divided
> > with no
add instruction opcodes for new vsx vector paired instructions,
* Load VSX Vector Paired (lxvp)
* Load VSX Vector Paired Indexed (lxvpx)
* Store VSX Vector Paired (stxvp)
* Store VSX Vector Paired Indexed (stxvpx)
Signed-off-by: Balamuruhan S
---
Bharata B Rao writes:
> Make GTSE an MMU feature and enable it by default for radix.
> However for guest, conditionally enable it if hypervisor supports
> it via OV5 vector. Let prom_init ask for radix GTSE only if the
> support exists.
>
> Having GTSE as an MMU feature will make it easy to
add emulate_step() changes to support vsx vector paired storage
access instructions that provides octword operands loads/stores
between storage and set of 64 Vector Scalar Registers (VSRs).
Signed-off-by: Balamuruhan S
---
arch/powerpc/include/asm/sstep.h | 2 +-
arch/powerpc/lib/sstep.c
On Mon, Jun 29, 2020 at 6:58 AM Aneesh Kumar K.V
wrote:
>
> of_pmem on POWER10 can now use phwsync instead of hwsync to ensure
> all previous writes are architecturally visible for the platform
> buffer flush.
>
> Signed-off-by: Aneesh Kumar K.V
> ---
> arch/powerpc/include/asm/cacheflush.h | 7
On Mon, Jun 29, 2020 at 1:41 PM Aneesh Kumar K.V
wrote:
>
> Michal Suchánek writes:
>
> > Hello,
> >
> > On Mon, Jun 29, 2020 at 07:27:20PM +0530, Aneesh Kumar K.V wrote:
> >> nvdimm expect the flush routines to just mark the cache clean. The barrier
> >> that mark the store globally visible is
Bharata B Rao writes:
> H_REGISTER_PROC_TBL asks for GTSE by default. GTSE flag bit should
> be set only when GTSE is supported.
>
Reviewed-by: Aneesh Kumar K.V
> Signed-off-by: Bharata B Rao
> ---
> arch/powerpc/platforms/pseries/lpar.c | 8 +---
> 1 file changed, 5 insertions(+), 3
I'm seeing RCU warnings when exiting xmon. xmon resets the NMI watchdog,
but does nothing with the RCU stall or soft lockup watchdogs. Add a
helper function that handles all three.
Signed-off-by: Anton Blanchard
---
arch/powerpc/xmon/xmon.c | 9 -
1 file changed, 8 insertions(+), 1
On Mon, Jun 29, 2020 at 1:29 PM Aneesh Kumar K.V
wrote:
>
> Architectures like ppc64 provide persistent memory specific barriers
> that will ensure that all stores for which the modifications are
> written to persistent storage by preceding dcbfps and dcbstps
> instructions have updated
Excerpts from Michael Ellerman's message of June 30, 2020 11:31 am:
> kernel test robot writes:
>> Hi Nicholas,
>>
>> I love your patch! Yet something to improve:
>>
>> [auto build test ERROR on powerpc/next]
>> [also build test ERROR on scottwood/next v5.8-rc2 next-20200626]
>> [cannot apply to
Excerpts from Anton Blanchard's message of June 30, 2020 10:02 am:
> I'm seeing RCU warnings when exiting xmon. xmon resets the NMI watchdog,
> but does nothing with the RCU stall or soft lockup watchdogs. Add a
> helper function that handles all three.
>
> Signed-off-by: Anton Blanchard
It's not done anything for a long time. Save the percpu variable, and
emit a warning to remind users to not expect it to do anything.
Fixes: 3fa8cad82b94 ("powerpc/pseries/cpuidle: smt-snooze-delay cleanup.")
Cc: sta...@vger.kernel.org # v3.14
Signed-off-by: Joel Stanley
--
v2:
Use pr_warn
Dan Williams writes:
> On Mon, Jun 29, 2020 at 1:29 PM Aneesh Kumar K.V
> wrote:
>>
>> Architectures like ppc64 provide persistent memory specific barriers
>> that will ensure that all stores for which the modifications are
>> written to persistent storage by preceding dcbfps and dcbstps
>>
On Mon, Jun 29, 2020 at 2:55 PM Michael Ellerman wrote:
>
> Masahiro Yamada writes:
> > CFLAGS_REMOVE_.o works per object, that is, there is no
> > convenient way to filter out flags for every object in a directory.
> >
> > Add ccflags-remove-y and asflags-remove-y to make it easily.
> >
> > Use
* Christopher Lameter [2020-06-29 14:58:40]:
> On Wed, 24 Jun 2020, Srikar Dronamraju wrote:
>
> > Currently Linux kernel with CONFIG_NUMA on a system with multiple
> > possible nodes, marks node 0 as online at boot. However in practice,
> > there are systems which have node 0 as memoryless
Dan Williams writes:
> On Mon, Jun 29, 2020 at 6:58 AM Aneesh Kumar K.V
> wrote:
>>
>> We only support persistent memory on P8 and above. This is enforced by the
>> firmware and further checked on virtualzied platform during platform init.
>> Add WARN_ONCE in pmem flush routines to catch the
Excerpts from Paul Mackerras's message of June 30, 2020 12:27 pm:
> On Sun, Jun 28, 2020 at 01:04:28AM +1000, Nicholas Piggin wrote:
>> KVM guests have certain restrictions and performance quirks when
>> using doorbells. This patch tests for KVM environment in doorbell
>> setup, and optimises IPI
VSX Vector Paired instructions loads/stores an octword (32 bytes)
from/to storage into two sequential VSRs. Add `analyse_instr()` support
to these new instructions,
* Load VSX Vector Paired (lxvp)
* Load VSX Vector Paired Indexed (lxvpx)
* Prefixed Load VSX Vector Paired
On Sat, Jun 27, 2020 at 5:35 PM Mike Rapoport wrote:
> Most architectures have very similar versions of pXd_alloc_one() and
> pXd_free_one() for intermediate levels of page table.
> These patches add generic versions of these functions in
> and enable use of the generic functions where
>
I'm sorry to say I can no longer maintain this position.
Signed-off-by: Sam Bobroff
---
MAINTAINERS | 1 -
1 file changed, 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 496fd4eafb68..7e954e4a29e1 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -13187,7 +13187,6 @@ F: tools/pci/
For blk-mq drivers bios can only be inserted for the same queue. So
bypass the complicated sorting logic in __submit_bio_noacct with
a blk-mq simpler submission helper.
Signed-off-by: Christoph Hellwig
---
block/blk-core.c | 50 +---
1 file changed,
On Mon, Jun 29, 2020 at 09:58:35PM +0800, Shengjiu Wang wrote:
> The ASRC not only supports ideal ratio mode, but also supports
> internal ratio mode.
>
> For internal rato mode, the rate of clock source should be divided
> with no remainder by sample rate, otherwise there is sound
> distortion.
Architectures like ppc64 provide persistent memory specific barriers
that will ensure that all stores for which the modifications are
written to persistent storage by preceding dcbfps and dcbstps
instructions have updated persistent storage before any data
access or data transfer caused by
Michal Suchánek writes:
> Hello,
>
> On Mon, Jun 29, 2020 at 07:27:20PM +0530, Aneesh Kumar K.V wrote:
>> nvdimm expect the flush routines to just mark the cache clean. The barrier
>> that mark the store globally visible is done in nvdimm_flush().
>>
>> Update the papr_scm driver to a
Now that submit_bio_noacct has a decent blk-mq fast path there is no
more need for this bypass.
Signed-off-by: Christoph Hellwig
---
block/blk-core.c | 28
drivers/md/dm.c | 5 +
drivers/nvme/host/multipath.c | 2 +-
kernel test robot writes:
> Hi "Aneesh,
>
> I love your patch! Yet something to improve:
>
> [auto build test ERROR on powerpc/next]
> [also build test ERROR on linux-nvdimm/libnvdimm-for-next v5.8-rc3
> next-20200629]
> [cannot apply to scottwood/next]
> [If yo
On Mon, Jun 29, 2020 at 9:40 PM Christoph Hellwig wrote:
> Instead of setting up the queuedata as well just use one private data
> field.
>
> Signed-off-by: Christoph Hellwig
Reviewed-by: Geert Uytterhoeven
Acked-by: Geert Uytterhoeven
Gr{oetje,eeting}s,
Geert
--
Bin Meng writes:
> On Sat, May 2, 2020 at 12:45 PM Bin Meng wrote:
>>
>> From: Bin Meng
>>
>> Drop CONFIG_MTD_M25P80 that was removed in
>> commit b35b9a10362d ("mtd: spi-nor: Move m25p80 code in spi-nor.c")
>>
>> Signed-off-by: Bin Meng
>>
>> ---
>>
>> Changes in v2:
>> - correct the typo
On 28/06/20 7:58 am, piliu wrote:
> Hi Hari,
>
> If in [4/11], get_exclude_memory_ranges() turns out to be unnecessary
> ,then this patch is abundant either. As my understanding, memblock has
> already helped to achieved the purpose that get_exclude_memory_ranges()
> wants.
As mentioned in
Hi Christophe
Thanks for the review...
On 27/06/20 12:12 pm, Christophe Leroy wrote:
>
>
> Le 26/06/2020 à 21:04, Hari Bathini a écrit :
>> Some of the kexec_file_load code isn't PPC64 specific. Move PPC64
>> specific code from kexec/file_load.c to kexec/file_load_64.c. Also,
>> rename
Le 28/06/2020 à 18:20, Bharata B Rao a écrit :
On Fri, Jun 19, 2020 at 03:43:41PM -0700, Ram Pai wrote:
H_SVM_INIT_DONE incorrectly assumes that the Ultravisor has explicitly
As noted in the last iteration, can you reword the above please?
I don't see it as an incorrect assumption, but see it
Unlike drivers/base/cacheinfo, powerpc cacheinfo code is not exposing
shared_cpu_list under /sys/devices/system/cpu/cpu/cache/index
Add shared_cpu_list to per cpu per index directory to maintain parity
with x86. Some scripts (example: mmtests
https://github.com/gormanm/mmtests) seem to be
Tejun Heo had modified shared_cpu_map_show to use scnprintf instead of
cpumap_print during support for *pb[l] format.
Refer commit 0c118b7bd09a ("powerpc: use %*pb[l] to print bitmaps including
cpumasks and nodemasks")
cpumap_print_to_pagebuf is a standard function to print cpumap. With
commit
On Mon, 2020-03-30 at 17:39 +1100, Sam Bobroff wrote:
> There is currently little synchronization between EEH error detection
> (eeh_dev_check_failure()), EEH error recovery
> (eeh_handle_{normal,special}_event()) and the PCI subsystem (device
> addition and removal), and so there are race
On 06/24/2020 08:10 PM, Alexander Gordeev wrote:
> On Wed, Jun 24, 2020 at 01:48:08PM +0200, Gerald Schaefer wrote:
>> On Wed, 24 Jun 2020 13:05:39 +0200
>> Alexander Gordeev wrote:
>>
>>> On Wed, Jun 24, 2020 at 08:43:10AM +0530, Anshuman Khandual wrote:
>>>
>>> [...]
>>>
Hello
In anticipation of implementing shared_cpu_list, move code under
shared_cpu_map_show to a common function.
No functional changes.
Cc: Nathan Lynch
Cc: Michael Ellerman
Cc: linuxppc-dev@lists.ozlabs.org
Signed-off-by: Srikar Dronamraju
---
arch/powerpc/kernel/cacheinfo.c | 10 --
1
Hi,
I have picked Quentin's series over my patch, modified both and tested.
V3->V4:
- Do __module_get() for cpufreq_default_governor() case as well and get
rid of an extra variable.
- Use a single character array, default_governor, instead of two of them.
V2->V3:
- default_governor is a
From: Quentin Perret
Currently, most CPUFreq governors are registered at core_initcall time
when used as default, and module_init otherwise. In preparation for
letting users specify the default governor on the kernel command line,
change all of them to use core_initcall unconditionally, as is
shared_cpu_list sysfs file is missing in powerpc and shared_cpu_map gives an
extra newline character.
Before this patchset
# ls /sys/devices/system/cpu0/cache/index1
coherency_line_size number_of_sets size ways_of_associativity
levelshared_cpu_map type
# cat
On Thu, Jun 25, 2020 at 07:33:49PM +0930, Joel Stanley wrote:
> It's not done anything for a long time. Save the percpu variable, and
> emit a warning to remind users to not expect it to do anything.
>
> Signed-off-by: Joel Stanley
The only known user of "smt_snooze_delay" is the "ppc64_cpu"
Hi Michael,
I see this patch is marked as "defered" in patchwork, but I can't see
any related discussion. Is it normal ?
Christophe
Le 16/04/2020 à 14:39, Christophe Leroy a écrit :
At the time being, __put_user()/__get_user() and friends only use
D-form addressing, with 0 offset. Ex:
When there is dedicated power domain bound with device, after probing
the power will be disabled, then registers are not accessible in
fsl_sai_dai_probe(), so regcache only need to be enabled in end of
probe() and regcache_mark_dirty should be moved to pm runtime resume
callback function.
On 06/27/2020 12:56 PM, Christophe Leroy wrote:
>
>
> Le 15/06/2020 à 05:37, Anshuman Khandual a écrit :
>> This adds new tests validating for these following arch advanced page table
>> helpers. These tests create and test specific mapping types at various page
>> table levels.
>>
>> 1.
On 25.06.2020 15:08, Joerg Roedel wrote:
> From: Joerg Roedel
>
> Remove the use of dev->archdata.iommu and use the private per-device
> pointer provided by IOMMU core code instead.
>
> Signed-off-by: Joerg Roedel
Acked-by: Marek Szyprowski
> ---
> drivers/iommu/exynos-iommu.c
Joerg Roedel writes:
> From: Joerg Roedel
>
> There are no users left, so remove the pointer and save some memory.
>
> Signed-off-by: Joerg Roedel
> ---
> arch/powerpc/include/asm/device.h | 3 ---
> 1 file changed, 3 deletions(-)
It's a little hard to confirm there are no users left just
On 06/27/2020 12:48 PM, Christophe Leroy wrote:
> Le 15/06/2020 à 05:37, Anshuman Khandual a écrit :
>> This adds new tests validating for these following arch advanced page table
>> helpers. These tests create and test specific mapping types at various page
>> table levels.
>>
>> 1.
On book3s32 (hash), exec protection is set per 256Mb segments with NX bit.
Instead of clearing NX bit on vmalloc space when CONFIG_MODULES is selected,
allocate modules in a dedicated segment (0xb000-0xbfff by default).
This allows to keep exec protection on vmalloc space while allowing
Hi Petr,
On 29/06/20 5:09 pm, Petr Tesarik wrote:
> Hi Hari,
>
> is there any good reason to add two more functions with a very similar
> name to an existing function? AFAICS all you need is a way to call a
> PPC64-specific function from within kexec_add_buffer (PATCH 4/11), so
> you could add
POWER10 introduces two new variants of dcbf instructions (dcbstps and dcbfps)
that can be used to write modified locations back to persistent storage.
Additionally, POWER10 also introduce phwsync and plwsync which can be used
to establish order of these writes to persistent storage.
This patch
of_pmem on POWER10 can now use phwsync instead of hwsync to ensure
all previous writes are architecturally visible for the platform
buffer flush.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/cacheflush.h | 7 +++
1 file changed, 7 insertions(+)
diff --git
Use is_vmalloc_or_module_addr() instead of is_vmalloc_addr()
Signed-off-by: Christophe Leroy
---
arch/powerpc/lib/code-patching.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/lib/code-patching.c b/arch/powerpc/lib/code-patching.c
index
In order to allow allocation of modules outside of vmalloc space,
use MODULES_VADDR and MODULES_END when MODULES_VADDR is defined.
Redefine module_alloc() when MODULES_VADDR defined.
Unmap corresponding KASAN shadow memory.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/module.c
Christophe Leroy writes:
> Hi Michael,
>
> I see this patch is marked as "defered" in patchwork, but I can't see
> any related discussion. Is it normal ?
Because it uses the "m<>" constraint which didn't work on GCC 4.6.
https://github.com/linuxppc/issues/issues/297
So we should be able to
Hi Hari,
is there any good reason to add two more functions with a very similar
name to an existing function? AFAICS all you need is a way to call a
PPC64-specific function from within kexec_add_buffer (PATCH 4/11), so
you could add something like this:
int __weak
Instead of leaving NX unset on all segments above the start
of vmalloc space, only leave NX unset on segments used for
modules.
Signed-off-by: Christophe Leroy
---
arch/powerpc/mm/book3s32/mmu.c | 17 ++---
1 file changed, 14 insertions(+), 3 deletions(-)
diff --git
Start using dcbstps; phwsync; sequence for flushing persistent memory range.
The new instructions are implemented as a variant of dcbf and hwsync and on
P8 and P9 they will be executed as those instructions. We avoid using them on
older hardware. This helps to avoid difficult to debug bugs.
User space stops at TASK_SIZE. At the moment, kernel space starts
at PAGE_OFFSET.
In order to use space between TASK_SIZE and PAGE_OFFSET for modules,
make TASK_SIZE the limit between user and kernel space.
Note that fault.c already considers TASK_SIZE as the boundary between
user and kernel
Kernel space starts at TASK_SIZE. Select kernel page table
when address is over TASK_SIZE.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_32.S | 12 ++--
arch/powerpc/mm/book3s32/hash_low.S | 2 +-
2 files changed, 7 insertions(+), 7 deletions(-)
diff --git
When STRICT_KERNEL_RWX is set, we want to set NX bit on vmalloc
segments. But modules require exec.
Use a dedicated segment for modules. There is not much space
above kernel, and we don't waste vmalloc space to do alignment.
Therefore, we take the segment before PAGE_OFFSET for modules.
st->last_pa is always updated in note_page() so it can
be done outside the if/elseif/else block.
Signed-off-by: Christophe Leroy
---
arch/powerpc/mm/ptdump/ptdump.c | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/arch/powerpc/mm/ptdump/ptdump.c
In note_page(), the pg_state is updated the same way in two places.
Add note_page_update_state() to do it.
Also include the display of boundary markers there as it is missing
"no level" leg, leading to a mismatch when the first two markers
are at the same address and the first displayed area
On Mon, Jun 29, 2020 at 04:07:01PM +0530, Srikar Dronamraju wrote:
> Tejun Heo had modified shared_cpu_map_show to use scnprintf instead of
> cpumap_print during support for *pb[l] format.
> Refer commit 0c118b7bd09a ("powerpc: use %*pb[l] to print bitmaps including
> cpumasks and nodemasks")
>
>
The PAPR based virtualized persistent memory devices are only supported on
POWER9 and above. In the followup patch, the kernel will switch the persistent
memory cache flush functions to use a new `dcbf` variant instruction. The new
instructions even though added in ISA 3.1 works even on P8 and P9
Architectures like ppc64 provide persistent memory specific barriers
that will ensure that all stores for which the modifications are
written to persistent storage by preceding dcbfps and dcbstps
instructions have updated persistent storage before any data
access or data transfer caused by
With kernel now supporting new pmem flush/sync instructions, we can now
enable the kernel to initialize the device. On P10 these devices would
appear with a new compatible string. For PAPR device we have
compatible "ibm,pmemory-v2"
and for OF pmem device we have
compatible
https://bugzilla.kernel.org/show_bug.cgi?id=208181
Erhard F. (erhar...@mailbox.org) changed:
What|Removed |Added
Attachment #289659|0 |1
is obsolete|
On Sat, Jun 27, 2020 at 4:36 PM Mike Rapoport wrote:
> From: Mike Rapoport
>
> Most architectures define pgd_free() as a wrapper for free_page().
>
> Provide a generic version in asm-generic/pgalloc.h and enable its use for
> most architectures.
>
> Signed-off-by: Mike Rapoport
For the m68k
The ASRC not only supports ideal ratio mode, but also supports
internal ratio mode.
For internal rato mode, the rate of clock source should be divided
with no remainder by sample rate, otherwise there is sound
distortion.
Add function fsl_asrc_select_clk() to find proper clock source for
https://bugzilla.kernel.org/show_bug.cgi?id=208181
Erhard F. (erhar...@mailbox.org) changed:
What|Removed |Added
Attachment #289661|0 |1
is obsolete|
https://bugzilla.kernel.org/show_bug.cgi?id=208181
--- Comment #5 from Christophe Leroy (christophe.le...@csgroup.eu) ---
Can we get a dump of /sys/kernel/debug/powerpc/block_address_translation
--
You are receiving this mail because:
You are watching the assignee of the bug.
We only support persistent memory on P8 and above. This is enforced by the
firmware and further checked on virtualzied platform during platform init.
Add WARN_ONCE in pmem flush routines to catch the wrong usage of these.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/cacheflush.h
This patch series enables the usage os new pmem flush and sync instructions on
POWER
architecture. POWER10 introduces two new variants of dcbf instructions (dcbstps
and dcbfps)
that can be used to write modified locations back to persistent storage.
Additionally,
POWER10 also introduce phwsync
On Sat, Jun 27, 2020 at 4:35 PM Mike Rapoport wrote:
> From: Mike Rapoport
>
> In the most cases header is required only for allocations
> of page table memory. Most of the .c files that include that header do not
> use symbols declared in and do not require that header.
>
> As for the other
nvdimm expect the flush routines to just mark the cache clean. The barrier
that mark the store globally visible is done in nvdimm_flush().
Update the papr_scm driver to a simplified nvdim_flush callback that do
only the required barrier.
Signed-off-by: Aneesh Kumar K.V
---
https://bugzilla.kernel.org/show_bug.cgi?id=208181
--- Comment #4 from Erhard F. (erhar...@mailbox.org) ---
Erm wait... there is some change.
In 5.8-rc1 stacktrace was:
BUG: KASAN: stack-out-of-bounds in strcmp+0x58/0xd8
Read of size 1 at addr c11c1a80 by task swapper/0
CPU: 0 PID: 0 Comm:
On Wed, 24 Jun 2020, Srikar Dronamraju wrote:
> Currently Linux kernel with CONFIG_NUMA on a system with multiple
> possible nodes, marks node 0 as online at boot. However in practice,
> there are systems which have node 0 as memoryless and cpuless.
Maybe add something to explain why you are
On Sat, Jun 27, 2020 at 08:03:04PM +0100, Matthew Wilcox wrote:
> On Sat, Jun 27, 2020 at 05:34:49PM +0300, Mike Rapoport wrote:
> > More elaborate versions on arm64 and x86 account memory for the user page
> > tables and call to pgtable_pmd_page_ctor() as the part of PMD page
> > initialization.
Hello,
On Mon, Jun 29, 2020 at 07:27:20PM +0530, Aneesh Kumar K.V wrote:
> nvdimm expect the flush routines to just mark the cache clean. The barrier
> that mark the store globally visible is done in nvdimm_flush().
>
> Update the papr_scm driver to a simplified nvdim_flush callback that do
>
https://bugzilla.kernel.org/show_bug.cgi?id=208181
--- Comment #6 from Erhard F. (erhar...@mailbox.org) ---
Created attachment 289945
--> https://bugzilla.kernel.org/attachment.cgi?id=289945=edit
block_address_translation
Sure.
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https://bugzilla.kernel.org/show_bug.cgi?id=208181
--- Comment #7 from Erhard F. (erhar...@mailbox.org) ---
Created attachment 289947
--> https://bugzilla.kernel.org/attachment.cgi?id=289947=edit
segment_registers
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Hi "Aneesh,
I love your patch! Yet something to improve:
[auto build test ERROR on powerpc/next]
[also build test ERROR on linux-nvdimm/libnvdimm-for-next v5.8-rc3
next-20200629]
[cannot apply to scottwood/next]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And
On Mon, Jun 29, 2020 at 07:23:30AM +0530, Bharata B Rao wrote:
> On Sun, Jun 28, 2020 at 09:41:53PM +0530, Bharata B Rao wrote:
> > On Fri, Jun 19, 2020 at 03:43:38PM -0700, Ram Pai wrote:
> > > The time taken to switch a VM to Secure-VM, increases by the size of the
> > > VM. A
> > > 100GB VM
Nothing in bcache actually uses the ->queuedata field.
Signed-off-by: Christoph Hellwig
---
drivers/md/bcache/super.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/md/bcache/super.c b/drivers/md/bcache/super.c
index 2014016f9a60d3..21aa168113d30b 100644
---
Instead of setting up the queuedata as well just use one private data
field.
Signed-off-by: Christoph Hellwig
---
drivers/block/ps3vram.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/block/ps3vram.c b/drivers/block/ps3vram.c
index 821d4d8b1d763e..5a1d1d137c7248
Instead of setting up the queuedata as well just use one private data
field.
Signed-off-by: Christoph Hellwig
---
drivers/block/drbd/drbd_main.c | 1 -
drivers/block/drbd/drbd_req.c | 2 +-
2 files changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/block/drbd/drbd_main.c
Instead of setting up the queuedata as well just use one private data
field.
Signed-off-by: Christoph Hellwig
---
arch/m68k/emu/nfblock.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/arch/m68k/emu/nfblock.c b/arch/m68k/emu/nfblock.c
index c3a630440512e9..87e8b1700acd28
All registers disks must have a valid queue pointer, so don't bother to
log a warning for that case.
Signed-off-by: Christoph Hellwig
---
block/blk-core.c | 12 +---
1 file changed, 1 insertion(+), 11 deletions(-)
diff --git a/block/blk-core.c b/block/blk-core.c
index
The make_request_fn is a little weird in that it sits directly in
struct request_queue instead of an operation vector. Replace it with
a block_device_operations method called submit_bio (which describes much
better what it does). Also remove the request_queue argument to it, as
the queue can be
generic_make_request has always been very confusingly misnamed, so rename
it to submit_bio_noacct to make it clear that it is submit_bio minus
accounting and a few checks.
Signed-off-by: Christoph Hellwig
---
Documentation/block/biodoc.rst| 2 +-
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