Currently the pin_name is fixed in asoc_simple_init_jack, but some driver
may use a different pin_name. So add a new parameter in
asoc_simple_init_jack for configuring pin_name.
If this parameter is NULL, then the default pin_name is used.
Signed-off-by: Shengjiu Wang
---
Support hp and mic detection.
Add a parameter for asoc_simple_init_jack.
Shengjiu Wang (3):
ASoC: simple-card-utils: Support configure pin_name for
asoc_simple_init_jack
ASoC: bindings: fsl-asoc-card: Support hp-det-gpio and mic-det-gpio
ASoC: fsl-asoc-card: Support Headphone and
On 10/07/2020 15:23, Oliver O'Halloran wrote:
> We pre-configure the m64 window for IODA1 as a 1-1 segment-PE mapping,
> similar to PHB3. Currently the actual mapping of segments occurs in
> pnv_ioda_pick_m64_pe(), but we can move it into pnv_ioda1_init_m64() and
> drop the IODA1 specific code
This converts the PPC4xx SPI driver to use GPIO descriptors.
The driver is already just picking some GPIOs from the device
tree so the conversion is pretty straight forward. However
this driver is looking form a pure "gpios" property rather
than the standard binding "cs-gpios" so we need to add a
On 14/07/2020 15:58, Oliver O'Halloran wrote:
> On Tue, Jul 14, 2020 at 3:37 PM Alexey Kardashevskiy wrote:
>>
>> On 10/07/2020 15:23, Oliver O'Halloran wrote:
>>> There's an optimisation in the PE setup which skips performing DMA
>>> setup for a PE if we only have bridges in a PE. The
On 14/07/2020 17:07, Christoph Hellwig wrote:
> On Mon, Jul 13, 2020 at 02:59:39PM +1000, Alexey Kardashevskiy wrote:
>>
>>
>> On 09/07/2020 01:24, Christoph Hellwig wrote:
>>> Several IOMMU drivers have a bypass mode where they can use a direct
>>> mapping if the devices DMA mask is large
On Mon, Jul 13, 2020 at 02:59:39PM +1000, Alexey Kardashevskiy wrote:
>
>
> On 09/07/2020 01:24, Christoph Hellwig wrote:
> > Several IOMMU drivers have a bypass mode where they can use a direct
> > mapping if the devices DMA mask is large enough. Add generic support
> > to the core dma-mapping
Dear Catalin,
Am 13.07.20 um 20:27 schrieb Catalin Marinas:
On Thu, Jul 09, 2020 at 11:08:52PM +0200, Paul Menzel wrote:
Am 09.07.20 um 19:57 schrieb Catalin Marinas:
On Thu, Jul 09, 2020 at 04:37:10PM +0200, Paul Menzel wrote:
Despite Linux 5.8-rc4 reporting memory leaks on the IBM POWER 8
In fact, the changes over the last patch are more complex than the
current patch.
Just for reference, that's how enable_ddw() currently patches:
@@ -1087,7 +1119,7 @@ static u64 enable_ddw(struct pci_dev *dev, struct
device_node *pdn)
struct device_node *dn;
u32
On Tue, 14 Jul 2020 at 05:04, Steven Rostedt wrote:
>
> On Mon, 13 Jul 2020 22:49:48 +0300
> Ard Biesheuvel wrote:
>
> > On arm64, we no longer use module_alloc for bpf or kprobes, to avoid
> > wasting va space on code that does not need to be loaded close to the
> > kernel. Also, module_alloc()
Hi Nayna,
Thanks! Would you be able to fold in some of the information from my
reply to v1 into the changelog? Until we have public PAPR release with
it, that information is the extent of the public documentation. It would
be good to get it into the git log rather than just floating around in
the
Excerpts from Nicholas Piggin's message of July 14, 2020 3:04 pm:
> Excerpts from Andy Lutomirski's message of July 14, 2020 4:18 am:
>>
>>> On Jul 13, 2020, at 9:48 AM, Nicholas Piggin wrote:
>>>
>>> Excerpts from Andy Lutomirski's message of July 14, 2020 1:59 am:
> On Thu, Jul 9, 2020
On Tue, 2020-07-14 at 14:52 +1000, Alexey Kardashevskiy wrote:
>
> On 14/07/2020 12:40, Leonardo Bras wrote:
> > Thank you for this feedback Alexey!
> >
> > On Mon, 2020-07-13 at 17:33 +1000, Alexey Kardashevskiy wrote:
> > > [...]
> > > > - int len, ret;
> > > > + int len, ret,
* Oliver O'Halloran [2020-07-14 15:40:09]:
> On Tue, Jul 14, 2020 at 2:45 PM Srikar Dronamraju
> wrote:
> >
> > Current code assumes that cpumask of cpus sharing a l2-cache mask will
> > always be a superset of cpu_sibling_mask.
> >
> > Lets stop that assumption.
>
> It's been a while since I
Athira Rajeev writes:
>> On 19-Mar-2020, at 4:22 PM, Michael Ellerman wrote:
>>
>> Hi Athira,
>>
>> Athira Rajeev writes:
>>> Sampled Instruction Event Register (SIER), is a PMU register,
>> ^
>>
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