Re: [PATCH 2/2] powerpc/perf: Add declarations to fix sparse warnings
On 9/16/20 5:26 PM, Michael Ellerman wrote: Sparse warns about all the init functions: symbol init_ppc970_pmu was not declared. Should it be static? symbol init_power5p_pmu was not declared. Should it be static? symbol init_power5_pmu was not declared. Should it be static? symbol init_power6_pmu was not declared. Should it be static? symbol init_power7_pmu was not declared. Should it be static? symbol init_power9_pmu was not declared. Should it be static? symbol init_power8_pmu was not declared. Should it be static? symbol init_generic_compat_pmu was not declared. Should it be static? They're already declared in internal.h, so just make sure all the C files include that directly or indirectly. Reviewed-by: Madhavan Srinivasan Signed-off-by: Michael Ellerman --- arch/powerpc/perf/isa207-common.h | 2 ++ arch/powerpc/perf/power10-pmu.c | 1 - arch/powerpc/perf/power5+-pmu.c | 2 ++ arch/powerpc/perf/power5-pmu.c| 2 ++ arch/powerpc/perf/power6-pmu.c| 2 ++ arch/powerpc/perf/power7-pmu.c| 2 ++ arch/powerpc/perf/ppc970-pmu.c| 2 ++ 7 files changed, 12 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/perf/isa207-common.h b/arch/powerpc/perf/isa207-common.h index 044de65e96b9..7025de5e60e7 100644 --- a/arch/powerpc/perf/isa207-common.h +++ b/arch/powerpc/perf/isa207-common.h @@ -13,6 +13,8 @@ #include #include +#include "internal.h" + #define EVENT_EBB_MASK1ull #define EVENT_EBB_SHIFT PERF_EVENT_CONFIG_EBB_SHIFT #define EVENT_BHRB_MASK 1ull diff --git a/arch/powerpc/perf/power10-pmu.c b/arch/powerpc/perf/power10-pmu.c index 83148656b524..9dbe8f9b89b4 100644 --- a/arch/powerpc/perf/power10-pmu.c +++ b/arch/powerpc/perf/power10-pmu.c @@ -9,7 +9,6 @@ #define pr_fmt(fmt) "power10-pmu: " fmt #include "isa207-common.h" -#include "internal.h" /* * Raw event encoding for Power10: diff --git a/arch/powerpc/perf/power5+-pmu.c b/arch/powerpc/perf/power5+-pmu.c index a62b2cd7914f..3e64b4a1511f 100644 --- a/arch/powerpc/perf/power5+-pmu.c +++ b/arch/powerpc/perf/power5+-pmu.c @@ -10,6 +10,8 @@ #include #include +#include "internal.h" + /* * Bits in event code for POWER5+ (POWER5 GS) and POWER5++ (POWER5 GS DD3) */ diff --git a/arch/powerpc/perf/power5-pmu.c b/arch/powerpc/perf/power5-pmu.c index 8732b587cf71..017bb19b73fb 100644 --- a/arch/powerpc/perf/power5-pmu.c +++ b/arch/powerpc/perf/power5-pmu.c @@ -10,6 +10,8 @@ #include #include +#include "internal.h" + /* * Bits in event code for POWER5 (not POWER5++) */ diff --git a/arch/powerpc/perf/power6-pmu.c b/arch/powerpc/perf/power6-pmu.c index 0e318cf87129..189974478e9f 100644 --- a/arch/powerpc/perf/power6-pmu.c +++ b/arch/powerpc/perf/power6-pmu.c @@ -10,6 +10,8 @@ #include #include +#include "internal.h" + /* * Bits in event code for POWER6 */ diff --git a/arch/powerpc/perf/power7-pmu.c b/arch/powerpc/perf/power7-pmu.c index 5e0bf09cf077..bacfab104a1a 100644 --- a/arch/powerpc/perf/power7-pmu.c +++ b/arch/powerpc/perf/power7-pmu.c @@ -10,6 +10,8 @@ #include #include +#include "internal.h" + /* * Bits in event code for POWER7 */ diff --git a/arch/powerpc/perf/ppc970-pmu.c b/arch/powerpc/perf/ppc970-pmu.c index d35223fb112c..7d78df97f272 100644 --- a/arch/powerpc/perf/ppc970-pmu.c +++ b/arch/powerpc/perf/ppc970-pmu.c @@ -9,6 +9,8 @@ #include #include +#include "internal.h" + /* * Bits in event code for PPC970 */
[PATCH] powerpc/process: Fix uninitialised variable error
Clang, and GCC with -Wmaybe-uninitialized, can't see that val is
unused in get_fpexec_mode():
arch/powerpc/kernel/process.c:1940:7: error: variable 'val' is used
uninitialized whenever 'if' condition is true
if (cpu_has_feature(CPU_FTR_SPE)) {
^~~~
We know that CPU_FTR_SPE will only be true iff CONFIG_SPE is also
true, but the compiler doesn't.
Avoid it by initialising val to zero.
Reported-by: kernel test robot
Fixes: 532ed1900d37 ("powerpc/process: Remove useless #ifdef CONFIG_SPE")
Signed-off-by: Michael Ellerman
---
arch/powerpc/kernel/process.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c
index 14d5189b17d8..d421a2c7f822 100644
--- a/arch/powerpc/kernel/process.c
+++ b/arch/powerpc/kernel/process.c
@@ -1934,7 +1934,7 @@ int set_fpexc_mode(struct task_struct *tsk, unsigned int
val)
int get_fpexc_mode(struct task_struct *tsk, unsigned long adr)
{
- unsigned int val;
+ unsigned int val = 0;
if (tsk->thread.fpexc_mode & PR_FP_EXC_SW_ENABLE) {
if (cpu_has_feature(CPU_FTR_SPE)) {
--
2.25.1
[PATCH -next v2] powerpc/book3s64: fix link error with CONFIG_PPC_RADIX_MMU=n
Fix link error when CONFIG_PPC_RADIX_MMU is disabled:
powerpc64-linux-gnu-ld: arch/powerpc/platforms/pseries/lpar.o:(.toc+0x0):
undefined reference to `mmu_pid_bits'
Reported-by: Hulk Robot
Signed-off-by: Yang Yingliang
---
v2:
- enclose radix_init_pseries with CONFIG_PPC_RADIX_MMU
- remove CONFIG_PPC_RADIX_MMU in radix__init_new_context()
---
arch/powerpc/platforms/pseries/lpar.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/powerpc/platforms/pseries/lpar.c
b/arch/powerpc/platforms/pseries/lpar.c
index baf24eacd268..764170fdb0f7 100644
--- a/arch/powerpc/platforms/pseries/lpar.c
+++ b/arch/powerpc/platforms/pseries/lpar.c
@@ -1724,6 +1724,7 @@ void __init hpte_init_pseries(void)
pseries_lpar_register_process_table(0, 0, 0);
}
+#ifdef CONFIG_PPC_RADIX_MMU
void radix_init_pseries(void)
{
pr_info("Using radix MMU under hypervisor\n");
@@ -1731,6 +1732,7 @@ void radix_init_pseries(void)
pseries_lpar_register_process_table(__pa(process_tb),
0, PRTB_SIZE_SHIFT - 12);
}
+#endif
#ifdef CONFIG_PPC_SMLPAR
#define CMO_FREE_HINT_DEFAULT 1
--
2.25.1
[PATCH 2/2] powerpc/64s: Convert some cpu_setup() and cpu_restore() functions to C
The only thing keeping the cpu_setup() and cpu_restore() functions used
in the cputable entries for Power7, Power8, Power9 and Power10 in
assembly was cpu_restore() being called before there was a stack in
generic_secondary_smp_init(). Commit ("powerpc/64: Set up a kernel stack
for secondaries before cpu_restore()") means that it is now possible to
use C.
Rewrite the functions in C so they are a little bit easier to read. This
is not changing their functionality.
Signed-off-by: Jordan Niethe
---
arch/powerpc/include/asm/cpu_setup_power.h | 12 +
arch/powerpc/kernel/cpu_setup_power.S | 252 ---
arch/powerpc/kernel/cpu_setup_power.c | 269 +
arch/powerpc/kernel/cputable.c | 9 +-
4 files changed, 282 insertions(+), 260 deletions(-)
create mode 100644 arch/powerpc/include/asm/cpu_setup_power.h
delete mode 100644 arch/powerpc/kernel/cpu_setup_power.S
create mode 100644 arch/powerpc/kernel/cpu_setup_power.c
diff --git a/arch/powerpc/include/asm/cpu_setup_power.h
b/arch/powerpc/include/asm/cpu_setup_power.h
new file mode 100644
index ..24be9131f803
--- /dev/null
+++ b/arch/powerpc/include/asm/cpu_setup_power.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (C) 2020 IBM Corporation
+ */
+void __setup_cpu_power7(unsigned long offset, struct cpu_spec *spec);
+void __restore_cpu_power7(void);
+void __setup_cpu_power8(unsigned long offset, struct cpu_spec *spec);
+void __restore_cpu_power8(void);
+void __setup_cpu_power9(unsigned long offset, struct cpu_spec *spec);
+void __restore_cpu_power9(void);
+void __setup_cpu_power10(unsigned long offset, struct cpu_spec *spec);
+void __restore_cpu_power10(void);
diff --git a/arch/powerpc/kernel/cpu_setup_power.S
b/arch/powerpc/kernel/cpu_setup_power.S
deleted file mode 100644
index 704e8b9501ee..
--- a/arch/powerpc/kernel/cpu_setup_power.S
+++ /dev/null
@@ -1,252 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/*
- * This file contains low level CPU setup functions.
- *Copyright (C) 2003 Benjamin Herrenschmidt (b...@kernel.crashing.org)
- */
-
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-
-/* Entry: r3 = crap, r4 = ptr to cputable entry
- *
- * Note that we can be called twice for pseudo-PVRs
- */
-_GLOBAL(__setup_cpu_power7)
- mflrr11
- bl __init_hvmode_206
- mtlrr11
- beqlr
- li r0,0
- mtspr SPRN_LPID,r0
- LOAD_REG_IMMEDIATE(r0, PCR_MASK)
- mtspr SPRN_PCR,r0
- mfspr r3,SPRN_LPCR
- li r4,(LPCR_LPES1 >> LPCR_LPES_SH)
- bl __init_LPCR_ISA206
- mtlrr11
- blr
-
-_GLOBAL(__restore_cpu_power7)
- mflrr11
- mfmsr r3
- rldicl. r0,r3,4,63
- beqlr
- li r0,0
- mtspr SPRN_LPID,r0
- LOAD_REG_IMMEDIATE(r0, PCR_MASK)
- mtspr SPRN_PCR,r0
- mfspr r3,SPRN_LPCR
- li r4,(LPCR_LPES1 >> LPCR_LPES_SH)
- bl __init_LPCR_ISA206
- mtlrr11
- blr
-
-_GLOBAL(__setup_cpu_power8)
- mflrr11
- bl __init_FSCR
- bl __init_PMU
- bl __init_PMU_ISA207
- bl __init_hvmode_206
- mtlrr11
- beqlr
- li r0,0
- mtspr SPRN_LPID,r0
- LOAD_REG_IMMEDIATE(r0, PCR_MASK)
- mtspr SPRN_PCR,r0
- mfspr r3,SPRN_LPCR
- ori r3, r3, LPCR_PECEDH
- li r4,0 /* LPES = 0 */
- bl __init_LPCR_ISA206
- bl __init_HFSCR
- bl __init_PMU_HV
- bl __init_PMU_HV_ISA207
- mtlrr11
- blr
-
-_GLOBAL(__restore_cpu_power8)
- mflrr11
- bl __init_FSCR
- bl __init_PMU
- bl __init_PMU_ISA207
- mfmsr r3
- rldicl. r0,r3,4,63
- mtlrr11
- beqlr
- li r0,0
- mtspr SPRN_LPID,r0
- LOAD_REG_IMMEDIATE(r0, PCR_MASK)
- mtspr SPRN_PCR,r0
- mfspr r3,SPRN_LPCR
- ori r3, r3, LPCR_PECEDH
- li r4,0 /* LPES = 0 */
- bl __init_LPCR_ISA206
- bl __init_HFSCR
- bl __init_PMU_HV
- bl __init_PMU_HV_ISA207
- mtlrr11
- blr
-
-_GLOBAL(__setup_cpu_power10)
- mflrr11
- bl __init_FSCR_power10
- bl __init_PMU
- bl __init_PMU_ISA31
- b 1f
-
-_GLOBAL(__setup_cpu_power9)
- mflrr11
- bl __init_FSCR_power9
- bl __init_PMU
-1: bl __init_hvmode_206
- mtlrr11
- beqlr
- li r0,0
- mtspr SPRN_PSSCR,r0
- mtspr SPRN_LPID,r0
- mtspr SPRN_PID,r0
- LOAD_REG_IMMEDIATE(r0, PCR_MASK)
- mtspr SPRN_PCR,r0
- mfspr r3,SPRN_LPCR
- LOAD_REG_IMMEDIATE(r4, LPCR_PECEDH | LPCR_PECE_HVEE | LPCR_HVICE |
LPCR_HEIC)
- or r3, r3, r4
- LOAD_REG_IMMEDIATE(r4, L
[PATCH 1/2] powerpc/64: Set up a kernel stack for secondaries before cpu_restore()
Currently in generic_secondary_smp_init(), cur_cpu_spec->cpu_restore()
is called before a stack has been set up in r1. This was previously fine
as the cpu_restore() functions were implemented in assembly and did not
use a stack. However commit 5a61ef74f269 ("powerpc/64s: Support new
device tree binding for discovering CPU features") used
__restore_cpu_cpufeatures() as the cpu_restore() function for a
device-tree features based cputable entry. This is a nonleaf C function
and hence requires a stack in r1.
Create the temp kernel stack before calling cpu_restore().
Fixes: 5a61ef74f269 ("powerpc/64s: Support new device tree binding for
discovering CPU features")
Signed-off-by: Jordan Niethe
---
arch/powerpc/kernel/head_64.S | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/kernel/head_64.S b/arch/powerpc/kernel/head_64.S
index 0e05a9a47a4b..4b7f4c6c2600 100644
--- a/arch/powerpc/kernel/head_64.S
+++ b/arch/powerpc/kernel/head_64.S
@@ -420,6 +420,10 @@ generic_secondary_common_init:
/* From now on, r24 is expected to be logical cpuid */
mr r24,r5
+ /* Create a temp kernel stack for use before relocation is on. */
+ ld r1,PACAEMERGSP(r13)
+ subir1,r1,STACK_FRAME_OVERHEAD
+
/* See if we need to call a cpu state restore handler */
LOAD_REG_ADDR(r23, cur_cpu_spec)
ld r23,0(r23)
@@ -448,10 +452,6 @@ generic_secondary_common_init:
sync/* order paca.run and cur_cpu_spec */
isync /* In case code patching happened */
- /* Create a temp kernel stack for use before relocation is on. */
- ld r1,PACAEMERGSP(r13)
- subir1,r1,STACK_FRAME_OVERHEAD
-
b __secondary_start
#endif /* SMP */
--
2.17.1
[PATCH 2/3] powerpc/mce: Add debugfs interface to inject MCE
To test machine check handling, add debugfs interface to inject
slb multihit errors.
To inject slb multihit:
#echo 1 > /sys/kernel/debug/powerpc/mce_error_inject/inject_slb_multihit
Signed-off-by: Ganesh Goudar
Signed-off-by: Mahesh Salgaonkar
---
arch/powerpc/Kconfig.debug | 9 ++
arch/powerpc/sysdev/Makefile | 2 +
arch/powerpc/sysdev/mce_error_inject.c | 148 +
3 files changed, 159 insertions(+)
create mode 100644 arch/powerpc/sysdev/mce_error_inject.c
diff --git a/arch/powerpc/Kconfig.debug b/arch/powerpc/Kconfig.debug
index b88900f4832f..61db133f2f0d 100644
--- a/arch/powerpc/Kconfig.debug
+++ b/arch/powerpc/Kconfig.debug
@@ -398,3 +398,12 @@ config KASAN_SHADOW_OFFSET
hex
depends on KASAN
default 0xe000
+
+config MCE_ERROR_INJECT
+ bool "Enable MCE error injection through debugfs"
+ depends on DEBUG_FS
+ default y
+ help
+ This option creates an mce_error_inject directory in the
+ powerpc debugfs directory that allows limited injection of
+ Machine Check Errors (MCEs).
diff --git a/arch/powerpc/sysdev/Makefile b/arch/powerpc/sysdev/Makefile
index 026b3f01a991..7fc10b77 100644
--- a/arch/powerpc/sysdev/Makefile
+++ b/arch/powerpc/sysdev/Makefile
@@ -52,3 +52,5 @@ obj-$(CONFIG_PPC_XICS)+= xics/
obj-$(CONFIG_PPC_XIVE) += xive/
obj-$(CONFIG_GE_FPGA) += ge/
+
+obj-$(CONFIG_MCE_ERROR_INJECT) += mce_error_inject.o
diff --git a/arch/powerpc/sysdev/mce_error_inject.c
b/arch/powerpc/sysdev/mce_error_inject.c
new file mode 100644
index ..ca4726bfa2d9
--- /dev/null
+++ b/arch/powerpc/sysdev/mce_error_inject.c
@@ -0,0 +1,148 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Machine Check Exception injection code
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+static inline unsigned long get_slb_index(void)
+{
+ unsigned long index;
+
+ index = get_paca()->stab_rr;
+
+ /*
+* simple round-robin replacement of slb starting at SLB_NUM_BOLTED.
+*/
+ if (index < (mmu_slb_size - 1))
+ index++;
+ else
+ index = SLB_NUM_BOLTED;
+ get_paca()->stab_rr = index;
+ return index;
+}
+
+#define slb_esid_mask(ssize) \
+ (((ssize) == MMU_SEGSIZE_256M) ? ESID_MASK : ESID_MASK_1T)
+
+static inline unsigned long mk_esid_data(unsigned long ea, int ssize,
+unsigned long slot)
+{
+ return (ea & slb_esid_mask(ssize)) | SLB_ESID_V | slot;
+}
+
+#define slb_vsid_shift(ssize) \
+ ((ssize) == MMU_SEGSIZE_256M ? SLB_VSID_SHIFT : SLB_VSID_SHIFT_1T)
+
+static inline unsigned long mk_vsid_data(unsigned long ea, int ssize,
+unsigned long flags)
+{
+ return (get_kernel_vsid(ea, ssize) << slb_vsid_shift(ssize)) | flags |
+ ((unsigned long)ssize << SLB_VSID_SSIZE_SHIFT);
+}
+
+static void insert_slb_entry(char *p, int ssize)
+{
+ unsigned long flags, entry;
+ struct paca_struct *paca;
+
+ flags = SLB_VSID_KERNEL | mmu_psize_defs[MMU_PAGE_64K].sllp;
+
+ preempt_disable();
+
+ paca = get_paca();
+
+ entry = get_slb_index();
+ asm volatile("slbmte %0,%1" :
+ : "r" (mk_vsid_data((unsigned long)p, ssize, flags)),
+ "r" (mk_esid_data((unsigned long)p, ssize, entry))
+ : "memory");
+
+ entry = get_slb_index();
+ asm volatile("slbmte %0,%1" :
+ : "r" (mk_vsid_data((unsigned long)p, ssize, flags)),
+ "r" (mk_esid_data((unsigned long)p, ssize, entry))
+ : "memory");
+ preempt_enable();
+ p[0] = '!';
+}
+
+static void inject_vmalloc_slb_multihit(void)
+{
+ char *p;
+
+ p = vmalloc(2048);
+ if (!p)
+ return;
+
+ insert_slb_entry(p, MMU_SEGSIZE_1T);
+ vfree(p);
+}
+
+static void inject_kmalloc_slb_multihit(void)
+{
+ char *p;
+
+ p = kmalloc(2048, GFP_KERNEL);
+ if (!p)
+ return;
+
+ insert_slb_entry(p, MMU_SEGSIZE_1T);
+ kfree(p);
+}
+
+static ssize_t inject_slb_multihit(const char __user *u_buf, size_t count)
+{
+ char buf[32];
+ size_t buf_size;
+
+ buf_size = min(count, (sizeof(buf) - 1));
+ if (copy_from_user(buf, u_buf, buf_size))
+ return -EFAULT;
+ buf[buf_size] = '\0';
+
+ if (buf[0] != '1')
+ return -EINVAL;
+
+ inject_vmalloc_slb_multihit();
+ inject_kmalloc_slb_multihit();
+ return count;
+}
+
+static ssize_t inject_write(struct file *file, const char __user *buf,
+ size_t count, loff_t *ppos)
+{
+ static ssize_t (*func)(const char __user *, size_t);
+
+ func = file->f_inode->i_private;
+ return func(buf, count);
+}
+
+static con
[PATCH 0/3] powerpc/mce: Fix mce handler and add selftest
This patch series fixes mce handling for pseries, provides debugfs interface for mce injection and adds selftest to test mce handling on pseries/powernv machines running in hash mmu mode. debugfs interface and sleftest are added only for slb multihit injection, We can add other tests in future if possible. Ganesh Goudar (3): powerpc/mce: remove nmi_enter/exit from real mode handler powerpc/mce: Add debugfs interface to inject MCE selftest/powerpc: Add slb multihit selftest arch/powerpc/Kconfig.debug| 9 ++ arch/powerpc/kernel/mce.c | 7 +- arch/powerpc/sysdev/Makefile | 2 + arch/powerpc/sysdev/mce_error_inject.c| 149 ++ tools/testing/selftests/powerpc/Makefile | 3 +- tools/testing/selftests/powerpc/mces/Makefile | 6 + .../selftests/powerpc/mces/slb_multihit.sh| 9 ++ 7 files changed, 183 insertions(+), 2 deletions(-) create mode 100644 arch/powerpc/sysdev/mce_error_inject.c create mode 100644 tools/testing/selftests/powerpc/mces/Makefile create mode 100755 tools/testing/selftests/powerpc/mces/slb_multihit.sh -- 2.26.2
[PATCH 3/3] selftest/powerpc: Add slb multihit selftest
Add selftest to check if the system recovers from slb multihit errors. Signed-off-by: Ganesh Goudar --- tools/testing/selftests/powerpc/Makefile | 3 ++- tools/testing/selftests/powerpc/mces/Makefile| 6 ++ tools/testing/selftests/powerpc/mces/slb_multihit.sh | 9 + 3 files changed, 17 insertions(+), 1 deletion(-) create mode 100644 tools/testing/selftests/powerpc/mces/Makefile create mode 100755 tools/testing/selftests/powerpc/mces/slb_multihit.sh diff --git a/tools/testing/selftests/powerpc/Makefile b/tools/testing/selftests/powerpc/Makefile index 0830e63818c1..3c900b30da79 100644 --- a/tools/testing/selftests/powerpc/Makefile +++ b/tools/testing/selftests/powerpc/Makefile @@ -31,7 +31,8 @@ SUB_DIRS = alignment \ vphn \ math \ ptrace \ - security + security \ + mces endif diff --git a/tools/testing/selftests/powerpc/mces/Makefile b/tools/testing/selftests/powerpc/mces/Makefile new file mode 100644 index ..5a356295e952 --- /dev/null +++ b/tools/testing/selftests/powerpc/mces/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0 +# Makefile for machine check exceptions selftests + +TEST_PROGS := slb_multihit.sh + +include ../../lib.mk diff --git a/tools/testing/selftests/powerpc/mces/slb_multihit.sh b/tools/testing/selftests/powerpc/mces/slb_multihit.sh new file mode 100755 index ..35c17c619d0a --- /dev/null +++ b/tools/testing/selftests/powerpc/mces/slb_multihit.sh @@ -0,0 +1,9 @@ +#!/bin/sh +# SPDX-License-Identifier: GPL-2.0 + +if [ ! -e "/sys/kernel/debug/powerpc/mce_error_inject/inject_slb_multihit" ] ; then +exit 0; +fi + +echo 1 > /sys/kernel/debug/powerpc/mce_error_inject/inject_slb_multihit +exit 0 -- 2.26.2
[PATCH 1/3] powerpc/mce: remove nmi_enter/exit from real mode handler
Use of nmi_enter/exit in real mode handler causes the kernel to panic
and reboot on injecting slb mutihit on pseries machine running in hash
mmu mode, As these calls try to accesses memory outside RMO region in
real mode handler where translation is disabled.
Add check to not to use these calls on pseries machine running in hash
mmu mode.
Fixes: 116ac378bb3f ("powerpc/64s: machine check interrupt update NMI
accounting")
Signed-off-by: Ganesh Goudar
---
arch/powerpc/kernel/mce.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/kernel/mce.c b/arch/powerpc/kernel/mce.c
index ada59f6c4298..1d42fe0f5f9c 100644
--- a/arch/powerpc/kernel/mce.c
+++ b/arch/powerpc/kernel/mce.c
@@ -591,10 +591,15 @@ EXPORT_SYMBOL_GPL(machine_check_print_event_info);
long notrace machine_check_early(struct pt_regs *regs)
{
long handled = 0;
- bool nested = in_nmi();
+ bool nested;
+ bool is_pseries_hpt_guest;
u8 ftrace_enabled = this_cpu_get_ftrace_enabled();
this_cpu_set_ftrace_enabled(0);
+ is_pseries_hpt_guest = machine_is(pseries) &&
+ mmu_has_feature(MMU_FTR_HPTE_TABLE);
+ /* Do not use nmi_enter/exit for pseries hpte guest */
+ nested = is_pseries_hpt_guest ? true : in_nmi();
if (!nested)
nmi_enter();
--
2.26.2
[PATCH v2] powerpc: fix EDEADLOCK redefinition error in uapi/asm/errno.h
A few archs like powerpc have different errno.h values for macros
EDEADLOCK and EDEADLK. In code including both libc and linux versions of
errno.h, this can result in multiple definitions of EDEADLOCK in the
include chain. Definitions to the same value (e.g. seen with mips) do
not raise warnings, but on powerpc there are redefinitions changing the
value, which raise warnings and errors (if using "-Werror").
Guard against these redefinitions to avoid build errors like the following,
first seen cross-compiling libbpf v5.8.9 for powerpc using GCC 8.4.0 with
musl 1.1.24:
In file included from ../../arch/powerpc/include/uapi/asm/errno.h:5,
from ../../include/linux/err.h:8,
from libbpf.c:29:
../../include/uapi/asm-generic/errno.h:40: error: "EDEADLOCK" redefined
[-Werror]
#define EDEADLOCK EDEADLK
In file included from
toolchain-powerpc_8540_gcc-8.4.0_musl/include/errno.h:10,
from libbpf.c:26:
toolchain-powerpc_8540_gcc-8.4.0_musl/include/bits/errno.h:58: note: this is
the location of the previous definition
#define EDEADLOCK 58
cc1: all warnings being treated as errors
Fixes: 95f28190aa01 ("tools include arch: Grab a copy of errno.h for arch's
supported by perf")
Fixes: c3617f72036c ("UAPI: (Scripted) Disintegrate arch/powerpc/include/asm")
Reported-by: Rosen Penev
Signed-off-by: Tony Ambardar
---
v1 -> v2:
* clean up commit description formatting
---
arch/powerpc/include/uapi/asm/errno.h | 1 +
tools/arch/powerpc/include/uapi/asm/errno.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/arch/powerpc/include/uapi/asm/errno.h
b/arch/powerpc/include/uapi/asm/errno.h
index cc79856896a1..4ba87de32be0 100644
--- a/arch/powerpc/include/uapi/asm/errno.h
+++ b/arch/powerpc/include/uapi/asm/errno.h
@@ -2,6 +2,7 @@
#ifndef _ASM_POWERPC_ERRNO_H
#define _ASM_POWERPC_ERRNO_H
+#undef EDEADLOCK
#include
#undef EDEADLOCK
diff --git a/tools/arch/powerpc/include/uapi/asm/errno.h
b/tools/arch/powerpc/include/uapi/asm/errno.h
index cc79856896a1..4ba87de32be0 100644
--- a/tools/arch/powerpc/include/uapi/asm/errno.h
+++ b/tools/arch/powerpc/include/uapi/asm/errno.h
@@ -2,6 +2,7 @@
#ifndef _ASM_POWERPC_ERRNO_H
#define _ASM_POWERPC_ERRNO_H
+#undef EDEADLOCK
#include
#undef EDEADLOCK
--
2.25.1
[PATCH] ibmvfc: Protect vhost->task_set increment by the host lock
In the discovery thread, ibmvfc does a vhost->task_set++ without any lock held. This could result in two targets getting the same cancel key, which could have strange effects in error recovery. The actual probability of this occurring should be extremely small, since this should all be done in a single threaded loop from the discovery thread, but let's fix it up anyway to be safe. Signed-off-by: Brian King --- drivers/scsi/ibmvscsi/ibmvfc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/scsi/ibmvscsi/ibmvfc.c b/drivers/scsi/ibmvscsi/ibmvfc.c index 322bb30..b393587 100644 --- a/drivers/scsi/ibmvscsi/ibmvfc.c +++ b/drivers/scsi/ibmvscsi/ibmvfc.c @@ -4169,11 +4169,11 @@ static int ibmvfc_alloc_target(struct ibmvfc_host *vhost,struct ibmvfc_discover_ tgt->wwpn = wwpn; tgt->vhost = vhost; tgt->need_login = 1; - tgt->cancel_key = vhost->task_set++; timer_setup(&tgt->timer, ibmvfc_adisc_timeout, 0); kref_init(&tgt->kref); ibmvfc_init_tgt(tgt, ibmvfc_tgt_implicit_logout); spin_lock_irqsave(vhost->host->host_lock, flags); + tgt->cancel_key = vhost->task_set++; list_add_tail(&tgt->queue, &vhost->targets); unlock_out: -- 1.8.3.1
Re: [PATCH] ASoC: fsl_audmix: make clock and output src write only
On Mon, Sep 14, 2020 at 08:24:34PM +0300, Viorel Suman (OSS) wrote:
> From: Viorel Suman
>
> "alsactl -f state.conf store/restore" sequence fails because setting
> "mixing clock source" and "output source" requires active TDM clock
> being started for configuration propagation. Make these two controls
> write only so that their values are not stored at "alsactl store".
>
> Signed-off-by: Viorel Suman
Acked-by: Nicolin Chen
> ---
> sound/soc/fsl/fsl_audmix.c | 16
> 1 file changed, 12 insertions(+), 4 deletions(-)
>
> diff --git a/sound/soc/fsl/fsl_audmix.c b/sound/soc/fsl/fsl_audmix.c
> index a447baf..7ad5925 100644
> --- a/sound/soc/fsl/fsl_audmix.c
> +++ b/sound/soc/fsl/fsl_audmix.c
> @@ -199,10 +199,18 @@ static int fsl_audmix_put_out_src(struct snd_kcontrol
> *kcontrol,
>
> static const struct snd_kcontrol_new fsl_audmix_snd_controls[] = {
> /* FSL_AUDMIX_CTR controls */
> - SOC_ENUM_EXT("Mixing Clock Source", fsl_audmix_enum[0],
> - snd_soc_get_enum_double, fsl_audmix_put_mix_clk_src),
> - SOC_ENUM_EXT("Output Source", fsl_audmix_enum[1],
> - snd_soc_get_enum_double, fsl_audmix_put_out_src),
> + { .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
> + .name = "Mixing Clock Source",
> + .info = snd_soc_info_enum_double,
> + .access = SNDRV_CTL_ELEM_ACCESS_WRITE,
> + .put = fsl_audmix_put_mix_clk_src,
> + .private_value = (unsigned long)&fsl_audmix_enum[0] },
> + { .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
> + .name = "Output Source",
> + .info = snd_soc_info_enum_double,
> + .access = SNDRV_CTL_ELEM_ACCESS_WRITE,
> + .put = fsl_audmix_put_out_src,
> + .private_value = (unsigned long)&fsl_audmix_enum[1] },
> SOC_ENUM("Output Width", fsl_audmix_enum[2]),
> SOC_ENUM("Frame Rate Diff Error", fsl_audmix_enum[3]),
> SOC_ENUM("Clock Freq Diff Error", fsl_audmix_enum[4]),
> --
> 2.7.4
>
[PATCH v4] pseries/hotplug-memory: hot-add: skip redundant LMB lookup
During memory hot-add, dlpar_add_lmb() calls memory_add_physaddr_to_nid() to determine which node id (nid) to use when later calling __add_memory(). This is wasteful. On pseries, memory_add_physaddr_to_nid() finds an appropriate nid for a given address by looking up the LMB containing the address and then passing that LMB to of_drconf_to_nid_single() to get the nid. In dlpar_add_lmb() we get this address from the LMB itself. In short, we have a pointer to an LMB and then we are searching for that LMB *again* in order to find its nid. If we call of_drconf_to_nid_single() directly from dlpar_add_lmb() we can skip the redundant lookup. The only error handling we need to duplicate from memory_add_physaddr_to_nid() is the fallback to the default nid when drconf_to_nid_single() returns -1 (NUMA_NO_NODE) or an invalid nid. Skipping the extra lookup makes hot-add operations faster, especially on machines with many LMBs. Consider an LPAR with 126976 LMBs. In one test, hot-adding 126000 LMBs on an upatched kernel took ~3.5 hours while a patched kernel completed the same operation in ~2 hours: Unpatched (12450 seconds): Sep 9 04:06:31 ltc-brazos1 drmgr[810169]: drmgr: -c mem -a -q 126000 Sep 9 04:06:31 ltc-brazos1 kernel: pseries-hotplug-mem: Attempting to hot-add 126000 LMB(s) [...] Sep 9 07:34:01 ltc-brazos1 kernel: pseries-hotplug-mem: Memory at 2000 (drc index 8002) was hot-added Patched (7065 seconds): Sep 8 21:49:57 ltc-brazos1 drmgr[877703]: drmgr: -c mem -a -q 126000 Sep 8 21:49:57 ltc-brazos1 kernel: pseries-hotplug-mem: Attempting to hot-add 126000 LMB(s) [...] Sep 8 23:27:42 ltc-brazos1 kernel: pseries-hotplug-mem: Memory at 2000 (drc index 8002) was hot-added It should be noted that the speedup grows more substantial when hot-adding LMBs at the end of the drconf range. This is because we are skipping a linear LMB search. To see the distinction, consider smaller hot-add test on the same LPAR. A perf-stat run with 10 iterations showed that hot-adding 4096 LMBs completed less than 1 second faster on a patched kernel: Unpatched: Performance counter stats for 'drmgr -c mem -a -q 4096' (10 runs): 104,753.42 msec task-clock#0.992 CPUs utilized ( +- 0.55% ) 4,708 context-switches #0.045 K/sec ( +- 0.69% ) 2,444 cpu-migrations#0.023 K/sec ( +- 1.25% ) 394 page-faults #0.004 K/sec ( +- 0.22% ) 445,902,503,057 cycles#4.257 GHz ( +- 0.55% ) (66.67%) 8,558,376,740 stalled-cycles-frontend #1.92% frontend cycles idle ( +- 0.88% ) (49.99%) 300,346,181,651 stalled-cycles-backend# 67.36% backend cycles idle ( +- 0.76% ) (50.01%) 258,091,488,691 instructions #0.58 insn per cycle #1.16 stalled cycles per insn ( +- 0.22% ) (66.67%) 70,568,169,256 branches # 673.660 M/sec ( +- 0.17% ) (50.01%) 3,100,725,426 branch-misses #4.39% of all branches ( +- 0.20% ) (49.99%) 105.583 +- 0.589 seconds time elapsed ( +- 0.56% ) Patched: Performance counter stats for 'drmgr -c mem -a -q 4096' (10 runs): 104,055.69 msec task-clock#0.993 CPUs utilized ( +- 0.32% ) 4,606 context-switches #0.044 K/sec ( +- 0.20% ) 2,463 cpu-migrations#0.024 K/sec ( +- 0.93% ) 394 page-faults #0.004 K/sec ( +- 0.25% ) 442,951,129,921 cycles#4.257 GHz ( +- 0.32% ) (66.66%) 8,710,413,329 stalled-cycles-frontend #1.97% frontend cycles idle ( +- 0.47% ) (50.06%) 299,656,905,836 stalled-cycles-backend# 67.65% backend cycles idle ( +- 0.39% ) (50.02%) 252,731,168,193 instructions #0.57 insn per cycle #1.19 stalled cycles per insn ( +- 0.20% ) (66.66%) 68,902,851,121 branches # 662.173 M/sec ( +- 0.13% ) (49.94%) 3,100,242,882 branch-misses #4.50% of all branches ( +- 0.15% ) (49.98%) 104.829 +- 0.325 seconds time elapsed ( +- 0.31% ) This is consistent. An add-by-count hot-add operation adds LMBs greedily, so LMBs near the start of the drconf range are considered first. On an otherwise idle LPAR with so many LMBs we would expect to find the LMBs we need near the start of the drconf range, hence the smaller speedup. Signed-off-by: Scott Cheloha ---
Re: [PATCH v3] pseries/hotplug-memory: hot-add: skip redundant LMB lookup
On 16.09.20 16:39, Scott Cheloha wrote: > On Wed, Sep 16, 2020 at 09:39:53AM +0200, David Hildenbrand wrote: >> On 15.09.20 21:46, Scott Cheloha wrote: >>> During memory hot-add, dlpar_add_lmb() calls memory_add_physaddr_to_nid() >>> to determine which node id (nid) to use when later calling __add_memory(). >>> >>> This is wasteful. On pseries, memory_add_physaddr_to_nid() finds an >>> appropriate nid for a given address by looking up the LMB containing the >>> address and then passing that LMB to of_drconf_to_nid_single() to get the >>> nid. In dlpar_add_lmb() we get this address from the LMB itself. >>> >>> In short, we have a pointer to an LMB and then we are searching for >>> that LMB *again* in order to find its nid. >>> >>> If we call of_drconf_to_nid_single() directly from dlpar_add_lmb() we >>> can skip the redundant lookup. The only error handling we need to >>> duplicate from memory_add_physaddr_to_nid() is the fallback to the >>> default nid when drconf_to_nid_single() returns -1 (NUMA_NO_NODE) or >>> an invalid nid. >>> >>> Skipping the extra lookup makes hot-add operations faster, especially >>> on machines with many LMBs. >>> >>> Consider an LPAR with 126976 LMBs. In one test, hot-adding 126000 >>> LMBs on an upatched kernel took ~3.5 hours while a patched kernel >>> completed the same operation in ~2 hours: >>> >>> Unpatched (12450 seconds): >>> Sep 9 04:06:31 ltc-brazos1 drmgr[810169]: drmgr: -c mem -a -q 126000 >>> Sep 9 04:06:31 ltc-brazos1 kernel: pseries-hotplug-mem: Attempting to >>> hot-add 126000 LMB(s) >>> [...] >>> Sep 9 07:34:01 ltc-brazos1 kernel: pseries-hotplug-mem: Memory at 2000 >>> (drc index 8002) was hot-added >>> >>> Patched (7065 seconds): >>> Sep 8 21:49:57 ltc-brazos1 drmgr[877703]: drmgr: -c mem -a -q 126000 >>> Sep 8 21:49:57 ltc-brazos1 kernel: pseries-hotplug-mem: Attempting to >>> hot-add 126000 LMB(s) >>> [...] >>> Sep 8 23:27:42 ltc-brazos1 kernel: pseries-hotplug-mem: Memory at 2000 >>> (drc index 8002) was hot-added >>> >>> It should be noted that the speedup grows more substantial when >>> hot-adding LMBs at the end of the drconf range. This is because we >>> are skipping a linear LMB search. >>> >>> To see the distinction, consider smaller hot-add test on the same >>> LPAR. A perf-stat run with 10 iterations showed that hot-adding 4096 >>> LMBs completed less than 1 second faster on a patched kernel: >>> >>> Unpatched: >>> Performance counter stats for 'drmgr -c mem -a -q 4096' (10 runs): >>> >>> 104,753.42 msec task-clock#0.992 CPUs utilized >>> ( +- 0.55% ) >>> 4,708 context-switches #0.045 K/sec >>> ( +- 0.69% ) >>> 2,444 cpu-migrations#0.023 K/sec >>> ( +- 1.25% ) >>>394 page-faults #0.004 K/sec >>> ( +- 0.22% ) >>>445,902,503,057 cycles#4.257 GHz >>> ( +- 0.55% ) (66.67%) >>> 8,558,376,740 stalled-cycles-frontend #1.92% frontend >>> cycles idle ( +- 0.88% ) (49.99%) >>>300,346,181,651 stalled-cycles-backend# 67.36% backend cycles >>> idle ( +- 0.76% ) (50.01%) >>>258,091,488,691 instructions #0.58 insn per cycle >>> #1.16 stalled cycles >>> per insn ( +- 0.22% ) (66.67%) >>> 70,568,169,256 branches # 673.660 M/sec >>> ( +- 0.17% ) (50.01%) >>> 3,100,725,426 branch-misses #4.39% of all >>> branches ( +- 0.20% ) (49.99%) >>> >>>105.583 +- 0.589 seconds time elapsed ( +- 0.56% ) >>> >>> Patched: >>> Performance counter stats for 'drmgr -c mem -a -q 4096' (10 runs): >>> >>> 104,055.69 msec task-clock#0.993 CPUs utilized >>> ( +- 0.32% ) >>> 4,606 context-switches #0.044 K/sec >>> ( +- 0.20% ) >>> 2,463 cpu-migrations#0.024 K/sec >>> ( +- 0.93% ) >>>394 page-faults #0.004 K/sec >>> ( +- 0.25% ) >>>442,951,129,921 cycles#4.257 GHz >>> ( +- 0.32% ) (66.66%) >>> 8,710,413,329 stalled-cycles-frontend #1.97% frontend >>> cycles idle ( +- 0.47% ) (50.06%) >>>299,656,905,836 stalled-cycles-backend# 67.65% backend cycles >>> idle ( +- 0.39% ) (50.02%) >>>252,731,168,193 instructions #0.57 insn per cycle >>> #1.19 stalled cycles >>> per insn ( +- 0.20% ) (66.66%) >>> 68,902,851,121 branches # 662.173 M/sec >>>
Re: [PATCH v3] pseries/hotplug-memory: hot-add: skip redundant LMB lookup
On Wed, Sep 16, 2020 at 09:39:53AM +0200, David Hildenbrand wrote: > On 15.09.20 21:46, Scott Cheloha wrote: > > During memory hot-add, dlpar_add_lmb() calls memory_add_physaddr_to_nid() > > to determine which node id (nid) to use when later calling __add_memory(). > > > > This is wasteful. On pseries, memory_add_physaddr_to_nid() finds an > > appropriate nid for a given address by looking up the LMB containing the > > address and then passing that LMB to of_drconf_to_nid_single() to get the > > nid. In dlpar_add_lmb() we get this address from the LMB itself. > > > > In short, we have a pointer to an LMB and then we are searching for > > that LMB *again* in order to find its nid. > > > > If we call of_drconf_to_nid_single() directly from dlpar_add_lmb() we > > can skip the redundant lookup. The only error handling we need to > > duplicate from memory_add_physaddr_to_nid() is the fallback to the > > default nid when drconf_to_nid_single() returns -1 (NUMA_NO_NODE) or > > an invalid nid. > > > > Skipping the extra lookup makes hot-add operations faster, especially > > on machines with many LMBs. > > > > Consider an LPAR with 126976 LMBs. In one test, hot-adding 126000 > > LMBs on an upatched kernel took ~3.5 hours while a patched kernel > > completed the same operation in ~2 hours: > > > > Unpatched (12450 seconds): > > Sep 9 04:06:31 ltc-brazos1 drmgr[810169]: drmgr: -c mem -a -q 126000 > > Sep 9 04:06:31 ltc-brazos1 kernel: pseries-hotplug-mem: Attempting to > > hot-add 126000 LMB(s) > > [...] > > Sep 9 07:34:01 ltc-brazos1 kernel: pseries-hotplug-mem: Memory at 2000 > > (drc index 8002) was hot-added > > > > Patched (7065 seconds): > > Sep 8 21:49:57 ltc-brazos1 drmgr[877703]: drmgr: -c mem -a -q 126000 > > Sep 8 21:49:57 ltc-brazos1 kernel: pseries-hotplug-mem: Attempting to > > hot-add 126000 LMB(s) > > [...] > > Sep 8 23:27:42 ltc-brazos1 kernel: pseries-hotplug-mem: Memory at 2000 > > (drc index 8002) was hot-added > > > > It should be noted that the speedup grows more substantial when > > hot-adding LMBs at the end of the drconf range. This is because we > > are skipping a linear LMB search. > > > > To see the distinction, consider smaller hot-add test on the same > > LPAR. A perf-stat run with 10 iterations showed that hot-adding 4096 > > LMBs completed less than 1 second faster on a patched kernel: > > > > Unpatched: > > Performance counter stats for 'drmgr -c mem -a -q 4096' (10 runs): > > > > 104,753.42 msec task-clock#0.992 CPUs utilized > > ( +- 0.55% ) > > 4,708 context-switches #0.045 K/sec > > ( +- 0.69% ) > > 2,444 cpu-migrations#0.023 K/sec > > ( +- 1.25% ) > >394 page-faults #0.004 K/sec > > ( +- 0.22% ) > >445,902,503,057 cycles#4.257 GHz > > ( +- 0.55% ) (66.67%) > > 8,558,376,740 stalled-cycles-frontend #1.92% frontend > > cycles idle ( +- 0.88% ) (49.99%) > >300,346,181,651 stalled-cycles-backend# 67.36% backend cycles > > idle ( +- 0.76% ) (50.01%) > >258,091,488,691 instructions #0.58 insn per cycle > > #1.16 stalled cycles > > per insn ( +- 0.22% ) (66.67%) > > 70,568,169,256 branches # 673.660 M/sec > > ( +- 0.17% ) (50.01%) > > 3,100,725,426 branch-misses #4.39% of all > > branches ( +- 0.20% ) (49.99%) > > > >105.583 +- 0.589 seconds time elapsed ( +- 0.56% ) > > > > Patched: > > Performance counter stats for 'drmgr -c mem -a -q 4096' (10 runs): > > > > 104,055.69 msec task-clock#0.993 CPUs utilized > > ( +- 0.32% ) > > 4,606 context-switches #0.044 K/sec > > ( +- 0.20% ) > > 2,463 cpu-migrations#0.024 K/sec > > ( +- 0.93% ) > >394 page-faults #0.004 K/sec > > ( +- 0.25% ) > >442,951,129,921 cycles#4.257 GHz > > ( +- 0.32% ) (66.66%) > > 8,710,413,329 stalled-cycles-frontend #1.97% frontend > > cycles idle ( +- 0.47% ) (50.06%) > >299,656,905,836 stalled-cycles-backend# 67.65% backend cycles > > idle ( +- 0.39% ) (50.02%) > >252,731,168,193 instructions #0.57 insn per cycle > > #1.19 stalled cycles > > per insn ( +- 0.20% ) (66.66%) > > 68,902,851,121 branches # 662.173 M/sec > > ( +- 0.13% ) (49.94%) > >
Re: [PATCH] ibmvfc: Avoid link down on FS9100 canister reboot
On 9/15/20 7:49 PM, Martin K. Petersen wrote: > > Brian, > >> When a canister on a FS9100, or similar storage, running in NPIV mode, >> is rebooted, its WWPNs will fail over to another canister. > > [...] > > Applied to 5.10/scsi-staging, thanks! I fixed a bunch of checkpatch > warnings. Sorry about the checkpatch issues. Thanks for pulling this in. -Brian -- Brian King Power Linux I/O IBM Linux Technology Center
Re: [PATCH] fsl: imx-audmix: Use devm_kcalloc() in imx_audmix_probe()
> A multiplication for the size determination of a memory allocation > indicated that an array data structure should be processed. > Thus use the corresponding function "devm_kcalloc". I find the previous patch subject inappropriate. Would you like to choose an alternative? Regards, Markus
[PATCH] powerpc/perf: Exclude pmc5/6 from the irrelevant PMU group constraints
PMU counter support functions enforces event constraints for group of
events to check if all events in a group can be monitored. Incase of
event codes using PMC5 and PMC6 ( 500fa and 600f4 respectively ),
not all constraints are applicable, say the threshold or sample bits.
But current code includes pmc5 and pmc6 in some group constraints (like
IC_DC Qualifier bits) which is actually not applicable and hence results
in those events not getting counted when scheduled along with group of
other events. Patch fixes this by excluding PMC5/6 from constraints
which are not relevant for it.
Fixes: 7ffd948 ('powerpc/perf: factor out power8 pmu functions')
Signed-off-by: Athira Rajeev
---
arch/powerpc/perf/isa207-common.c | 4
1 file changed, 4 insertions(+)
diff --git a/arch/powerpc/perf/isa207-common.c
b/arch/powerpc/perf/isa207-common.c
index 964437a..186fad8 100644
--- a/arch/powerpc/perf/isa207-common.c
+++ b/arch/powerpc/perf/isa207-common.c
@@ -288,6 +288,9 @@ int isa207_get_constraint(u64 event, unsigned long *maskp,
unsigned long *valp)
mask |= CNST_PMC_MASK(pmc);
value |= CNST_PMC_VAL(pmc);
+
+ if (pmc >= 5)
+ goto ebb_bhrb;
}
if (pmc <= 4) {
@@ -357,6 +360,7 @@ int isa207_get_constraint(u64 event, unsigned long *maskp,
unsigned long *valp)
}
}
+ebb_bhrb:
if (!pmc && ebb)
/* EBB events must specify the PMC */
return -1;
--
1.8.3.1
[PATCH 1/2] powerpc/mm/64s: Fix slb_setup_new_exec() sparse warning
Sparse says:
symbol slb_setup_new_exec was not declared. Should it be static?
No, it should have a declaration in a header, add one.
Signed-off-by: Michael Ellerman
---
arch/powerpc/mm/book3s64/internal.h| 2 ++
arch/powerpc/mm/book3s64/mmu_context.c | 4 ++--
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/mm/book3s64/internal.h
b/arch/powerpc/mm/book3s64/internal.h
index 7eda0d30d765..c12d78ee42f5 100644
--- a/arch/powerpc/mm/book3s64/internal.h
+++ b/arch/powerpc/mm/book3s64/internal.h
@@ -13,4 +13,6 @@ static inline bool stress_slb(void)
return static_branch_unlikely(&stress_slb_key);
}
+void slb_setup_new_exec(void);
+
#endif /* ARCH_POWERPC_MM_BOOK3S64_INTERNAL_H */
diff --git a/arch/powerpc/mm/book3s64/mmu_context.c
b/arch/powerpc/mm/book3s64/mmu_context.c
index 0ba30b8b935b..1c54821de7bf 100644
--- a/arch/powerpc/mm/book3s64/mmu_context.c
+++ b/arch/powerpc/mm/book3s64/mmu_context.c
@@ -21,6 +21,8 @@
#include
#include
+#include "internal.h"
+
static DEFINE_IDA(mmu_context_ida);
static int alloc_context_id(int min_id, int max_id)
@@ -48,8 +50,6 @@ int hash__alloc_context_id(void)
}
EXPORT_SYMBOL_GPL(hash__alloc_context_id);
-void slb_setup_new_exec(void);
-
static int realloc_context_ids(mm_context_t *ctx)
{
int i, id;
--
2.25.1
[PATCH 2/2] powerpc/perf: Add declarations to fix sparse warnings
Sparse warns about all the init functions: symbol init_ppc970_pmu was not declared. Should it be static? symbol init_power5p_pmu was not declared. Should it be static? symbol init_power5_pmu was not declared. Should it be static? symbol init_power6_pmu was not declared. Should it be static? symbol init_power7_pmu was not declared. Should it be static? symbol init_power9_pmu was not declared. Should it be static? symbol init_power8_pmu was not declared. Should it be static? symbol init_generic_compat_pmu was not declared. Should it be static? They're already declared in internal.h, so just make sure all the C files include that directly or indirectly. Signed-off-by: Michael Ellerman --- arch/powerpc/perf/isa207-common.h | 2 ++ arch/powerpc/perf/power10-pmu.c | 1 - arch/powerpc/perf/power5+-pmu.c | 2 ++ arch/powerpc/perf/power5-pmu.c| 2 ++ arch/powerpc/perf/power6-pmu.c| 2 ++ arch/powerpc/perf/power7-pmu.c| 2 ++ arch/powerpc/perf/ppc970-pmu.c| 2 ++ 7 files changed, 12 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/perf/isa207-common.h b/arch/powerpc/perf/isa207-common.h index 044de65e96b9..7025de5e60e7 100644 --- a/arch/powerpc/perf/isa207-common.h +++ b/arch/powerpc/perf/isa207-common.h @@ -13,6 +13,8 @@ #include #include +#include "internal.h" + #define EVENT_EBB_MASK 1ull #define EVENT_EBB_SHIFTPERF_EVENT_CONFIG_EBB_SHIFT #define EVENT_BHRB_MASK1ull diff --git a/arch/powerpc/perf/power10-pmu.c b/arch/powerpc/perf/power10-pmu.c index 83148656b524..9dbe8f9b89b4 100644 --- a/arch/powerpc/perf/power10-pmu.c +++ b/arch/powerpc/perf/power10-pmu.c @@ -9,7 +9,6 @@ #define pr_fmt(fmt)"power10-pmu: " fmt #include "isa207-common.h" -#include "internal.h" /* * Raw event encoding for Power10: diff --git a/arch/powerpc/perf/power5+-pmu.c b/arch/powerpc/perf/power5+-pmu.c index a62b2cd7914f..3e64b4a1511f 100644 --- a/arch/powerpc/perf/power5+-pmu.c +++ b/arch/powerpc/perf/power5+-pmu.c @@ -10,6 +10,8 @@ #include #include +#include "internal.h" + /* * Bits in event code for POWER5+ (POWER5 GS) and POWER5++ (POWER5 GS DD3) */ diff --git a/arch/powerpc/perf/power5-pmu.c b/arch/powerpc/perf/power5-pmu.c index 8732b587cf71..017bb19b73fb 100644 --- a/arch/powerpc/perf/power5-pmu.c +++ b/arch/powerpc/perf/power5-pmu.c @@ -10,6 +10,8 @@ #include #include +#include "internal.h" + /* * Bits in event code for POWER5 (not POWER5++) */ diff --git a/arch/powerpc/perf/power6-pmu.c b/arch/powerpc/perf/power6-pmu.c index 0e318cf87129..189974478e9f 100644 --- a/arch/powerpc/perf/power6-pmu.c +++ b/arch/powerpc/perf/power6-pmu.c @@ -10,6 +10,8 @@ #include #include +#include "internal.h" + /* * Bits in event code for POWER6 */ diff --git a/arch/powerpc/perf/power7-pmu.c b/arch/powerpc/perf/power7-pmu.c index 5e0bf09cf077..bacfab104a1a 100644 --- a/arch/powerpc/perf/power7-pmu.c +++ b/arch/powerpc/perf/power7-pmu.c @@ -10,6 +10,8 @@ #include #include +#include "internal.h" + /* * Bits in event code for POWER7 */ diff --git a/arch/powerpc/perf/ppc970-pmu.c b/arch/powerpc/perf/ppc970-pmu.c index d35223fb112c..7d78df97f272 100644 --- a/arch/powerpc/perf/ppc970-pmu.c +++ b/arch/powerpc/perf/ppc970-pmu.c @@ -9,6 +9,8 @@ #include #include +#include "internal.h" + /* * Bits in event code for PPC970 */ -- 2.25.1
[PATCH -next] ide: Fix symbol undeclared warnings
Build the object file with `C=2` and get the following warnings:
make allmodconfig ARCH=powerpc CROSS_COMPILE=powerpc64-linux-gnu-
make C=2 drivers/ide/pmac.o ARCH=powerpc64
CROSS_COMPILE=powerpc64-linux-gnu-
drivers/ide/pmac.c:228:23: warning: symbol 'mdma_timings_33' was not
declared. Should it be static?
drivers/ide/pmac.c:241:23: warning: symbol 'mdma_timings_33k' was not
declared. Should it be static?
drivers/ide/pmac.c:254:23: warning: symbol 'mdma_timings_66' was not
declared. Should it be static?
drivers/ide/pmac.c:272:3: warning: symbol 'kl66_udma_timings' was not
declared. Should it be static?
drivers/ide/pmac.c:1418:12: warning: symbol 'pmac_ide_probe' was not
declared. Should it be static?
Signed-off-by: Wang Wensheng
---
drivers/ide/pmac.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/ide/pmac.c b/drivers/ide/pmac.c
index ea0b064b5f56..6bb2fc6755c2 100644
--- a/drivers/ide/pmac.c
+++ b/drivers/ide/pmac.c
@@ -225,7 +225,7 @@ struct mdma_timings_t {
int cycleTime;
};
-struct mdma_timings_t mdma_timings_33[] =
+static struct mdma_timings_t mdma_timings_33[] =
{
{ 240, 240, 480 },
{ 180, 180, 360 },
@@ -238,7 +238,7 @@ struct mdma_timings_t mdma_timings_33[] =
{ 0, 0, 0 }
};
-struct mdma_timings_t mdma_timings_33k[] =
+static struct mdma_timings_t mdma_timings_33k[] =
{
{ 240, 240, 480 },
{ 180, 180, 360 },
@@ -251,7 +251,7 @@ struct mdma_timings_t mdma_timings_33k[] =
{ 0, 0, 0 }
};
-struct mdma_timings_t mdma_timings_66[] =
+static struct mdma_timings_t mdma_timings_66[] =
{
{ 240, 240, 480 },
{ 180, 180, 360 },
@@ -265,7 +265,7 @@ struct mdma_timings_t mdma_timings_66[] =
};
/* KeyLargo ATA-4 Ultra DMA timings (rounded) */
-struct {
+static struct {
int addrSetup; /* ??? */
int rdy2pause;
int wrDataSetup;
@@ -1415,7 +1415,7 @@ static struct pci_driver pmac_ide_pci_driver = {
};
MODULE_DEVICE_TABLE(pci, pmac_ide_pci_match);
-int __init pmac_ide_probe(void)
+static int __init pmac_ide_probe(void)
{
int error;
--
2.25.0
[PATCH 2/2] ASoC: dt-bindings: fsl_xcvr: Add document for XCVR
From: Viorel Suman
XCVR (Audio Transceiver) is a new IP module found on i.MX8MP.
Signed-off-by: Viorel Suman
---
.../devicetree/bindings/sound/fsl,xcvr.yaml| 104 +
1 file changed, 104 insertions(+)
create mode 100644 Documentation/devicetree/bindings/sound/fsl,xcvr.yaml
diff --git a/Documentation/devicetree/bindings/sound/fsl,xcvr.yaml
b/Documentation/devicetree/bindings/sound/fsl,xcvr.yaml
new file mode 100644
index ..d4bb792
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/fsl,xcvr.yaml
@@ -0,0 +1,104 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/fsl,xcvr.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP Audio Transceiver (XCVR) Controller
+
+maintainers:
+ - Viorel Suman
+
+properties:
+ $nodename:
+pattern: "^xcvr@.*"
+
+ compatible:
+const: fsl,imx8mp-xcvr
+
+ reg:
+items:
+ - description: 20K RAM for code and data
+ - description: registers space
+ - description: RX FIFO address
+ - description: TX FIFO address
+
+ reg-names:
+items:
+ - const: ram
+ - const: regs
+ - const: rxfifo
+ - const: txfifo
+
+ interrupts:
+maxItems: 3
+
+ clocks:
+items:
+ - description: Peripheral clock
+ - description: PHY clock
+ - description: SPBA clock
+ - description: PLL clock
+
+ clock-names:
+items:
+ - const: ipg
+ - const: phy
+ - const: spba
+ - const: pll_ipg
+
+ dmas:
+maxItems: 2
+
+ dma-names:
+items:
+ - const: rx
+ - const: tx
+
+ firmware-name:
+$ref: /schemas/types.yaml#/definitions/string
+const: imx/xcvr/xcvr-imx8mp.bin
+description: |
+ Should contain the name of the default firmware image
+ file located on the firmware search path
+
+ resets:
+maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - interrupts
+ - clocks
+ - clock-names
+ - dmas
+ - dma-names
+ - firmware-name
+ - resets
+
+examples:
+ - |
+#include
+#include
+
+xcvr: xcvr@30cc {
+ compatible = "fsl,imx8mp-xcvr";
+ reg = <0x30cc 0x800>,
+ <0x30cc0800 0x400>,
+ <0x30cc0c00 0x080>,
+ <0x30cc0e00 0x080>;
+ reg-names = "ram", "regs", "rxfifo", "txfifo";
+ interrupts = , /* XCVR IRQ 0 */
+, /* XCVR IRQ 1 */
+; /* XCVR PHY - SPDIF
wakeup IRQ */
+ clocks = <&audiomix_clk IMX8MP_CLK_AUDIOMIX_EARC_IPG>,
+<&audiomix_clk IMX8MP_CLK_AUDIOMIX_EARC_PHY>,
+<&audiomix_clk IMX8MP_CLK_AUDIOMIX_SPBA2_ROOT>,
+<&audiomix_clk IMX8MP_CLK_AUDIOMIX_AUDPLL_ROOT>;
+ clock-names = "ipg", "phy", "spba", "pll_ipg";
+ dmas = <&sdma2 30 2 0>, <&sdma2 31 2 0>;
+ dma-names = "rx", "tx";
+ firmware-name = "imx/xcvr/xcvr-imx8mp.bin";
+ resets = <&audiomix_reset 0>;
+};
--
2.7.4
[PATCH 1/2] ASoC: fsl_xcvr: Add XCVR ASoC CPU DAI driver
From: Viorel Suman
XCVR (Audio Transceiver) is a on-chip functional module found
on i.MX8MP. It support HDMI2.1 eARC, HDMI1.4 ARC and SPDIF.
Signed-off-by: Viorel Suman
---
sound/soc/fsl/Kconfig| 10 +
sound/soc/fsl/Makefile |2 +
sound/soc/fsl/fsl_xcvr.c | 1352 ++
sound/soc/fsl/fsl_xcvr.h | 266 +
4 files changed, 1630 insertions(+)
create mode 100644 sound/soc/fsl/fsl_xcvr.c
create mode 100644 sound/soc/fsl/fsl_xcvr.h
diff --git a/sound/soc/fsl/Kconfig b/sound/soc/fsl/Kconfig
index 3f76ff7..d04b64d 100644
--- a/sound/soc/fsl/Kconfig
+++ b/sound/soc/fsl/Kconfig
@@ -95,6 +95,16 @@ config SND_SOC_FSL_EASRC
destination sample rate. It is a new design module compare with the
old ASRC.
+config SND_SOC_FSL_XCVR
+ tristate "NXP Audio Transceiver (XCVR) module support"
+ select REGMAP_MMIO
+ select SND_SOC_IMX_PCM_DMA if SND_IMX_SOC != n
+ select SND_SOC_GENERIC_DMAENGINE_PCM
+ help
+ Say Y if you want to add Audio Transceiver (XCVR) support for NXP
+ iMX CPUs. XCVR is a digital module that supports HDMI2.1 eARC,
+ HDMI1.4 ARC and SPDIF.
+
config SND_SOC_FSL_UTILS
tristate
diff --git a/sound/soc/fsl/Makefile b/sound/soc/fsl/Makefile
index b835eeb..1d2231f 100644
--- a/sound/soc/fsl/Makefile
+++ b/sound/soc/fsl/Makefile
@@ -25,6 +25,7 @@ snd-soc-fsl-utils-objs := fsl_utils.o
snd-soc-fsl-dma-objs := fsl_dma.o
snd-soc-fsl-mqs-objs := fsl_mqs.o
snd-soc-fsl-easrc-objs := fsl_easrc.o
+snd-soc-fsl-xcvr-objs := fsl_xcvr.o
obj-$(CONFIG_SND_SOC_FSL_AUDMIX) += snd-soc-fsl-audmix.o
obj-$(CONFIG_SND_SOC_FSL_ASOC_CARD) += snd-soc-fsl-asoc-card.o
@@ -38,6 +39,7 @@ obj-$(CONFIG_SND_SOC_FSL_UTILS) += snd-soc-fsl-utils.o
obj-$(CONFIG_SND_SOC_FSL_MQS) += snd-soc-fsl-mqs.o
obj-$(CONFIG_SND_SOC_FSL_EASRC) += snd-soc-fsl-easrc.o
obj-$(CONFIG_SND_SOC_POWERPC_DMA) += snd-soc-fsl-dma.o
+obj-$(CONFIG_SND_SOC_FSL_XCVR) += snd-soc-fsl-xcvr.o
# MPC5200 Platform Support
obj-$(CONFIG_SND_MPC52xx_DMA) += mpc5200_dma.o
diff --git a/sound/soc/fsl/fsl_xcvr.c b/sound/soc/fsl/fsl_xcvr.c
new file mode 100644
index ..2e66f22
--- /dev/null
+++ b/sound/soc/fsl/fsl_xcvr.c
@@ -0,0 +1,1352 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright 2019 NXP
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "fsl_xcvr.h"
+#include "imx-pcm.h"
+
+#define FSL_XCVR_CAPDS_SIZE256
+
+struct fsl_xcvr {
+ struct platform_device *pdev;
+ struct regmap *regmap;
+ struct clk *ipg_clk;
+ struct clk *pll_ipg_clk;
+ struct clk *phy_clk;
+ struct clk *spba_clk;
+ struct reset_control *reset;
+ const char *fw_name;
+ u8 streams;
+ u32 mode;
+ u32 arc_mode;
+ void __iomem *ram_addr;
+ struct snd_dmaengine_dai_dma_data dma_prms_rx;
+ struct snd_dmaengine_dai_dma_data dma_prms_tx;
+ struct snd_aes_iec958 rx_iec958;
+ struct snd_aes_iec958 tx_iec958;
+ u8 cap_ds[FSL_XCVR_CAPDS_SIZE];
+};
+
+static const struct fsl_xcvr_pll_conf {
+ u8 mfi; /* min=0x18, max=0x38 */
+ u32 mfn; /* signed int, 2's compl., min=0x3FFF, max=0x0001 */
+ u32 mfd; /* unsigned int */
+ u32 fout; /* Fout = Fref*(MFI + MFN/MFD), Fref is 24MHz */
+} fsl_xcvr_pll_cfg[] = {
+ { .mfi = 54, .mfn = 1, .mfd = 6, .fout = 13, }, /* 1.3 GHz */
+ { .mfi = 32, .mfn = 96, .mfd = 125, .fout = 786432000, }, /* 8000 Hz */
+ { .mfi = 30, .mfn = 66, .mfd = 625, .fout = 722534400, }, /* 11025 Hz
*/
+ { .mfi = 29, .mfn = 1, .mfd = 6, .fout = 7, }, /* 700 MHz */
+};
+
+static const u32 fsl_xcvr_earc_channels[] = { 1, 2, 8, 16, 32, }; /* one bit
6, 12 ? */
+static const struct snd_pcm_hw_constraint_list fsl_xcvr_earc_channels_constr =
{
+ .count = ARRAY_SIZE(fsl_xcvr_earc_channels),
+ .list = fsl_xcvr_earc_channels,
+};
+
+static const u32 fsl_xcvr_earc_rates[] = {
+ 32000, 44100, 48000, 64000, 88200, 96000,
+ 128000, 176400, 192000, 256000, 352800, 384000,
+ 512000, 705600, 768000, 1024000, 1411200, 1536000,
+};
+static const struct snd_pcm_hw_constraint_list fsl_xcvr_earc_rates_constr = {
+ .count = ARRAY_SIZE(fsl_xcvr_earc_rates),
+ .list = fsl_xcvr_earc_rates,
+};
+
+static const u32 fsl_xcvr_spdif_channels[] = { 2, };
+static const struct snd_pcm_hw_constraint_list fsl_xcvr_spdif_channels_constr
= {
+ .count = ARRAY_SIZE(fsl_xcvr_spdif_channels),
+ .list = fsl_xcvr_spdif_channels,
+};
+
+static const u32 fsl_xcvr_spdif_rates[] = {
+ 32000, 44100, 48000, 88200, 96000, 176400, 192000,
+};
+static const struct snd_pcm_hw_constraint_list fsl_xcvr_spdif_rates_constr = {
+ .count = ARRAY_SIZE(fsl_xcvr_spdif_rates),
+ .list = fsl_xcvr_spdif_rates,
+};
+
+static int fsl_xcvr_arc_mode_put(struct snd_kc
[PATCH 0/2] DAI driver for new XCVR IP
From: Viorel Suman DAI driver for new XCVR IP found in i.MX8MP. Viorel Suman (2): ASoC: fsl_xcvr: Add XCVR ASoC CPU DAI driver ASoC: dt-bindings: fsl_xcvr: Add document for XCVR .../devicetree/bindings/sound/fsl,xcvr.yaml| 104 ++ sound/soc/fsl/Kconfig | 10 + sound/soc/fsl/Makefile |2 + sound/soc/fsl/fsl_xcvr.c | 1352 sound/soc/fsl/fsl_xcvr.h | 266 5 files changed, 1734 insertions(+) create mode 100644 Documentation/devicetree/bindings/sound/fsl,xcvr.yaml create mode 100644 sound/soc/fsl/fsl_xcvr.c create mode 100644 sound/soc/fsl/fsl_xcvr.h -- 2.7.4
Re: [PATCH] Revert "powerpc/64s: machine check interrupt update NMI accounting"
On Tue, Sep 15, 2020 at 08:16:42PM +0200, pet...@infradead.org wrote:
> On Tue, Sep 15, 2020 at 08:06:59PM +0200, Michal Suchanek wrote:
> > This reverts commit 116ac378bb3ff844df333e7609e7604651a0db9d.
> >
> > This commit causes the kernel to oops and reboot when injecting a SLB
> > multihit which causes a MCE.
> >
> > Before this commit a SLB multihit was corrected by the kernel and the
> > system continued to operate normally.
> >
> > cc: sta...@vger.kernel.org
> > Fixes: 116ac378bb3f ("powerpc/64s: machine check interrupt update NMI
> > accounting")
> > Signed-off-by: Michal Suchanek
>
> Ever since 69ea03b56ed2 ("hardirq/nmi: Allow nested nmi_enter()")
> nmi_enter() supports nesting natively.
And this patch was merged in parallel with this native nesting support
and conflicted with it - hence the explicit nesting in the hunk that did
not conflict.
Either way the bug is present on kernels both with and without
69ea03b56ed2. So besides the conflict 69ea03b56ed2 does not affect this
problem.
Thanks
Michal
[PATCH 5/5] arm: dts: ls1021a: fix rcpm failed to claim resource
The range of dcfg reg is wrong, which overlap with other device,
such as rcpm. This issue causing rcpm driver failed to claim
reg resource when calling devm_ioremap_resource().
Signed-off-by: Ran Wang
---
arch/arm/boot/dts/ls1021a.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
index e372630f..286c547 100644
--- a/arch/arm/boot/dts/ls1021a.dtsi
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -173,7 +173,7 @@
dcfg: dcfg@1ee {
compatible = "fsl,ls1021a-dcfg", "syscon";
- reg = <0x0 0x1ee 0x0 0x1>;
+ reg = <0x0 0x1ee 0x0 0x1000>;
big-endian;
};
--
2.7.4
[PATCH 4/5] arm: dts: ls1021a: fix flextimer failed to wake system
The data of property 'fsl,rcpm-wakeup' is not corrcet, which causing RCPM driver incorrectly program register IPPDEXPCR1, then flextimer is wrongly clock gated during system suspend, can't send interrupt to wake. Signed-off-by: Ran Wang --- arch/arm/boot/dts/ls1021a.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi index 089fe86..e372630f 100644 --- a/arch/arm/boot/dts/ls1021a.dtsi +++ b/arch/arm/boot/dts/ls1021a.dtsi @@ -1014,7 +1014,7 @@ compatible = "fsl,ls1021a-ftm-alarm"; reg = <0x0 0x29d 0x0 0x1>; reg-names = "ftm"; - fsl,rcpm-wakeup = <&rcpm 0x2 0x0>; + fsl,rcpm-wakeup = <&rcpm 0x0 0x2000>; interrupts = ; big-endian; }; -- 2.7.4
[PATCH 3/5] arm: dts: ls1021a: fix that FlexTimer cannot wakeup system in deep sleep
From: Biwen Li
The patch fixes a bug that FlexTimer cannot
wakeup system in deep sleep.
Signed-off-by: Biwen Li
Signed-off-by: Ran Wang
---
arch/arm/boot/dts/ls1021a.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
index 827373e..089fe86 100644
--- a/arch/arm/boot/dts/ls1021a.dtsi
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -1007,6 +1007,7 @@
compatible = "fsl,ls1021a-rcpm", "fsl,qoriq-rcpm-2.1+";
reg = <0x0 0x1ee2140 0x0 0x8>;
#fsl,rcpm-wakeup-cells = <2>;
+ fsl,ippdexpcr1-alt-addr = <&scfg 0x51c>;
};
ftm_alarm0: timer0@29d {
--
2.7.4
[PATCH 2/5] soc: fsl: handle RCPM errata A-008646 on SoC LS1021A
From: Biwen Li
Description:
- Reading configuration register RCPM_IPPDEXPCR1
always return zero
Workaround:
- Save register RCPM_IPPDEXPCR1's value to
register SCFG_SPARECR8.(uboot's psci also
need reading value from the register SCFG_SPARECR8
to set register RCPM_IPPDEXPCR1)
Impact:
- FlexTimer module will cannot wakeup system in
deep sleep on SoC LS1021A
Signed-off-by: Biwen Li
Signed-off-by: Ran Wang
---
drivers/soc/fsl/rcpm.c | 42 +-
1 file changed, 41 insertions(+), 1 deletion(-)
diff --git a/drivers/soc/fsl/rcpm.c b/drivers/soc/fsl/rcpm.c
index a093dbe..e6354f5 100644
--- a/drivers/soc/fsl/rcpm.c
+++ b/drivers/soc/fsl/rcpm.c
@@ -2,7 +2,7 @@
//
// rcpm.c - Freescale QorIQ RCPM driver
//
-// Copyright 2019 NXP
+// Copyright 2019-2020 NXP
//
// Author: Ran Wang
@@ -13,6 +13,9 @@
#include
#include
#include
+#include
+#include
+#include
#define RCPM_WAKEUP_CELL_MAX_SIZE 7
@@ -37,6 +40,9 @@ static int rcpm_pm_prepare(struct device *dev)
struct device_node *np = dev->of_node;
u32 value[RCPM_WAKEUP_CELL_MAX_SIZE + 1];
u32 setting[RCPM_WAKEUP_CELL_MAX_SIZE] = {0};
+ struct regmap *scfg_addr_regmap = NULL;
+ u32 reg_offset[2];
+ u32 reg_value = 0;
rcpm = dev_get_drvdata(dev);
if (!rcpm)
@@ -90,6 +96,40 @@ static int rcpm_pm_prepare(struct device *dev)
tmp |= ioread32be(address);
iowrite32be(tmp, address);
}
+ /*
+* Workaround of errata A-008646 on SoC LS1021A:
+* There is a bug of register ippdexpcr1.
+* Reading configuration register RCPM_IPPDEXPCR1
+* always return zero. So save ippdexpcr1's value
+* to register SCFG_SPARECR8.And the value of
+* ippdexpcr1 will be read from SCFG_SPARECR8.
+*/
+ if (device_property_present(dev, "fsl,ippdexpcr1-alt-addr")) {
+ if (dev_of_node(dev)) {
+ scfg_addr_regmap =
syscon_regmap_lookup_by_phandle(np,
+
"fsl,ippdexpcr1-alt-addr");
+ } else if (is_acpi_node(dev->fwnode)) {
+ continue;
+ }
+
+ if (scfg_addr_regmap && (i == 1)) {
+ if (device_property_read_u32_array(dev,
+ "fsl,ippdexpcr1-alt-addr",
+ reg_offset,
+ 2)) {
+ scfg_addr_regmap = NULL;
+ continue;
+ }
+ /* Read value from register SCFG_SPARECR8 */
+ regmap_read(scfg_addr_regmap,
+ reg_offset[1],
+ ®_value);
+ /* Write value to register SCFG_SPARECR8 */
+ regmap_write(scfg_addr_regmap,
+reg_offset[1],
+tmp | reg_value);
+ }
+ }
}
return 0;
--
2.7.4
[PATCH 1/5] Documentation: dt: binding: fsl: Add 'fsl, ippdexpcr1-alt-addr' property
From: Biwen Li
The 'fsl,ippdexpcr1-alt-addr' property is used to handle an errata A-008646
on LS1021A
Signed-off-by: Biwen Li
Signed-off-by: Ran Wang
---
Documentation/devicetree/bindings/soc/fsl/rcpm.txt | 19 +++
1 file changed, 19 insertions(+)
diff --git a/Documentation/devicetree/bindings/soc/fsl/rcpm.txt
b/Documentation/devicetree/bindings/soc/fsl/rcpm.txt
index 5a33619..1be58a3 100644
--- a/Documentation/devicetree/bindings/soc/fsl/rcpm.txt
+++ b/Documentation/devicetree/bindings/soc/fsl/rcpm.txt
@@ -34,6 +34,11 @@ Chassis Version Example Chips
Optional properties:
- little-endian : RCPM register block is Little Endian. Without it RCPM
will be Big Endian (default case).
+ - fsl,ippdexpcr1-alt-addr : The property is related to a hardware issue
+ on SoC LS1021A and only needed on SoC LS1021A.
+ Must include 2 entries:
+ The first entry must be a link to the SCFG device node.
+ The 2nd entry must be offset of register IPPDEXPCR1 in SCFG.
Example:
The RCPM node for T4240:
@@ -43,6 +48,20 @@ The RCPM node for T4240:
#fsl,rcpm-wakeup-cells = <2>;
};
+The RCPM node for LS1021A:
+ rcpm: rcpm@1ee2140 {
+ compatible = "fsl,ls1021a-rcpm", "fsl,qoriq-rcpm-2.1+";
+ reg = <0x0 0x1ee2140 0x0 0x8>;
+ #fsl,rcpm-wakeup-cells = <2>;
+
+ /*
+* The second and third entry compose an alt offset
+* address for IPPDEXPCR1(SCFG_SPARECR8)
+*/
+ fsl,ippdexpcr1-alt-addr = <&scfg 0x51c>;
+ };
+
+
* Freescale RCPM Wakeup Source Device Tree Bindings
---
Required fsl,rcpm-wakeup property should be added to a device node if the
device
--
2.7.4
Re: [PATCH v3] pseries/hotplug-memory: hot-add: skip redundant LMB lookup
Le 15/09/2020 à 21:46, Scott Cheloha a écrit : During memory hot-add, dlpar_add_lmb() calls memory_add_physaddr_to_nid() to determine which node id (nid) to use when later calling __add_memory(). This is wasteful. On pseries, memory_add_physaddr_to_nid() finds an appropriate nid for a given address by looking up the LMB containing the address and then passing that LMB to of_drconf_to_nid_single() to get the nid. In dlpar_add_lmb() we get this address from the LMB itself. In short, we have a pointer to an LMB and then we are searching for that LMB *again* in order to find its nid. If we call of_drconf_to_nid_single() directly from dlpar_add_lmb() we can skip the redundant lookup. The only error handling we need to duplicate from memory_add_physaddr_to_nid() is the fallback to the default nid when drconf_to_nid_single() returns -1 (NUMA_NO_NODE) or an invalid nid. Skipping the extra lookup makes hot-add operations faster, especially on machines with many LMBs. Consider an LPAR with 126976 LMBs. In one test, hot-adding 126000 LMBs on an upatched kernel took ~3.5 hours while a patched kernel completed the same operation in ~2 hours: Unpatched (12450 seconds): Sep 9 04:06:31 ltc-brazos1 drmgr[810169]: drmgr: -c mem -a -q 126000 Sep 9 04:06:31 ltc-brazos1 kernel: pseries-hotplug-mem: Attempting to hot-add 126000 LMB(s) [...] Sep 9 07:34:01 ltc-brazos1 kernel: pseries-hotplug-mem: Memory at 2000 (drc index 8002) was hot-added Patched (7065 seconds): Sep 8 21:49:57 ltc-brazos1 drmgr[877703]: drmgr: -c mem -a -q 126000 Sep 8 21:49:57 ltc-brazos1 kernel: pseries-hotplug-mem: Attempting to hot-add 126000 LMB(s) [...] Sep 8 23:27:42 ltc-brazos1 kernel: pseries-hotplug-mem: Memory at 2000 (drc index 8002) was hot-added It should be noted that the speedup grows more substantial when hot-adding LMBs at the end of the drconf range. This is because we are skipping a linear LMB search. To see the distinction, consider smaller hot-add test on the same LPAR. A perf-stat run with 10 iterations showed that hot-adding 4096 LMBs completed less than 1 second faster on a patched kernel: Unpatched: Performance counter stats for 'drmgr -c mem -a -q 4096' (10 runs): 104,753.42 msec task-clock#0.992 CPUs utilized ( +- 0.55% ) 4,708 context-switches #0.045 K/sec ( +- 0.69% ) 2,444 cpu-migrations#0.023 K/sec ( +- 1.25% ) 394 page-faults #0.004 K/sec ( +- 0.22% ) 445,902,503,057 cycles#4.257 GHz ( +- 0.55% ) (66.67%) 8,558,376,740 stalled-cycles-frontend #1.92% frontend cycles idle ( +- 0.88% ) (49.99%) 300,346,181,651 stalled-cycles-backend# 67.36% backend cycles idle ( +- 0.76% ) (50.01%) 258,091,488,691 instructions #0.58 insn per cycle #1.16 stalled cycles per insn ( +- 0.22% ) (66.67%) 70,568,169,256 branches # 673.660 M/sec ( +- 0.17% ) (50.01%) 3,100,725,426 branch-misses #4.39% of all branches ( +- 0.20% ) (49.99%) 105.583 +- 0.589 seconds time elapsed ( +- 0.56% ) Patched: Performance counter stats for 'drmgr -c mem -a -q 4096' (10 runs): 104,055.69 msec task-clock#0.993 CPUs utilized ( +- 0.32% ) 4,606 context-switches #0.044 K/sec ( +- 0.20% ) 2,463 cpu-migrations#0.024 K/sec ( +- 0.93% ) 394 page-faults #0.004 K/sec ( +- 0.25% ) 442,951,129,921 cycles#4.257 GHz ( +- 0.32% ) (66.66%) 8,710,413,329 stalled-cycles-frontend #1.97% frontend cycles idle ( +- 0.47% ) (50.06%) 299,656,905,836 stalled-cycles-backend# 67.65% backend cycles idle ( +- 0.39% ) (50.02%) 252,731,168,193 instructions #0.57 insn per cycle #1.19 stalled cycles per insn ( +- 0.20% ) (66.66%) 68,902,851,121 branches # 662.173 M/sec ( +- 0.13% ) (49.94%) 3,100,242,882 branch-misses #4.50% of all branches ( +- 0.15% ) (49.98%) 104.829 +- 0.325 seconds time elapsed ( +- 0.31% ) This is consistent. An add-by-count hot-add operation adds LMBs greedily, so LMBs near the start of the drconf range are considered first. On an otherwise idle LPAR with so many LMBs we would expect to find the LMBs we need near the start of the d
Re: [PATCH] Doc: admin-guide: Add entry for kvm_cma_resv_ratio kernel param
Hi Randy,
Thanks for the comments, will send a V2 fixing them.
On Tue, Sep 15, 2020 at 11:18:52PM -0700, Randy Dunlap wrote:
> On 9/15/20 11:11 PM, sathn...@linux.vnet.ibm.com wrote:
> > From: Satheesh Rajendran
> >
> > Add document entry for kvm_cma_resv_ratio kernel param which
> > is used to alter the KVM contiguous memory allocation percentage
> > for hash pagetable allocation used by hash mode PowerPC KVM guests.
> >
> > Cc: linux-ker...@vger.kernel.org
> > Cc: kvm-...@vger.kernel.org
> > Cc: linuxppc-dev@lists.ozlabs.org
> > Cc: Paul Mackerras
> > Cc: Michael Ellerman
> > Cc: Jonathan Corbet
> > Signed-off-by: Satheesh Rajendran
> > ---
> > Documentation/admin-guide/kernel-parameters.txt | 9 +
> > 1 file changed, 9 insertions(+)
> >
> > diff --git a/Documentation/admin-guide/kernel-parameters.txt
> > b/Documentation/admin-guide/kernel-parameters.txt
> > index a1068742a6df..9cb126573c71 100644
> > --- a/Documentation/admin-guide/kernel-parameters.txt
> > +++ b/Documentation/admin-guide/kernel-parameters.txt
> > @@ -599,6 +599,15 @@
> > altogether. For more information, see
> > include/linux/dma-contiguous.h
> >
> > +kvm_cma_resv_ratio=n
> > +[PPC]
>
> You can put [PPC] on the line above.
>
sure
> > +Reserves given percentage from system memory area
> > for
> > +contiguous memory allocation for KVM hash pagetable
> > +allocation.
> > +Bydefault it reserves 5% of total system memory.
>
> By default
>
> > +Format:
> > +Default: 5
> > +
>
> and please use tabs for indentation, not all spaces.
>
sure
> > cmo_free_hint= [PPC] Format: { yes | no }
> > Specify whether pages are marked as being inactive
> > when they are freed. This is used in CMO environments
> >
>
> Entries in kernel-parameters.txt should be sorted into dictionary order,
> so please put that with the other kvm parameters.
>
sure.
> thanks.
> --
> ~Randy
>
Thanks!
-Satheesh.
[PATCH v1] powerpc: fix EDEADLOCK redefinition error in uapi/asm/errno.h
A few archs like powerpc have different errno.h values for macros
EDEADLOCK and EDEADLK. In code including both libc and linux versions of
errno.h, this can result in multiple definitions of EDEADLOCK in the
include chain. Definitions to the same value (e.g. seen with mips) do
not raise warnings, but on powerpc there are redefinitions changing the
value, which raise warnings and errors (if using "-Werror").
Guard against these redefinitions to avoid build errors like the following,
first seen cross-compiling libbpf v5.8.9 for powerpc using GCC 8.4.0 with
musl 1.1.24:
In file included from ../../arch/powerpc/include/uapi/asm/errno.h:5,
from ../../include/linux/err.h:8,
from libbpf.c:29:
../../include/uapi/asm-generic/errno.h:40: error: "EDEADLOCK" redefined
[-Werror]
#define EDEADLOCK EDEADLK
In file included from
toolchain-powerpc_8540_gcc-8.4.0_musl/include/errno.h:10,
from libbpf.c:26:
toolchain-powerpc_8540_gcc-8.4.0_musl/include/bits/errno.h:58: note: this is
the location of the previous definition
#define EDEADLOCK 58
cc1: all warnings being treated as errors
make[5]: ***
[target-powerpc_8540_musl/bpftools-5.8.9/tools/build/Makefile.build:97:
/home/kodidev/openwrt-project/build_dir/target-powerpc_8540_musl/bpftools-minimal/bpftools-5.8.9//libbpf/staticobjs/libbpf.o]
Error 1
Fixes: 95f28190aa01 ("tools include arch: Grab a copy of errno.h for arch's
supported by perf")
Fixes: c3617f72036c ("UAPI: (Scripted) Disintegrate arch/powerpc/include/asm")
Reported-by: Rosen Penev
Signed-off-by: Tony Ambardar
---
arch/powerpc/include/uapi/asm/errno.h | 1 +
tools/arch/powerpc/include/uapi/asm/errno.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/arch/powerpc/include/uapi/asm/errno.h
b/arch/powerpc/include/uapi/asm/errno.h
index cc79856896a1..4ba87de32be0 100644
--- a/arch/powerpc/include/uapi/asm/errno.h
+++ b/arch/powerpc/include/uapi/asm/errno.h
@@ -2,6 +2,7 @@
#ifndef _ASM_POWERPC_ERRNO_H
#define _ASM_POWERPC_ERRNO_H
+#undef EDEADLOCK
#include
#undef EDEADLOCK
diff --git a/tools/arch/powerpc/include/uapi/asm/errno.h
b/tools/arch/powerpc/include/uapi/asm/errno.h
index cc79856896a1..4ba87de32be0 100644
--- a/tools/arch/powerpc/include/uapi/asm/errno.h
+++ b/tools/arch/powerpc/include/uapi/asm/errno.h
@@ -2,6 +2,7 @@
#ifndef _ASM_POWERPC_ERRNO_H
#define _ASM_POWERPC_ERRNO_H
+#undef EDEADLOCK
#include
#undef EDEADLOCK
--
2.25.1
Re: [PATCH v3] pseries/hotplug-memory: hot-add: skip redundant LMB lookup
On 15.09.20 21:46, Scott Cheloha wrote: > During memory hot-add, dlpar_add_lmb() calls memory_add_physaddr_to_nid() > to determine which node id (nid) to use when later calling __add_memory(). > > This is wasteful. On pseries, memory_add_physaddr_to_nid() finds an > appropriate nid for a given address by looking up the LMB containing the > address and then passing that LMB to of_drconf_to_nid_single() to get the > nid. In dlpar_add_lmb() we get this address from the LMB itself. > > In short, we have a pointer to an LMB and then we are searching for > that LMB *again* in order to find its nid. > > If we call of_drconf_to_nid_single() directly from dlpar_add_lmb() we > can skip the redundant lookup. The only error handling we need to > duplicate from memory_add_physaddr_to_nid() is the fallback to the > default nid when drconf_to_nid_single() returns -1 (NUMA_NO_NODE) or > an invalid nid. > > Skipping the extra lookup makes hot-add operations faster, especially > on machines with many LMBs. > > Consider an LPAR with 126976 LMBs. In one test, hot-adding 126000 > LMBs on an upatched kernel took ~3.5 hours while a patched kernel > completed the same operation in ~2 hours: > > Unpatched (12450 seconds): > Sep 9 04:06:31 ltc-brazos1 drmgr[810169]: drmgr: -c mem -a -q 126000 > Sep 9 04:06:31 ltc-brazos1 kernel: pseries-hotplug-mem: Attempting to > hot-add 126000 LMB(s) > [...] > Sep 9 07:34:01 ltc-brazos1 kernel: pseries-hotplug-mem: Memory at 2000 > (drc index 8002) was hot-added > > Patched (7065 seconds): > Sep 8 21:49:57 ltc-brazos1 drmgr[877703]: drmgr: -c mem -a -q 126000 > Sep 8 21:49:57 ltc-brazos1 kernel: pseries-hotplug-mem: Attempting to > hot-add 126000 LMB(s) > [...] > Sep 8 23:27:42 ltc-brazos1 kernel: pseries-hotplug-mem: Memory at 2000 > (drc index 8002) was hot-added > > It should be noted that the speedup grows more substantial when > hot-adding LMBs at the end of the drconf range. This is because we > are skipping a linear LMB search. > > To see the distinction, consider smaller hot-add test on the same > LPAR. A perf-stat run with 10 iterations showed that hot-adding 4096 > LMBs completed less than 1 second faster on a patched kernel: > > Unpatched: > Performance counter stats for 'drmgr -c mem -a -q 4096' (10 runs): > > 104,753.42 msec task-clock#0.992 CPUs utilized > ( +- 0.55% ) > 4,708 context-switches #0.045 K/sec > ( +- 0.69% ) > 2,444 cpu-migrations#0.023 K/sec > ( +- 1.25% ) >394 page-faults #0.004 K/sec > ( +- 0.22% ) >445,902,503,057 cycles#4.257 GHz > ( +- 0.55% ) (66.67%) > 8,558,376,740 stalled-cycles-frontend #1.92% frontend cycles > idle ( +- 0.88% ) (49.99%) >300,346,181,651 stalled-cycles-backend# 67.36% backend cycles > idle ( +- 0.76% ) (50.01%) >258,091,488,691 instructions #0.58 insn per cycle > #1.16 stalled cycles > per insn ( +- 0.22% ) (66.67%) > 70,568,169,256 branches # 673.660 M/sec > ( +- 0.17% ) (50.01%) > 3,100,725,426 branch-misses #4.39% of all branches > ( +- 0.20% ) (49.99%) > >105.583 +- 0.589 seconds time elapsed ( +- 0.56% ) > > Patched: > Performance counter stats for 'drmgr -c mem -a -q 4096' (10 runs): > > 104,055.69 msec task-clock#0.993 CPUs utilized > ( +- 0.32% ) > 4,606 context-switches #0.044 K/sec > ( +- 0.20% ) > 2,463 cpu-migrations#0.024 K/sec > ( +- 0.93% ) >394 page-faults #0.004 K/sec > ( +- 0.25% ) >442,951,129,921 cycles#4.257 GHz > ( +- 0.32% ) (66.66%) > 8,710,413,329 stalled-cycles-frontend #1.97% frontend cycles > idle ( +- 0.47% ) (50.06%) >299,656,905,836 stalled-cycles-backend# 67.65% backend cycles > idle ( +- 0.39% ) (50.02%) >252,731,168,193 instructions #0.57 insn per cycle > #1.19 stalled cycles > per insn ( +- 0.20% ) (66.66%) > 68,902,851,121 branches # 662.173 M/sec > ( +- 0.13% ) (49.94%) > 3,100,242,882 branch-misses #4.50% of all branches > ( +- 0.15% ) (49.98%) > >104.829 +- 0.325 seconds time elapsed ( +- 0.31% ) > > This is consistent. An add-by-count hot-add operation adds LMBs > greedily, s
Re: Injecting SLB miltihit crashes kernel 5.9.0-rc5
On 9/15/20 2:13 PM, Michal Suchánek wrote: > Hello, > > Using the SLB mutihit injection test module (which I did not write so I > do not want to post it here) to verify updates on my 5.3 frankernekernel > I found that the kernel crashes with Oops: kernel bad access. > > I tested on latest upstream kernel build that I have at hand and the > result is te same (minus the message - nothing was logged and the kernel > simply rebooted). Yes, SLB multihit recovery is broken upstream. Fix is on the way. > > Since the whole effort to write a real mode MCE handler was supposed to > prevent this maybe the SLB injection module should be added to the > kernel selftests? Yes. We are working on adding SLB injection selftest patches will be posted soon. Thanks, -Mahesh. > > Thanks > > Michal >
