Re: [PATCH] powerpc/perf: Fix hv-24x7 metric events for power10

[Madhavan Srinivasan]

On 10/17/22 7:03 PM, Arnaldo Carvalho de Melo wrote:

Em Fri, Oct 14, 2022 at 07:32:20PM +0530, Kajol Jain escreveu:

Testcase stat_all_metrics.sh fails in powerpc:

90: perf all metrics test : FAILED!

The testcase "stat_all_metrics.sh" verifies perf stat
result for all the metric events present in perf list.
It runs perf metric events with various commands and
expects non-empty metric result.

Incase of powerpc:hv-24x7 events, some of the event count can
be 0 based on system configuration. And if that event used as
denominator in divide equation, it can cause divide by 0
error. The current nest_metric.json file creating divide by 0
issue for some of the metric events, which results in failure
of the "stat_all_metrics.sh" test case.

Most of the metrics events have cycles or an event which
expect to have a larger value as denominator, so adding 1
to the denominator of the metric expression as a fix.

Result in powerpc box after this patch changes:

90: perf all metrics test : Ok

Looks ok, applied. Next time please try to ask others to provide a
Reviewed-by or at least an Acked-by.

Reviewed-by: Madhavan Srinivasan 
I did review this patch yesterday. But missed to send my reviewed-by. My 
bad.

Maddy


- Arnaldo


Fixes: a3cbcadfdfc3 ("perf vendor events power10: Adds 24x7 nest
metric events for power10 platform")
Signed-off-by: Kajol Jain 
---
  .../arch/powerpc/power10/nest_metrics.json| 72 +--
  1 file changed, 36 insertions(+), 36 deletions(-)

diff --git a/tools/perf/pmu-events/arch/powerpc/power10/nest_metrics.json 
b/tools/perf/pmu-events/arch/powerpc/power10/nest_metrics.json
index 8ba3e81c9808..fe050d44374b 100644
--- a/tools/perf/pmu-events/arch/powerpc/power10/nest_metrics.json
+++ b/tools/perf/pmu-events/arch/powerpc/power10/nest_metrics.json
@@ -1,13 +1,13 @@
  [
  {
"MetricName": "VEC_GROUP_PUMP_RETRY_RATIO_P01",
-  "MetricExpr": "(hv_24x7@PM_PB_RTY_VG_PUMP01\\,chip\\=?@ / 
hv_24x7@PM_PB_VG_PUMP01\\,chip\\=?@) * 100",
+  "MetricExpr": "(hv_24x7@PM_PB_RTY_VG_PUMP01\\,chip\\=?@ / (1 + 
hv_24x7@PM_PB_VG_PUMP01\\,chip\\=?@)) * 100",
"ScaleUnit": "1%",
"AggregationMode": "PerChip"
  },
  {
"MetricName": "VEC_GROUP_PUMP_RETRY_RATIO_P23",
-  "MetricExpr": "(hv_24x7@PM_PB_RTY_VG_PUMP23\\,chip\\=?@ / 
hv_24x7@PM_PB_VG_PUMP23\\,chip\\=?@) * 100",
+  "MetricExpr": "(hv_24x7@PM_PB_RTY_VG_PUMP23\\,chip\\=?@ / (1 + 
hv_24x7@PM_PB_VG_PUMP23\\,chip\\=?@)) * 100",
"ScaleUnit": "1%",
"AggregationMode": "PerChip"
  },
@@ -61,13 +61,13 @@
  },
  {
"MetricName": "REMOTE_NODE_PUMPS_RETRIES_RATIO_P01",
-  "MetricExpr": "(hv_24x7@PM_PB_RTY_RNS_PUMP01\\,chip\\=?@ / 
hv_24x7@PM_PB_RNS_PUMP01\\,chip\\=?@) * 100",
+  "MetricExpr": "(hv_24x7@PM_PB_RTY_RNS_PUMP01\\,chip\\=?@ / (1 + 
hv_24x7@PM_PB_RNS_PUMP01\\,chip\\=?@)) * 100",
"ScaleUnit": "1%",
"AggregationMode": "PerChip"
  },
  {
"MetricName": "REMOTE_NODE_PUMPS_RETRIES_RATIO_P23",
-  "MetricExpr": "(hv_24x7@PM_PB_RTY_RNS_PUMP23\\,chip\\=?@ / 
hv_24x7@PM_PB_RNS_PUMP23\\,chip\\=?@) * 100",
+  "MetricExpr": "(hv_24x7@PM_PB_RTY_RNS_PUMP23\\,chip\\=?@ / (1 + 
hv_24x7@PM_PB_RNS_PUMP23\\,chip\\=?@)) * 100",
"ScaleUnit": "1%",
"AggregationMode": "PerChip"
  },
@@ -151,193 +151,193 @@
  },
  {
"MetricName": "XLINK0_OUT_TOTAL_UTILIZATION",
-  "MetricExpr": "((hv_24x7@PM_XLINK0_OUT_ODD_TOTAL_UTIL\\,chip\\=?@ + 
hv_24x7@PM_XLINK0_OUT_EVEN_TOTAL_UTIL\\,chip\\=?@) / 
(hv_24x7@PM_XLINK0_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + 
hv_24x7@PM_XLINK0_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
+  "MetricExpr": "((hv_24x7@PM_XLINK0_OUT_ODD_TOTAL_UTIL\\,chip\\=?@ + 
hv_24x7@PM_XLINK0_OUT_EVEN_TOTAL_UTIL\\,chip\\=?@) / (1 + 
hv_24x7@PM_XLINK0_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + 
hv_24x7@PM_XLINK0_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
"ScaleUnit": "1%",
"AggregationMode": "PerChip"
  },
  {
"MetricName": "XLINK1_OUT_TOTAL_UTILIZATION",
-  "MetricExpr": "((hv_24x7@PM_XLINK1_OUT_ODD_TOTAL_UTIL\\,chip\\=?@ + 
hv_24x7@PM_XLINK1_OUT_EVEN_TOTAL_UTIL\\,chip\\=?@) / 
(hv_24x7@PM_XLINK1_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + 
hv_24x7@PM_XLINK1_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
+  "MetricExpr": "((hv_24x7@PM_XLINK1_OUT_ODD_TOTAL_UTIL\\,chip\\=?@ + 
hv_24x7@PM_XLINK1_OUT_EVEN_TOTAL_UTIL\\,chip\\=?@) / (1 + 
hv_24x7@PM_XLINK1_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + 
hv_24x7@PM_XLINK1_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
"ScaleUnit": "1%",
"AggregationMode": "PerChip"
  },
  {
"MetricName": "XLINK2_OUT_TOTAL_UTILIZATION",
-  "MetricExpr": "((hv_24x7@PM_XLINK2_OUT_ODD_TOTAL_UTIL\\,chip\\=?@ + 
hv_24x7@PM_XLINK2_OUT_EVEN_TOTAL_UTIL\\,chip\\=?@) / 
(hv_24x7@PM_XLINK2_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + 
hv_24x7@PM_XLINK2_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
+  "MetricExpr": 

Re: [PATCH] soc: move from strlcpy with unused retval to strscpy

[Bjorn Andersson]

On Thu, 18 Aug 2022 23:01:06 +0200, Wolfram Sang wrote:
> Follow the advice of the below link and prefer 'strscpy' in this
> subsystem. Conversion is 1:1 because the return value is not used.
> Generated by a coccinelle script.
> 
> 

Applied, thanks!

[1/1] soc: move from strlcpy with unused retval to strscpy
  commit: 3f54a39819324e7adba8ff3c0e2bd97f218bb956

Best regards,
-- 
Bjorn Andersson 

Re: [PATCH AUTOSEL 5.19 05/29] powerpc/hw_breakpoint: Avoid relying on caller synchronization

[Marco Elver]

On Mon, 17 Oct 2022 at 17:08, Sasha Levin  wrote:
>
> From: Marco Elver 
>
> [ Upstream commit f95e5a3d59011eec1257d0e76de1e1f8969d426f ]
>
> Internal data structures (cpu_bps, task_bps) of powerpc's hw_breakpoint
> implementation have relied on nr_bp_mutex serializing access to them.
>
> Before overhauling synchronization of kernel/events/hw_breakpoint.c,
> introduce 2 spinlocks to synchronize cpu_bps and task_bps respectively,
> thus avoiding reliance on callers synchronizing powerpc's hw_breakpoint.
>
> Reported-by: Dmitry Vyukov 
> Signed-off-by: Marco Elver 
> Signed-off-by: Peter Zijlstra (Intel) 
> Acked-by: Dmitry Vyukov 
> Acked-by: Ian Rogers 
> Link: https://lore.kernel.org/r/20220829124719.675715-10-el...@google.com
> Signed-off-by: Sasha Levin 

Backporting this patch seems unnecessary if we're not backporting the
hw_breakpoint overhaul.

Without the overhaul, nothing will break without this patch.

Thanks,
-- Marco

> ---
>  arch/powerpc/kernel/hw_breakpoint.c | 53 ++---
>  1 file changed, 40 insertions(+), 13 deletions(-)
>
> diff --git a/arch/powerpc/kernel/hw_breakpoint.c 
> b/arch/powerpc/kernel/hw_breakpoint.c
> index 2669f80b3a49..8db1a15d7acb 100644
> --- a/arch/powerpc/kernel/hw_breakpoint.c
> +++ b/arch/powerpc/kernel/hw_breakpoint.c
> @@ -15,6 +15,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  #include 
>  #include 
>
> @@ -129,7 +130,14 @@ struct breakpoint {
> bool ptrace_bp;
>  };
>
> +/*
> + * While kernel/events/hw_breakpoint.c does its own synchronization, we 
> cannot
> + * rely on it safely synchronizing internals here; however, we can rely on it
> + * not requesting more breakpoints than available.
> + */
> +static DEFINE_SPINLOCK(cpu_bps_lock);
>  static DEFINE_PER_CPU(struct breakpoint *, cpu_bps[HBP_NUM_MAX]);
> +static DEFINE_SPINLOCK(task_bps_lock);
>  static LIST_HEAD(task_bps);
>
>  static struct breakpoint *alloc_breakpoint(struct perf_event *bp)
> @@ -174,7 +182,9 @@ static int task_bps_add(struct perf_event *bp)
> if (IS_ERR(tmp))
> return PTR_ERR(tmp);
>
> +   spin_lock(_bps_lock);
> list_add(>list, _bps);
> +   spin_unlock(_bps_lock);
> return 0;
>  }
>
> @@ -182,6 +192,7 @@ static void task_bps_remove(struct perf_event *bp)
>  {
> struct list_head *pos, *q;
>
> +   spin_lock(_bps_lock);
> list_for_each_safe(pos, q, _bps) {
> struct breakpoint *tmp = list_entry(pos, struct breakpoint, 
> list);
>
> @@ -191,6 +202,7 @@ static void task_bps_remove(struct perf_event *bp)
> break;
> }
> }
> +   spin_unlock(_bps_lock);
>  }
>
>  /*
> @@ -200,12 +212,17 @@ static void task_bps_remove(struct perf_event *bp)
>  static bool all_task_bps_check(struct perf_event *bp)
>  {
> struct breakpoint *tmp;
> +   bool ret = false;
>
> +   spin_lock(_bps_lock);
> list_for_each_entry(tmp, _bps, list) {
> -   if (!can_co_exist(tmp, bp))
> -   return true;
> +   if (!can_co_exist(tmp, bp)) {
> +   ret = true;
> +   break;
> +   }
> }
> -   return false;
> +   spin_unlock(_bps_lock);
> +   return ret;
>  }
>
>  /*
> @@ -215,13 +232,18 @@ static bool all_task_bps_check(struct perf_event *bp)
>  static bool same_task_bps_check(struct perf_event *bp)
>  {
> struct breakpoint *tmp;
> +   bool ret = false;
>
> +   spin_lock(_bps_lock);
> list_for_each_entry(tmp, _bps, list) {
> if (tmp->bp->hw.target == bp->hw.target &&
> -   !can_co_exist(tmp, bp))
> -   return true;
> +   !can_co_exist(tmp, bp)) {
> +   ret = true;
> +   break;
> +   }
> }
> -   return false;
> +   spin_unlock(_bps_lock);
> +   return ret;
>  }
>
>  static int cpu_bps_add(struct perf_event *bp)
> @@ -234,6 +256,7 @@ static int cpu_bps_add(struct perf_event *bp)
> if (IS_ERR(tmp))
> return PTR_ERR(tmp);
>
> +   spin_lock(_bps_lock);
> cpu_bp = per_cpu_ptr(cpu_bps, bp->cpu);
> for (i = 0; i < nr_wp_slots(); i++) {
> if (!cpu_bp[i]) {
> @@ -241,6 +264,7 @@ static int cpu_bps_add(struct perf_event *bp)
> break;
> }
> }
> +   spin_unlock(_bps_lock);
> return 0;
>  }
>
> @@ -249,6 +273,7 @@ static void cpu_bps_remove(struct perf_event *bp)
> struct breakpoint **cpu_bp;
> int i = 0;
>
> +   spin_lock(_bps_lock);
> cpu_bp = per_cpu_ptr(cpu_bps, bp->cpu);
> for (i = 0; i < nr_wp_slots(); i++) {
> if (!cpu_bp[i])
> @@ -260,19 +285,25 @@ static void cpu_bps_remove(struct perf_event *bp)
> break;
> }
> }
> +   spin_unlock(_bps_lock);
>  }

[PATCH AUTOSEL 4.19 05/10] powerpc/64: don't refer nr_cpu_ids in asm code when it's undefined

[Sasha Levin]

From: Yury Norov 

[ Upstream commit 546a073d628111e3338af689938407e77d5dc38f ]

generic_secondary_common_init() calls LOAD_REG_ADDR(r7, nr_cpu_ids)
conditionally on CONFIG_SMP. However, if 'NR_CPUS == 1', kernel doesn't
use the nr_cpu_ids, and in C code, it's just:
  #if NR_CPUS == 1
  #define nr_cpu_ids
  ...

This series makes declaration of nr_cpu_ids conditional on NR_CPUS == 1,
and that reveals the issue, because compiler can't link the
LOAD_REG_ADDR(r7, nr_cpu_ids) against nonexisting symbol.

Current code looks unsafe for those who build kernel with CONFIG_SMP=y and
NR_CPUS == 1. This is weird configuration, but not disallowed.

Fix the linker error by replacing LOAD_REG_ADDR() with LOAD_REG_IMMEDIATE()
conditionally on NR_CPUS == 1.

As the following patch adds CONFIG_FORCE_NR_CPUS option that has the
similar effect on nr_cpu_ids, make the generic_secondary_common_init()
conditional on it too.

Reported-by: Stephen Rothwell 
Signed-off-by: Yury Norov 
Signed-off-by: Sasha Levin 
---
 arch/powerpc/kernel/head_64.S | 4 
 1 file changed, 4 insertions(+)

diff --git a/arch/powerpc/kernel/head_64.S b/arch/powerpc/kernel/head_64.S
index 4f7b225d78cf..4215439a4663 100644
--- a/arch/powerpc/kernel/head_64.S
+++ b/arch/powerpc/kernel/head_64.S
@@ -398,8 +398,12 @@ generic_secondary_common_init:
 #else
LOAD_REG_ADDR(r8, paca_ptrs)/* Load paca_ptrs pointe */
ld  r8,0(r8)/* Get base vaddr of array   */
+#if (NR_CPUS == 1) || defined(CONFIG_FORCE_NR_CPUS)
+   LOAD_REG_IMMEDIATE(r7, NR_CPUS)
+#else
LOAD_REG_ADDR(r7, nr_cpu_ids)   /* Load nr_cpu_ids address   */
lwz r7,0(r7)/* also the max paca allocated   */
+#endif
li  r5,0/* logical cpu id*/
 1:
sldir9,r5,3 /* get paca_ptrs[] index from cpu id */
-- 
2.35.1

[PATCH AUTOSEL 5.4 07/13] powerpc/64: don't refer nr_cpu_ids in asm code when it's undefined

[Sasha Levin]

From: Yury Norov 

[ Upstream commit 546a073d628111e3338af689938407e77d5dc38f ]

generic_secondary_common_init() calls LOAD_REG_ADDR(r7, nr_cpu_ids)
conditionally on CONFIG_SMP. However, if 'NR_CPUS == 1', kernel doesn't
use the nr_cpu_ids, and in C code, it's just:
  #if NR_CPUS == 1
  #define nr_cpu_ids
  ...

This series makes declaration of nr_cpu_ids conditional on NR_CPUS == 1,
and that reveals the issue, because compiler can't link the
LOAD_REG_ADDR(r7, nr_cpu_ids) against nonexisting symbol.

Current code looks unsafe for those who build kernel with CONFIG_SMP=y and
NR_CPUS == 1. This is weird configuration, but not disallowed.

Fix the linker error by replacing LOAD_REG_ADDR() with LOAD_REG_IMMEDIATE()
conditionally on NR_CPUS == 1.

As the following patch adds CONFIG_FORCE_NR_CPUS option that has the
similar effect on nr_cpu_ids, make the generic_secondary_common_init()
conditional on it too.

Reported-by: Stephen Rothwell 
Signed-off-by: Yury Norov 
Signed-off-by: Sasha Levin 
---
 arch/powerpc/kernel/head_64.S | 4 
 1 file changed, 4 insertions(+)

diff --git a/arch/powerpc/kernel/head_64.S b/arch/powerpc/kernel/head_64.S
index 9019f1395d39..be6e94f203c1 100644
--- a/arch/powerpc/kernel/head_64.S
+++ b/arch/powerpc/kernel/head_64.S
@@ -395,8 +395,12 @@ generic_secondary_common_init:
 #else
LOAD_REG_ADDR(r8, paca_ptrs)/* Load paca_ptrs pointe */
ld  r8,0(r8)/* Get base vaddr of array   */
+#if (NR_CPUS == 1) || defined(CONFIG_FORCE_NR_CPUS)
+   LOAD_REG_IMMEDIATE(r7, NR_CPUS)
+#else
LOAD_REG_ADDR(r7, nr_cpu_ids)   /* Load nr_cpu_ids address   */
lwz r7,0(r7)/* also the max paca allocated   */
+#endif
li  r5,0/* logical cpu id*/
 1:
sldir9,r5,3 /* get paca_ptrs[] index from cpu id */
-- 
2.35.1

[PATCH AUTOSEL 5.10 09/16] powerpc/64: don't refer nr_cpu_ids in asm code when it's undefined

[Sasha Levin]

From: Yury Norov 

[ Upstream commit 546a073d628111e3338af689938407e77d5dc38f ]

generic_secondary_common_init() calls LOAD_REG_ADDR(r7, nr_cpu_ids)
conditionally on CONFIG_SMP. However, if 'NR_CPUS == 1', kernel doesn't
use the nr_cpu_ids, and in C code, it's just:
  #if NR_CPUS == 1
  #define nr_cpu_ids
  ...

This series makes declaration of nr_cpu_ids conditional on NR_CPUS == 1,
and that reveals the issue, because compiler can't link the
LOAD_REG_ADDR(r7, nr_cpu_ids) against nonexisting symbol.

Current code looks unsafe for those who build kernel with CONFIG_SMP=y and
NR_CPUS == 1. This is weird configuration, but not disallowed.

Fix the linker error by replacing LOAD_REG_ADDR() with LOAD_REG_IMMEDIATE()
conditionally on NR_CPUS == 1.

As the following patch adds CONFIG_FORCE_NR_CPUS option that has the
similar effect on nr_cpu_ids, make the generic_secondary_common_init()
conditional on it too.

Reported-by: Stephen Rothwell 
Signed-off-by: Yury Norov 
Signed-off-by: Sasha Levin 
---
 arch/powerpc/kernel/head_64.S | 4 
 1 file changed, 4 insertions(+)

diff --git a/arch/powerpc/kernel/head_64.S b/arch/powerpc/kernel/head_64.S
index 2d6581db0c7b..86f9970d8631 100644
--- a/arch/powerpc/kernel/head_64.S
+++ b/arch/powerpc/kernel/head_64.S
@@ -392,8 +392,12 @@ generic_secondary_common_init:
 #else
LOAD_REG_ADDR(r8, paca_ptrs)/* Load paca_ptrs pointe */
ld  r8,0(r8)/* Get base vaddr of array   */
+#if (NR_CPUS == 1) || defined(CONFIG_FORCE_NR_CPUS)
+   LOAD_REG_IMMEDIATE(r7, NR_CPUS)
+#else
LOAD_REG_ADDR(r7, nr_cpu_ids)   /* Load nr_cpu_ids address   */
lwz r7,0(r7)/* also the max paca allocated   */
+#endif
li  r5,0/* logical cpu id*/
 1:
sldir9,r5,3 /* get paca_ptrs[] index from cpu id */
-- 
2.35.1

[PATCH AUTOSEL 5.10 04/16] powerpc/hw_breakpoint: Avoid relying on caller synchronization

[Sasha Levin]

From: Marco Elver 

[ Upstream commit f95e5a3d59011eec1257d0e76de1e1f8969d426f ]

Internal data structures (cpu_bps, task_bps) of powerpc's hw_breakpoint
implementation have relied on nr_bp_mutex serializing access to them.

Before overhauling synchronization of kernel/events/hw_breakpoint.c,
introduce 2 spinlocks to synchronize cpu_bps and task_bps respectively,
thus avoiding reliance on callers synchronizing powerpc's hw_breakpoint.

Reported-by: Dmitry Vyukov 
Signed-off-by: Marco Elver 
Signed-off-by: Peter Zijlstra (Intel) 
Acked-by: Dmitry Vyukov 
Acked-by: Ian Rogers 
Link: https://lore.kernel.org/r/20220829124719.675715-10-el...@google.com
Signed-off-by: Sasha Levin 
---
 arch/powerpc/kernel/hw_breakpoint.c | 53 ++---
 1 file changed, 40 insertions(+), 13 deletions(-)

diff --git a/arch/powerpc/kernel/hw_breakpoint.c 
b/arch/powerpc/kernel/hw_breakpoint.c
index f4e8f21046f5..b081e60ecc6a 100644
--- a/arch/powerpc/kernel/hw_breakpoint.c
+++ b/arch/powerpc/kernel/hw_breakpoint.c
@@ -15,6 +15,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 
@@ -130,7 +131,14 @@ struct breakpoint {
bool ptrace_bp;
 };
 
+/*
+ * While kernel/events/hw_breakpoint.c does its own synchronization, we cannot
+ * rely on it safely synchronizing internals here; however, we can rely on it
+ * not requesting more breakpoints than available.
+ */
+static DEFINE_SPINLOCK(cpu_bps_lock);
 static DEFINE_PER_CPU(struct breakpoint *, cpu_bps[HBP_NUM_MAX]);
+static DEFINE_SPINLOCK(task_bps_lock);
 static LIST_HEAD(task_bps);
 
 static struct breakpoint *alloc_breakpoint(struct perf_event *bp)
@@ -175,7 +183,9 @@ static int task_bps_add(struct perf_event *bp)
if (IS_ERR(tmp))
return PTR_ERR(tmp);
 
+   spin_lock(_bps_lock);
list_add(>list, _bps);
+   spin_unlock(_bps_lock);
return 0;
 }
 
@@ -183,6 +193,7 @@ static void task_bps_remove(struct perf_event *bp)
 {
struct list_head *pos, *q;
 
+   spin_lock(_bps_lock);
list_for_each_safe(pos, q, _bps) {
struct breakpoint *tmp = list_entry(pos, struct breakpoint, 
list);
 
@@ -192,6 +203,7 @@ static void task_bps_remove(struct perf_event *bp)
break;
}
}
+   spin_unlock(_bps_lock);
 }
 
 /*
@@ -201,12 +213,17 @@ static void task_bps_remove(struct perf_event *bp)
 static bool all_task_bps_check(struct perf_event *bp)
 {
struct breakpoint *tmp;
+   bool ret = false;
 
+   spin_lock(_bps_lock);
list_for_each_entry(tmp, _bps, list) {
-   if (!can_co_exist(tmp, bp))
-   return true;
+   if (!can_co_exist(tmp, bp)) {
+   ret = true;
+   break;
+   }
}
-   return false;
+   spin_unlock(_bps_lock);
+   return ret;
 }
 
 /*
@@ -216,13 +233,18 @@ static bool all_task_bps_check(struct perf_event *bp)
 static bool same_task_bps_check(struct perf_event *bp)
 {
struct breakpoint *tmp;
+   bool ret = false;
 
+   spin_lock(_bps_lock);
list_for_each_entry(tmp, _bps, list) {
if (tmp->bp->hw.target == bp->hw.target &&
-   !can_co_exist(tmp, bp))
-   return true;
+   !can_co_exist(tmp, bp)) {
+   ret = true;
+   break;
+   }
}
-   return false;
+   spin_unlock(_bps_lock);
+   return ret;
 }
 
 static int cpu_bps_add(struct perf_event *bp)
@@ -235,6 +257,7 @@ static int cpu_bps_add(struct perf_event *bp)
if (IS_ERR(tmp))
return PTR_ERR(tmp);
 
+   spin_lock(_bps_lock);
cpu_bp = per_cpu_ptr(cpu_bps, bp->cpu);
for (i = 0; i < nr_wp_slots(); i++) {
if (!cpu_bp[i]) {
@@ -242,6 +265,7 @@ static int cpu_bps_add(struct perf_event *bp)
break;
}
}
+   spin_unlock(_bps_lock);
return 0;
 }
 
@@ -250,6 +274,7 @@ static void cpu_bps_remove(struct perf_event *bp)
struct breakpoint **cpu_bp;
int i = 0;
 
+   spin_lock(_bps_lock);
cpu_bp = per_cpu_ptr(cpu_bps, bp->cpu);
for (i = 0; i < nr_wp_slots(); i++) {
if (!cpu_bp[i])
@@ -261,19 +286,25 @@ static void cpu_bps_remove(struct perf_event *bp)
break;
}
}
+   spin_unlock(_bps_lock);
 }
 
 static bool cpu_bps_check(int cpu, struct perf_event *bp)
 {
struct breakpoint **cpu_bp;
+   bool ret = false;
int i;
 
+   spin_lock(_bps_lock);
cpu_bp = per_cpu_ptr(cpu_bps, cpu);
for (i = 0; i < nr_wp_slots(); i++) {
-   if (cpu_bp[i] && !can_co_exist(cpu_bp[i], bp))
-   return true;
+   if (cpu_bp[i] && !can_co_exist(cpu_bp[i], bp)) {
+   ret = true;
+   break;
+ 

[PATCH AUTOSEL 5.15 10/21] powerpc/64: don't refer nr_cpu_ids in asm code when it's undefined

[Sasha Levin]

From: Yury Norov 

[ Upstream commit 546a073d628111e3338af689938407e77d5dc38f ]

generic_secondary_common_init() calls LOAD_REG_ADDR(r7, nr_cpu_ids)
conditionally on CONFIG_SMP. However, if 'NR_CPUS == 1', kernel doesn't
use the nr_cpu_ids, and in C code, it's just:
  #if NR_CPUS == 1
  #define nr_cpu_ids
  ...

This series makes declaration of nr_cpu_ids conditional on NR_CPUS == 1,
and that reveals the issue, because compiler can't link the
LOAD_REG_ADDR(r7, nr_cpu_ids) against nonexisting symbol.

Current code looks unsafe for those who build kernel with CONFIG_SMP=y and
NR_CPUS == 1. This is weird configuration, but not disallowed.

Fix the linker error by replacing LOAD_REG_ADDR() with LOAD_REG_IMMEDIATE()
conditionally on NR_CPUS == 1.

As the following patch adds CONFIG_FORCE_NR_CPUS option that has the
similar effect on nr_cpu_ids, make the generic_secondary_common_init()
conditional on it too.

Reported-by: Stephen Rothwell 
Signed-off-by: Yury Norov 
Signed-off-by: Sasha Levin 
---
 arch/powerpc/kernel/head_64.S | 4 
 1 file changed, 4 insertions(+)

diff --git a/arch/powerpc/kernel/head_64.S b/arch/powerpc/kernel/head_64.S
index f17ae2083733..1cfb9be1ca9b 100644
--- a/arch/powerpc/kernel/head_64.S
+++ b/arch/powerpc/kernel/head_64.S
@@ -400,8 +400,12 @@ generic_secondary_common_init:
 #else
LOAD_REG_ADDR(r8, paca_ptrs)/* Load paca_ptrs pointe */
ld  r8,0(r8)/* Get base vaddr of array   */
+#if (NR_CPUS == 1) || defined(CONFIG_FORCE_NR_CPUS)
+   LOAD_REG_IMMEDIATE(r7, NR_CPUS)
+#else
LOAD_REG_ADDR(r7, nr_cpu_ids)   /* Load nr_cpu_ids address   */
lwz r7,0(r7)/* also the max paca allocated   */
+#endif
li  r5,0/* logical cpu id*/
 1:
sldir9,r5,3 /* get paca_ptrs[] index from cpu id */
-- 
2.35.1

[PATCH AUTOSEL 5.15 04/21] powerpc/hw_breakpoint: Avoid relying on caller synchronization

[Sasha Levin]

From: Marco Elver 

[ Upstream commit f95e5a3d59011eec1257d0e76de1e1f8969d426f ]

Internal data structures (cpu_bps, task_bps) of powerpc's hw_breakpoint
implementation have relied on nr_bp_mutex serializing access to them.

Before overhauling synchronization of kernel/events/hw_breakpoint.c,
introduce 2 spinlocks to synchronize cpu_bps and task_bps respectively,
thus avoiding reliance on callers synchronizing powerpc's hw_breakpoint.

Reported-by: Dmitry Vyukov 
Signed-off-by: Marco Elver 
Signed-off-by: Peter Zijlstra (Intel) 
Acked-by: Dmitry Vyukov 
Acked-by: Ian Rogers 
Link: https://lore.kernel.org/r/20220829124719.675715-10-el...@google.com
Signed-off-by: Sasha Levin 
---
 arch/powerpc/kernel/hw_breakpoint.c | 53 ++---
 1 file changed, 40 insertions(+), 13 deletions(-)

diff --git a/arch/powerpc/kernel/hw_breakpoint.c 
b/arch/powerpc/kernel/hw_breakpoint.c
index 91a3be14808b..4d99c6523b6d 100644
--- a/arch/powerpc/kernel/hw_breakpoint.c
+++ b/arch/powerpc/kernel/hw_breakpoint.c
@@ -15,6 +15,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 
@@ -129,7 +130,14 @@ struct breakpoint {
bool ptrace_bp;
 };
 
+/*
+ * While kernel/events/hw_breakpoint.c does its own synchronization, we cannot
+ * rely on it safely synchronizing internals here; however, we can rely on it
+ * not requesting more breakpoints than available.
+ */
+static DEFINE_SPINLOCK(cpu_bps_lock);
 static DEFINE_PER_CPU(struct breakpoint *, cpu_bps[HBP_NUM_MAX]);
+static DEFINE_SPINLOCK(task_bps_lock);
 static LIST_HEAD(task_bps);
 
 static struct breakpoint *alloc_breakpoint(struct perf_event *bp)
@@ -174,7 +182,9 @@ static int task_bps_add(struct perf_event *bp)
if (IS_ERR(tmp))
return PTR_ERR(tmp);
 
+   spin_lock(_bps_lock);
list_add(>list, _bps);
+   spin_unlock(_bps_lock);
return 0;
 }
 
@@ -182,6 +192,7 @@ static void task_bps_remove(struct perf_event *bp)
 {
struct list_head *pos, *q;
 
+   spin_lock(_bps_lock);
list_for_each_safe(pos, q, _bps) {
struct breakpoint *tmp = list_entry(pos, struct breakpoint, 
list);
 
@@ -191,6 +202,7 @@ static void task_bps_remove(struct perf_event *bp)
break;
}
}
+   spin_unlock(_bps_lock);
 }
 
 /*
@@ -200,12 +212,17 @@ static void task_bps_remove(struct perf_event *bp)
 static bool all_task_bps_check(struct perf_event *bp)
 {
struct breakpoint *tmp;
+   bool ret = false;
 
+   spin_lock(_bps_lock);
list_for_each_entry(tmp, _bps, list) {
-   if (!can_co_exist(tmp, bp))
-   return true;
+   if (!can_co_exist(tmp, bp)) {
+   ret = true;
+   break;
+   }
}
-   return false;
+   spin_unlock(_bps_lock);
+   return ret;
 }
 
 /*
@@ -215,13 +232,18 @@ static bool all_task_bps_check(struct perf_event *bp)
 static bool same_task_bps_check(struct perf_event *bp)
 {
struct breakpoint *tmp;
+   bool ret = false;
 
+   spin_lock(_bps_lock);
list_for_each_entry(tmp, _bps, list) {
if (tmp->bp->hw.target == bp->hw.target &&
-   !can_co_exist(tmp, bp))
-   return true;
+   !can_co_exist(tmp, bp)) {
+   ret = true;
+   break;
+   }
}
-   return false;
+   spin_unlock(_bps_lock);
+   return ret;
 }
 
 static int cpu_bps_add(struct perf_event *bp)
@@ -234,6 +256,7 @@ static int cpu_bps_add(struct perf_event *bp)
if (IS_ERR(tmp))
return PTR_ERR(tmp);
 
+   spin_lock(_bps_lock);
cpu_bp = per_cpu_ptr(cpu_bps, bp->cpu);
for (i = 0; i < nr_wp_slots(); i++) {
if (!cpu_bp[i]) {
@@ -241,6 +264,7 @@ static int cpu_bps_add(struct perf_event *bp)
break;
}
}
+   spin_unlock(_bps_lock);
return 0;
 }
 
@@ -249,6 +273,7 @@ static void cpu_bps_remove(struct perf_event *bp)
struct breakpoint **cpu_bp;
int i = 0;
 
+   spin_lock(_bps_lock);
cpu_bp = per_cpu_ptr(cpu_bps, bp->cpu);
for (i = 0; i < nr_wp_slots(); i++) {
if (!cpu_bp[i])
@@ -260,19 +285,25 @@ static void cpu_bps_remove(struct perf_event *bp)
break;
}
}
+   spin_unlock(_bps_lock);
 }
 
 static bool cpu_bps_check(int cpu, struct perf_event *bp)
 {
struct breakpoint **cpu_bp;
+   bool ret = false;
int i;
 
+   spin_lock(_bps_lock);
cpu_bp = per_cpu_ptr(cpu_bps, cpu);
for (i = 0; i < nr_wp_slots(); i++) {
-   if (cpu_bp[i] && !can_co_exist(cpu_bp[i], bp))
-   return true;
+   if (cpu_bp[i] && !can_co_exist(cpu_bp[i], bp)) {
+   ret = true;
+   break;
+ 

[PATCH AUTOSEL 5.19 12/29] powerpc/64: don't refer nr_cpu_ids in asm code when it's undefined

[Sasha Levin]

From: Yury Norov 

[ Upstream commit 546a073d628111e3338af689938407e77d5dc38f ]

generic_secondary_common_init() calls LOAD_REG_ADDR(r7, nr_cpu_ids)
conditionally on CONFIG_SMP. However, if 'NR_CPUS == 1', kernel doesn't
use the nr_cpu_ids, and in C code, it's just:
  #if NR_CPUS == 1
  #define nr_cpu_ids
  ...

This series makes declaration of nr_cpu_ids conditional on NR_CPUS == 1,
and that reveals the issue, because compiler can't link the
LOAD_REG_ADDR(r7, nr_cpu_ids) against nonexisting symbol.

Current code looks unsafe for those who build kernel with CONFIG_SMP=y and
NR_CPUS == 1. This is weird configuration, but not disallowed.

Fix the linker error by replacing LOAD_REG_ADDR() with LOAD_REG_IMMEDIATE()
conditionally on NR_CPUS == 1.

As the following patch adds CONFIG_FORCE_NR_CPUS option that has the
similar effect on nr_cpu_ids, make the generic_secondary_common_init()
conditional on it too.

Reported-by: Stephen Rothwell 
Signed-off-by: Yury Norov 
Signed-off-by: Sasha Levin 
---
 arch/powerpc/kernel/head_64.S | 4 
 1 file changed, 4 insertions(+)

diff --git a/arch/powerpc/kernel/head_64.S b/arch/powerpc/kernel/head_64.S
index d3eea633d11a..8408d3f7f61f 100644
--- a/arch/powerpc/kernel/head_64.S
+++ b/arch/powerpc/kernel/head_64.S
@@ -400,8 +400,12 @@ generic_secondary_common_init:
 #else
LOAD_REG_ADDR(r8, paca_ptrs)/* Load paca_ptrs pointe */
ld  r8,0(r8)/* Get base vaddr of array   */
+#if (NR_CPUS == 1) || defined(CONFIG_FORCE_NR_CPUS)
+   LOAD_REG_IMMEDIATE(r7, NR_CPUS)
+#else
LOAD_REG_ADDR(r7, nr_cpu_ids)   /* Load nr_cpu_ids address   */
lwz r7,0(r7)/* also the max paca allocated   */
+#endif
li  r5,0/* logical cpu id*/
 1:
sldir9,r5,3 /* get paca_ptrs[] index from cpu id */
-- 
2.35.1

[PATCH AUTOSEL 5.19 05/29] powerpc/hw_breakpoint: Avoid relying on caller synchronization

[Sasha Levin]

From: Marco Elver 

[ Upstream commit f95e5a3d59011eec1257d0e76de1e1f8969d426f ]

Internal data structures (cpu_bps, task_bps) of powerpc's hw_breakpoint
implementation have relied on nr_bp_mutex serializing access to them.

Before overhauling synchronization of kernel/events/hw_breakpoint.c,
introduce 2 spinlocks to synchronize cpu_bps and task_bps respectively,
thus avoiding reliance on callers synchronizing powerpc's hw_breakpoint.

Reported-by: Dmitry Vyukov 
Signed-off-by: Marco Elver 
Signed-off-by: Peter Zijlstra (Intel) 
Acked-by: Dmitry Vyukov 
Acked-by: Ian Rogers 
Link: https://lore.kernel.org/r/20220829124719.675715-10-el...@google.com
Signed-off-by: Sasha Levin 
---
 arch/powerpc/kernel/hw_breakpoint.c | 53 ++---
 1 file changed, 40 insertions(+), 13 deletions(-)

diff --git a/arch/powerpc/kernel/hw_breakpoint.c 
b/arch/powerpc/kernel/hw_breakpoint.c
index 2669f80b3a49..8db1a15d7acb 100644
--- a/arch/powerpc/kernel/hw_breakpoint.c
+++ b/arch/powerpc/kernel/hw_breakpoint.c
@@ -15,6 +15,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 
@@ -129,7 +130,14 @@ struct breakpoint {
bool ptrace_bp;
 };
 
+/*
+ * While kernel/events/hw_breakpoint.c does its own synchronization, we cannot
+ * rely on it safely synchronizing internals here; however, we can rely on it
+ * not requesting more breakpoints than available.
+ */
+static DEFINE_SPINLOCK(cpu_bps_lock);
 static DEFINE_PER_CPU(struct breakpoint *, cpu_bps[HBP_NUM_MAX]);
+static DEFINE_SPINLOCK(task_bps_lock);
 static LIST_HEAD(task_bps);
 
 static struct breakpoint *alloc_breakpoint(struct perf_event *bp)
@@ -174,7 +182,9 @@ static int task_bps_add(struct perf_event *bp)
if (IS_ERR(tmp))
return PTR_ERR(tmp);
 
+   spin_lock(_bps_lock);
list_add(>list, _bps);
+   spin_unlock(_bps_lock);
return 0;
 }
 
@@ -182,6 +192,7 @@ static void task_bps_remove(struct perf_event *bp)
 {
struct list_head *pos, *q;
 
+   spin_lock(_bps_lock);
list_for_each_safe(pos, q, _bps) {
struct breakpoint *tmp = list_entry(pos, struct breakpoint, 
list);
 
@@ -191,6 +202,7 @@ static void task_bps_remove(struct perf_event *bp)
break;
}
}
+   spin_unlock(_bps_lock);
 }
 
 /*
@@ -200,12 +212,17 @@ static void task_bps_remove(struct perf_event *bp)
 static bool all_task_bps_check(struct perf_event *bp)
 {
struct breakpoint *tmp;
+   bool ret = false;
 
+   spin_lock(_bps_lock);
list_for_each_entry(tmp, _bps, list) {
-   if (!can_co_exist(tmp, bp))
-   return true;
+   if (!can_co_exist(tmp, bp)) {
+   ret = true;
+   break;
+   }
}
-   return false;
+   spin_unlock(_bps_lock);
+   return ret;
 }
 
 /*
@@ -215,13 +232,18 @@ static bool all_task_bps_check(struct perf_event *bp)
 static bool same_task_bps_check(struct perf_event *bp)
 {
struct breakpoint *tmp;
+   bool ret = false;
 
+   spin_lock(_bps_lock);
list_for_each_entry(tmp, _bps, list) {
if (tmp->bp->hw.target == bp->hw.target &&
-   !can_co_exist(tmp, bp))
-   return true;
+   !can_co_exist(tmp, bp)) {
+   ret = true;
+   break;
+   }
}
-   return false;
+   spin_unlock(_bps_lock);
+   return ret;
 }
 
 static int cpu_bps_add(struct perf_event *bp)
@@ -234,6 +256,7 @@ static int cpu_bps_add(struct perf_event *bp)
if (IS_ERR(tmp))
return PTR_ERR(tmp);
 
+   spin_lock(_bps_lock);
cpu_bp = per_cpu_ptr(cpu_bps, bp->cpu);
for (i = 0; i < nr_wp_slots(); i++) {
if (!cpu_bp[i]) {
@@ -241,6 +264,7 @@ static int cpu_bps_add(struct perf_event *bp)
break;
}
}
+   spin_unlock(_bps_lock);
return 0;
 }
 
@@ -249,6 +273,7 @@ static void cpu_bps_remove(struct perf_event *bp)
struct breakpoint **cpu_bp;
int i = 0;
 
+   spin_lock(_bps_lock);
cpu_bp = per_cpu_ptr(cpu_bps, bp->cpu);
for (i = 0; i < nr_wp_slots(); i++) {
if (!cpu_bp[i])
@@ -260,19 +285,25 @@ static void cpu_bps_remove(struct perf_event *bp)
break;
}
}
+   spin_unlock(_bps_lock);
 }
 
 static bool cpu_bps_check(int cpu, struct perf_event *bp)
 {
struct breakpoint **cpu_bp;
+   bool ret = false;
int i;
 
+   spin_lock(_bps_lock);
cpu_bp = per_cpu_ptr(cpu_bps, cpu);
for (i = 0; i < nr_wp_slots(); i++) {
-   if (cpu_bp[i] && !can_co_exist(cpu_bp[i], bp))
-   return true;
+   if (cpu_bp[i] && !can_co_exist(cpu_bp[i], bp)) {
+   ret = true;
+   break;
+ 

[PATCH AUTOSEL 6.0 14/32] powerpc/64: don't refer nr_cpu_ids in asm code when it's undefined

[Sasha Levin]

From: Yury Norov 

[ Upstream commit 546a073d628111e3338af689938407e77d5dc38f ]

generic_secondary_common_init() calls LOAD_REG_ADDR(r7, nr_cpu_ids)
conditionally on CONFIG_SMP. However, if 'NR_CPUS == 1', kernel doesn't
use the nr_cpu_ids, and in C code, it's just:
  #if NR_CPUS == 1
  #define nr_cpu_ids
  ...

This series makes declaration of nr_cpu_ids conditional on NR_CPUS == 1,
and that reveals the issue, because compiler can't link the
LOAD_REG_ADDR(r7, nr_cpu_ids) against nonexisting symbol.

Current code looks unsafe for those who build kernel with CONFIG_SMP=y and
NR_CPUS == 1. This is weird configuration, but not disallowed.

Fix the linker error by replacing LOAD_REG_ADDR() with LOAD_REG_IMMEDIATE()
conditionally on NR_CPUS == 1.

As the following patch adds CONFIG_FORCE_NR_CPUS option that has the
similar effect on nr_cpu_ids, make the generic_secondary_common_init()
conditional on it too.

Reported-by: Stephen Rothwell 
Signed-off-by: Yury Norov 
Signed-off-by: Sasha Levin 
---
 arch/powerpc/kernel/head_64.S | 4 
 1 file changed, 4 insertions(+)

diff --git a/arch/powerpc/kernel/head_64.S b/arch/powerpc/kernel/head_64.S
index cf2c08902c05..d36939029701 100644
--- a/arch/powerpc/kernel/head_64.S
+++ b/arch/powerpc/kernel/head_64.S
@@ -400,8 +400,12 @@ generic_secondary_common_init:
 #else
LOAD_REG_ADDR(r8, paca_ptrs)/* Load paca_ptrs pointe */
ld  r8,0(r8)/* Get base vaddr of array   */
+#if (NR_CPUS == 1) || defined(CONFIG_FORCE_NR_CPUS)
+   LOAD_REG_IMMEDIATE(r7, NR_CPUS)
+#else
LOAD_REG_ADDR(r7, nr_cpu_ids)   /* Load nr_cpu_ids address   */
lwz r7,0(r7)/* also the max paca allocated   */
+#endif
li  r5,0/* logical cpu id*/
 1:
sldir9,r5,3 /* get paca_ptrs[] index from cpu id */
-- 
2.35.1

[PATCH AUTOSEL 6.0 05/32] powerpc/hw_breakpoint: Avoid relying on caller synchronization

[Sasha Levin]

From: Marco Elver 

[ Upstream commit f95e5a3d59011eec1257d0e76de1e1f8969d426f ]

Internal data structures (cpu_bps, task_bps) of powerpc's hw_breakpoint
implementation have relied on nr_bp_mutex serializing access to them.

Before overhauling synchronization of kernel/events/hw_breakpoint.c,
introduce 2 spinlocks to synchronize cpu_bps and task_bps respectively,
thus avoiding reliance on callers synchronizing powerpc's hw_breakpoint.

Reported-by: Dmitry Vyukov 
Signed-off-by: Marco Elver 
Signed-off-by: Peter Zijlstra (Intel) 
Acked-by: Dmitry Vyukov 
Acked-by: Ian Rogers 
Link: https://lore.kernel.org/r/20220829124719.675715-10-el...@google.com
Signed-off-by: Sasha Levin 
---
 arch/powerpc/kernel/hw_breakpoint.c | 53 ++---
 1 file changed, 40 insertions(+), 13 deletions(-)

diff --git a/arch/powerpc/kernel/hw_breakpoint.c 
b/arch/powerpc/kernel/hw_breakpoint.c
index 2669f80b3a49..8db1a15d7acb 100644
--- a/arch/powerpc/kernel/hw_breakpoint.c
+++ b/arch/powerpc/kernel/hw_breakpoint.c
@@ -15,6 +15,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 
@@ -129,7 +130,14 @@ struct breakpoint {
bool ptrace_bp;
 };
 
+/*
+ * While kernel/events/hw_breakpoint.c does its own synchronization, we cannot
+ * rely on it safely synchronizing internals here; however, we can rely on it
+ * not requesting more breakpoints than available.
+ */
+static DEFINE_SPINLOCK(cpu_bps_lock);
 static DEFINE_PER_CPU(struct breakpoint *, cpu_bps[HBP_NUM_MAX]);
+static DEFINE_SPINLOCK(task_bps_lock);
 static LIST_HEAD(task_bps);
 
 static struct breakpoint *alloc_breakpoint(struct perf_event *bp)
@@ -174,7 +182,9 @@ static int task_bps_add(struct perf_event *bp)
if (IS_ERR(tmp))
return PTR_ERR(tmp);
 
+   spin_lock(_bps_lock);
list_add(>list, _bps);
+   spin_unlock(_bps_lock);
return 0;
 }
 
@@ -182,6 +192,7 @@ static void task_bps_remove(struct perf_event *bp)
 {
struct list_head *pos, *q;
 
+   spin_lock(_bps_lock);
list_for_each_safe(pos, q, _bps) {
struct breakpoint *tmp = list_entry(pos, struct breakpoint, 
list);
 
@@ -191,6 +202,7 @@ static void task_bps_remove(struct perf_event *bp)
break;
}
}
+   spin_unlock(_bps_lock);
 }
 
 /*
@@ -200,12 +212,17 @@ static void task_bps_remove(struct perf_event *bp)
 static bool all_task_bps_check(struct perf_event *bp)
 {
struct breakpoint *tmp;
+   bool ret = false;
 
+   spin_lock(_bps_lock);
list_for_each_entry(tmp, _bps, list) {
-   if (!can_co_exist(tmp, bp))
-   return true;
+   if (!can_co_exist(tmp, bp)) {
+   ret = true;
+   break;
+   }
}
-   return false;
+   spin_unlock(_bps_lock);
+   return ret;
 }
 
 /*
@@ -215,13 +232,18 @@ static bool all_task_bps_check(struct perf_event *bp)
 static bool same_task_bps_check(struct perf_event *bp)
 {
struct breakpoint *tmp;
+   bool ret = false;
 
+   spin_lock(_bps_lock);
list_for_each_entry(tmp, _bps, list) {
if (tmp->bp->hw.target == bp->hw.target &&
-   !can_co_exist(tmp, bp))
-   return true;
+   !can_co_exist(tmp, bp)) {
+   ret = true;
+   break;
+   }
}
-   return false;
+   spin_unlock(_bps_lock);
+   return ret;
 }
 
 static int cpu_bps_add(struct perf_event *bp)
@@ -234,6 +256,7 @@ static int cpu_bps_add(struct perf_event *bp)
if (IS_ERR(tmp))
return PTR_ERR(tmp);
 
+   spin_lock(_bps_lock);
cpu_bp = per_cpu_ptr(cpu_bps, bp->cpu);
for (i = 0; i < nr_wp_slots(); i++) {
if (!cpu_bp[i]) {
@@ -241,6 +264,7 @@ static int cpu_bps_add(struct perf_event *bp)
break;
}
}
+   spin_unlock(_bps_lock);
return 0;
 }
 
@@ -249,6 +273,7 @@ static void cpu_bps_remove(struct perf_event *bp)
struct breakpoint **cpu_bp;
int i = 0;
 
+   spin_lock(_bps_lock);
cpu_bp = per_cpu_ptr(cpu_bps, bp->cpu);
for (i = 0; i < nr_wp_slots(); i++) {
if (!cpu_bp[i])
@@ -260,19 +285,25 @@ static void cpu_bps_remove(struct perf_event *bp)
break;
}
}
+   spin_unlock(_bps_lock);
 }
 
 static bool cpu_bps_check(int cpu, struct perf_event *bp)
 {
struct breakpoint **cpu_bp;
+   bool ret = false;
int i;
 
+   spin_lock(_bps_lock);
cpu_bp = per_cpu_ptr(cpu_bps, cpu);
for (i = 0; i < nr_wp_slots(); i++) {
-   if (cpu_bp[i] && !can_co_exist(cpu_bp[i], bp))
-   return true;
+   if (cpu_bp[i] && !can_co_exist(cpu_bp[i], bp)) {
+   ret = true;
+   break;
+ 

Re: [PATCH v6 0/7] treewide cleanup of random integer usage

[liulongfang]

On 2022/10/11 7:06, Jason A. Donenfeld Wrote:
> Changes v5->v6:
> - Added a few missing conversions that weren't in my older tree, so now
>   this should be ready to go, as well as a couple nits people had from
>   v5. Barring something large and unforeseen, this is the "final
>   version", as this is ready to ship. Thanks to everyone who reviewed
>   this.
> 
> Hi folks,
> 
> This is a five part treewide cleanup of random integer handling. The
> rules for random integers are:
> 
> - If you want a secure or an insecure random u64, use get_random_u64().
> - If you want a secure or an insecure random u32, use get_random_u32().
>   * The old function prandom_u32() has been deprecated for a while now
> and is just a wrapper around get_random_u32(). Same for
> get_random_int().
> - If you want a secure or an insecure random u16, use get_random_u16().
> - If you want a secure or an insecure random u8, use get_random_u8().
> - If you want secure or insecure random bytes, use get_random_bytes().
>   * The old function prandom_bytes() has been deprecated for a while now
> and has long been a wrapper around get_random_bytes().
> - If you want a non-uniform random u32, u16, or u8 bounded by a certain
>   open interval maximum, use prandom_u32_max().
>   * I say "non-uniform", because it doesn't do any rejection sampling or
> divisions. Hence, it stays within the prandom_* namespace.
> 
> These rules ought to be applied uniformly, so that we can clean up the
> deprecated functions, and earn the benefits of using the modern
> functions. In particular, in addition to the boring substitutions, this
> patchset accomplishes a few nice effects:
> 
> - By using prandom_u32_max() with an upper-bound that the compiler can
>   prove at compile-time is ≤65536 or ≤256, internally get_random_u16()
>   or get_random_u8() is used, which wastes fewer batched random bytes,
>   and hence has higher throughput.
> 
> - By using prandom_u32_max() instead of %, when the upper-bound is not a
>   constant, division is still avoided, because prandom_u32_max() uses
>   a faster multiplication-based trick instead.
> 
> - By using get_random_u16() or get_random_u8() in cases where the return
>   value is intended to indeed be a u16 or a u8, we waste fewer batched
>   random bytes, and hence have higher throughput.
> 
> So, based on those rules and benefits from following them, this patchset
> breaks down into the following five steps:
> 
> 1) Replace `prandom_u32() % max` and variants thereof with
>prandom_u32_max(max).
> 
>* Part 1 is done with Coccinelle. Part 2 is done by hand.
> 
> 2) Replace `(type)get_random_u32()` and variants thereof with
>get_random_u16() or get_random_u8(). I took the pains to actually
>look and see what every lvalue type was across the entire tree.
> 
>* Part 1 is done with Coccinelle. Part 2 is done by hand.
> 
> 3) Replace remaining deprecated uses of prandom_u32() and
>get_random_int() with get_random_u32(). 
> 
>* A boring search and replace operation.
> 
> 4) Replace remaining deprecated uses of prandom_bytes() with
>get_random_bytes().
> 
>* A boring search and replace operation.
> 
> 5) Remove the deprecated and now-unused prandom_u32() and
>prandom_bytes() inline wrapper functions.
> 
>* Just deleting code and updating comments.
> 
> I'll be sending this toward the end of the 6.1 merge window via the
> random.git tree.
> 
> Please take a look! The number of lines touched is quite small, so this
> should be reviewable, and as much as is possible has been pushed into
> Coccinelle scripts.
> 
> Thanks,
> Jason
> 
> Cc: Andreas Noever 
> Cc: Andrew Morton 
> Cc: Andy Shevchenko 
> Cc: Borislav Petkov 
> Cc: Catalin Marinas 
> Cc: Christoph Böhmwalder 
> Cc: Christoph Hellwig 
> Cc: Christophe Leroy 
> Cc: Daniel Borkmann 
> Cc: Dave Airlie 
> Cc: Dave Hansen 
> Cc: David S. Miller 
> Cc: Eric Dumazet 
> Cc: Florian Westphal 
> Cc: Greg Kroah-Hartman ,
> Cc: H. Peter Anvin 
> Cc: Heiko Carstens 
> Cc: Helge Deller 
> Cc: Herbert Xu 
> Cc: Huacai Chen 
> Cc: Hugh Dickins 
> Cc: Jakub Kicinski 
> Cc: James E.J. Bottomley 
> Cc: Jan Kara 
> Cc: Jason Gunthorpe 
> Cc: Jens Axboe 
> Cc: Johannes Berg 
> Cc: Jonathan Corbet 
> Cc: Jozsef Kadlecsik 
> Cc: KP Singh 
> Cc: Kees Cook 
> Cc: Marco Elver 
> Cc: Mauro Carvalho Chehab 
> Cc: Michael Ellerman 
> Cc: Pablo Neira Ayuso 
> Cc: Paolo Abeni 
> Cc: Peter Zijlstra 
> Cc: Richard Weinberger 
> Cc: Russell King 
> Cc: Theodore Ts'o 
> Cc: Thomas Bogendoerfer 
> Cc: Thomas Gleixner 
> Cc: Thomas Graf 
> Cc: Ulf Hansson 
> Cc: Vignesh Raghavendra 
> Cc: WANG Xuerui 
> Cc: Will Deacon 
> Cc: Yury Norov 
> Cc: dri-de...@lists.freedesktop.org
> Cc: kasan-...@googlegroups.com
> Cc: kernel-janit...@vger.kernel.org
> Cc: linux-arm-ker...@lists.infradead.org
> Cc: linux-bl...@vger.kernel.org
> Cc: linux-cry...@vger.kernel.org
> Cc: linux-...@vger.kernel.org
> Cc: linux-fsde...@vger.kernel.org
> Cc: 

[PATCH net-next v7 10/10] arm64: dts: layerscape: Add nodes for QSGMII PCSs

[Sean Anderson]

Now that we actually read registers from QSGMII PCSs, it's important
that we have the correct address (instead of hoping that we're the MAC
with all the QSGMII PCSs on its bus). This adds nodes for the QSGMII
PCSs.  The exact mapping of QSGMII to MACs depends on the SoC.

Since the first QSGMII PCSs share an address with the SGMII and XFI
PCSs, we only add new nodes for PCSs 2-4. This avoids address conflicts
on the bus.

Signed-off-by: Sean Anderson 
---

(no changes since v3)

Changes in v3:
- Split this patch off from the previous one

Changes in v2:
- New

 .../boot/dts/freescale/fsl-ls1043-post.dtsi   | 24 ++
 .../boot/dts/freescale/fsl-ls1046-post.dtsi   | 25 +++
 2 files changed, 49 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043-post.dtsi 
b/arch/arm64/boot/dts/freescale/fsl-ls1043-post.dtsi
index d237162a8744..5c4d7eef8b61 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043-post.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043-post.dtsi
@@ -24,9 +24,12 @@  {
 
/* these aliases provide the FMan ports mapping */
enet0: ethernet@e {
+   pcs-handle-names = "qsgmii";
};
 
enet1: ethernet@e2000 {
+   pcsphy-handle = <>, <_pcs1>;
+   pcs-handle-names = "sgmii", "qsgmii";
};
 
enet2: ethernet@e4000 {
@@ -36,11 +39,32 @@ enet3: ethernet@e6000 {
};
 
enet4: ethernet@e8000 {
+   pcsphy-handle = <>, <_pcs2>;
+   pcs-handle-names = "sgmii", "qsgmii";
};
 
enet5: ethernet@ea000 {
+   pcsphy-handle = <>, <_pcs3>;
+   pcs-handle-names = "sgmii", "qsgmii";
};
 
enet6: ethernet@f {
};
+
+   mdio@e1000 {
+   qsgmiib_pcs1: ethernet-pcs@1 {
+   compatible = "fsl,lynx-pcs";
+   reg = <0x1>;
+   };
+
+   qsgmiib_pcs2: ethernet-pcs@2 {
+   compatible = "fsl,lynx-pcs";
+   reg = <0x2>;
+   };
+
+   qsgmiib_pcs3: ethernet-pcs@3 {
+   compatible = "fsl,lynx-pcs";
+   reg = <0x3>;
+   };
+   };
 };
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046-post.dtsi 
b/arch/arm64/boot/dts/freescale/fsl-ls1046-post.dtsi
index d6caaea57d90..4e3345093943 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046-post.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046-post.dtsi
@@ -23,6 +23,8 @@  {
  {
/* these aliases provide the FMan ports mapping */
enet0: ethernet@e {
+   pcsphy-handle = <_pcs3>;
+   pcs-handle-names = "qsgmii";
};
 
enet1: ethernet@e2000 {
@@ -35,14 +37,37 @@ enet3: ethernet@e6000 {
};
 
enet4: ethernet@e8000 {
+   pcsphy-handle = <>, <_pcs1>;
+   pcs-handle-names = "sgmii", "qsgmii";
};
 
enet5: ethernet@ea000 {
+   pcsphy-handle = <>, <>;
+   pcs-handle-names = "sgmii", "qsgmii";
};
 
enet6: ethernet@f {
};
 
enet7: ethernet@f2000 {
+   pcsphy-handle = <>, <_pcs2>, <>;
+   pcs-handle-names = "sgmii", "qsgmii", "xfi";
+   };
+
+   mdio@eb000 {
+   qsgmiib_pcs1: ethernet-pcs@1 {
+   compatible = "fsl,lynx-pcs";
+   reg = <0x1>;
+   };
+
+   qsgmiib_pcs2: ethernet-pcs@2 {
+   compatible = "fsl,lynx-pcs";
+   reg = <0x2>;
+   };
+
+   qsgmiib_pcs3: ethernet-pcs@3 {
+   compatible = "fsl,lynx-pcs";
+   reg = <0x3>;
+   };
};
 };
-- 
2.35.1.1320.gc452695387.dirty

[PATCH net-next v7 09/10] powerpc: dts: qoriq: Add nodes for QSGMII PCSs

[Sean Anderson]

Now that we actually read registers from QSGMII PCSs, it's important
that we have the correct address (instead of hoping that we're the MAC
with all the QSGMII PCSs on its bus). This adds nodes for the QSGMII
PCSs. They have the same addresses on all SoCs (e.g. if QSGMIIA is
present it's used for MACs 1 through 4).

Since the first QSGMII PCSs share an address with the SGMII and XFI
PCSs, we only add new nodes for PCSs 2-4. This avoids address conflicts
on the bus.

Signed-off-by: Sean Anderson 
---

(no changes since v4)

Changes in v4:
- Add XFI PCS for t208x MAC1/MAC2

Changes in v3:
- Add compatibles for QSGMII PCSs
- Split arm and powerpcs dts updates

Changes in v2:
- New

 .../boot/dts/fsl/qoriq-fman3-0-10g-0-best-effort.dtsi  |  3 ++-
 arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-0.dtsi | 10 +-
 .../boot/dts/fsl/qoriq-fman3-0-10g-1-best-effort.dtsi  | 10 +-
 arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-1.dtsi | 10 +-
 arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-2.dtsi |  3 ++-
 arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-3.dtsi |  3 ++-
 arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-0.dtsi  |  3 ++-
 arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-1.dtsi  | 10 +-
 arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-2.dtsi  | 10 +-
 arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-3.dtsi  | 10 +-
 arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-4.dtsi  |  3 ++-
 arch/powerpc/boot/dts/fsl/qoriq-fman3-0-1g-5.dtsi  | 10 +-
 arch/powerpc/boot/dts/fsl/qoriq-fman3-1-10g-0.dtsi | 10 +-
 arch/powerpc/boot/dts/fsl/qoriq-fman3-1-10g-1.dtsi | 10 +-
 arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-0.dtsi  |  3 ++-
 arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-1.dtsi  | 10 +-
 arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-2.dtsi  | 10 +-
 arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-3.dtsi  | 10 +-
 arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-4.dtsi  |  3 ++-
 arch/powerpc/boot/dts/fsl/qoriq-fman3-1-1g-5.dtsi  | 10 +-
 20 files changed, 131 insertions(+), 20 deletions(-)

diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-0-best-effort.dtsi 
b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-0-best-effort.dtsi
index baa0c503e741..7e70977f282a 100644
--- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-0-best-effort.dtsi
+++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-0-best-effort.dtsi
@@ -55,7 +55,8 @@ ethernet@e {
reg = <0xe 0x1000>;
fsl,fman-ports = <_rx_0x08 _tx_0x28>;
ptp-timer = <_timer0>;
-   pcsphy-handle = <>;
+   pcsphy-handle = <>, <>;
+   pcs-handle-names = "sgmii", "qsgmii";
};
 
mdio@e1000 {
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-0.dtsi 
b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-0.dtsi
index 93095600e808..5f89f7c1761f 100644
--- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-0.dtsi
+++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-0.dtsi
@@ -52,7 +52,15 @@ ethernet@f {
compatible = "fsl,fman-memac";
reg = <0xf 0x1000>;
fsl,fman-ports = <_rx_0x10 _tx_0x30>;
-   pcsphy-handle = <>;
+   pcsphy-handle = <>, <_pcs2>, <>;
+   pcs-handle-names = "sgmii", "qsgmii", "xfi";
+   };
+
+   mdio@e9000 {
+   qsgmiib_pcs2: ethernet-pcs@2 {
+   compatible = "fsl,lynx-pcs";
+   reg = <2>;
+   };
};
 
mdio@f1000 {
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-1-best-effort.dtsi 
b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-1-best-effort.dtsi
index ff4bd38f0645..71eb75e82c2e 100644
--- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-1-best-effort.dtsi
+++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-1-best-effort.dtsi
@@ -55,7 +55,15 @@ ethernet@e2000 {
reg = <0xe2000 0x1000>;
fsl,fman-ports = <_rx_0x09 _tx_0x29>;
ptp-timer = <_timer0>;
-   pcsphy-handle = <>;
+   pcsphy-handle = <>, <_pcs1>;
+   pcs-handle-names = "sgmii", "qsgmii";
+   };
+
+   mdio@e1000 {
+   qsgmiia_pcs1: ethernet-pcs@1 {
+   compatible = "fsl,lynx-pcs";
+   reg = <1>;
+   };
};
 
mdio@e3000 {
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-1.dtsi 
b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-1.dtsi
index 1fa38ed6f59e..fb7032ddb7fc 100644
--- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-1.dtsi
+++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-1.dtsi
@@ -52,7 +52,15 @@ ethernet@f2000 {
compatible = "fsl,fman-memac";
reg = <0xf2000 0x1000>;
fsl,fman-ports = <_rx_0x11 _tx_0x31>;
-   pcsphy-handle = <>;
+   pcsphy-handle = <>, <_pcs3>, <>;
+   

[PATCH net-next v7 08/10] powerpc: dts: t208x: Mark MAC1 and MAC2 as 10G

[Sean Anderson]

On the T208X SoCs, MAC1 and MAC2 support XGMII. Add some new MAC dtsi
fragments, and mark the QMAN ports as 10G.

Fixes: da414bb923d9 ("powerpc/mpc85xx: Add FSL QorIQ DPAA FMan support to the 
SoC device tree(s)")
Signed-off-by: Sean Anderson 
---

(no changes since v4)

Changes in v4:
- New

 .../boot/dts/fsl/qoriq-fman3-0-10g-2.dtsi | 44 +++
 .../boot/dts/fsl/qoriq-fman3-0-10g-3.dtsi | 44 +++
 arch/powerpc/boot/dts/fsl/t2081si-post.dtsi   |  4 +-
 3 files changed, 90 insertions(+), 2 deletions(-)
 create mode 100644 arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-2.dtsi
 create mode 100644 arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-3.dtsi

diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-2.dtsi 
b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-2.dtsi
new file mode 100644
index ..437dab3fc017
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-2.dtsi
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-or-later
+/*
+ * QorIQ FMan v3 10g port #2 device tree stub [ controller @ offset 0x40 ]
+ *
+ * Copyright 2022 Sean Anderson 
+ * Copyright 2012 - 2015 Freescale Semiconductor Inc.
+ */
+
+fman@40 {
+   fman0_rx_0x08: port@88000 {
+   cell-index = <0x8>;
+   compatible = "fsl,fman-v3-port-rx";
+   reg = <0x88000 0x1000>;
+   fsl,fman-10g-port;
+   };
+
+   fman0_tx_0x28: port@a8000 {
+   cell-index = <0x28>;
+   compatible = "fsl,fman-v3-port-tx";
+   reg = <0xa8000 0x1000>;
+   fsl,fman-10g-port;
+   };
+
+   ethernet@e {
+   cell-index = <0>;
+   compatible = "fsl,fman-memac";
+   reg = <0xe 0x1000>;
+   fsl,fman-ports = <_rx_0x08 _tx_0x28>;
+   ptp-timer = <_timer0>;
+   pcsphy-handle = <>;
+   };
+
+   mdio@e1000 {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
+   reg = <0xe1000 0x1000>;
+   fsl,erratum-a011043; /* must ignore read errors */
+
+   pcsphy0: ethernet-phy@0 {
+   reg = <0x0>;
+   };
+   };
+};
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-3.dtsi 
b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-3.dtsi
new file mode 100644
index ..ad116b17850a
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-3.dtsi
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-or-later
+/*
+ * QorIQ FMan v3 10g port #3 device tree stub [ controller @ offset 0x40 ]
+ *
+ * Copyright 2022 Sean Anderson 
+ * Copyright 2012 - 2015 Freescale Semiconductor Inc.
+ */
+
+fman@40 {
+   fman0_rx_0x09: port@89000 {
+   cell-index = <0x9>;
+   compatible = "fsl,fman-v3-port-rx";
+   reg = <0x89000 0x1000>;
+   fsl,fman-10g-port;
+   };
+
+   fman0_tx_0x29: port@a9000 {
+   cell-index = <0x29>;
+   compatible = "fsl,fman-v3-port-tx";
+   reg = <0xa9000 0x1000>;
+   fsl,fman-10g-port;
+   };
+
+   ethernet@e2000 {
+   cell-index = <1>;
+   compatible = "fsl,fman-memac";
+   reg = <0xe2000 0x1000>;
+   fsl,fman-ports = <_rx_0x09 _tx_0x29>;
+   ptp-timer = <_timer0>;
+   pcsphy-handle = <>;
+   };
+
+   mdio@e3000 {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
+   reg = <0xe3000 0x1000>;
+   fsl,erratum-a011043; /* must ignore read errors */
+
+   pcsphy1: ethernet-phy@0 {
+   reg = <0x0>;
+   };
+   };
+};
diff --git a/arch/powerpc/boot/dts/fsl/t2081si-post.dtsi 
b/arch/powerpc/boot/dts/fsl/t2081si-post.dtsi
index ecbb447920bc..74e17e134387 100644
--- a/arch/powerpc/boot/dts/fsl/t2081si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/t2081si-post.dtsi
@@ -609,8 +609,8 @@ usb1: usb@211000 {
 /include/ "qoriq-bman1.dtsi"
 
 /include/ "qoriq-fman3-0.dtsi"
-/include/ "qoriq-fman3-0-1g-0.dtsi"
-/include/ "qoriq-fman3-0-1g-1.dtsi"
+/include/ "qoriq-fman3-0-10g-2.dtsi"
+/include/ "qoriq-fman3-0-10g-3.dtsi"
 /include/ "qoriq-fman3-0-1g-2.dtsi"
 /include/ "qoriq-fman3-0-1g-3.dtsi"
 /include/ "qoriq-fman3-0-1g-4.dtsi"
-- 
2.35.1.1320.gc452695387.dirty

[PATCH net-next v7 07/10] net: dpaa: Convert to phylink

[Sean Anderson]

This converts DPAA to phylink. All macs are converted. This should work
with no device tree modifications (including those made in this series),
except for QSGMII (as noted previously).

The mEMAC configuration is one of the tricker areas. I have tried to
capture all the restrictions across the various models. Most of the time,
we assume that if the serdes supports a mode or the phy-interface-mode
specifies it, then we support it. The only place we can't do this is
(RG)MII, since there's no serdes. In that case, we rely on a (new)
devicetree property. There are also several cases where half-duplex is
broken. Unfortunately, only a single compatible is used for the MAC, so we
have to use the board compatible instead.

The 10GEC conversion is very straightforward, since it only supports XAUI.
There is generally nothing to configure.

The dTSEC conversion is broadly similar to mEMAC, but is simpler because we
don't support configuring the SerDes (though this can be easily added) and
we don't have multiple PCSs. From what I can tell, there's nothing
different in the driver or documentation between SGMII and 1000BASE-X
except for the advertising. Similarly, I couldn't find anything about
2500BASE-X. In both cases, I treat them like SGMII. These modes aren't used
by any in-tree boards. Similarly, despite being mentioned in the driver, I
couldn't find any documented SoCs which supported QSGMII.  I have left it
unimplemented for now.

Signed-off-by: Sean Anderson 
---
This has been tested on an LS1046ARDB.

With managed=phy, I was unable to get the interfaces to come up at all,
hence the default to in-band.

10GEC and dTSEC have not been tested at all. I would greatly appreciate if
someone could try them out.

Changes in v7:
- Fix 81-character line
- Simplify memac_validate with phylink_validate_mask_caps

Changes in v6:
- Fix uninitialized variable in dtsec_mac_config

Changes in v3:
- Remove _return label from memac_initialization in favor of returning
  directly
- Fix grabbing the default PCS not checking for -ENODATA from
  of_property_match_string
- Set DTSEC_ECNTRL_R100M in dtsec_link_up instead of dtsec_mac_config
- Remove rmii/mii properties

Changes in v2:
- Remove unused variable slow_10g_if
- Restrict valid link modes based on the phy interface. This is easier
  to set up, and mostly captures what I intended to do the first time.
  We now have a custom validate which restricts half-duplex for some SoCs
  for RGMII, but generally just uses the default phylink validate.
- Configure the SerDes in enable/disable
- Properly implement all ethtool ops and ioctls. These were mostly
  stubbed out just enough to compile last time.
- Convert 10GEC and dTSEC as well

 drivers/net/ethernet/freescale/dpaa/Kconfig   |   4 +-
 .../net/ethernet/freescale/dpaa/dpaa_eth.c|  89 +--
 .../ethernet/freescale/dpaa/dpaa_ethtool.c|  90 +--
 drivers/net/ethernet/freescale/fman/Kconfig   |   1 -
 .../net/ethernet/freescale/fman/fman_dtsec.c  | 460 +++---
 .../net/ethernet/freescale/fman/fman_mac.h|  10 -
 .../net/ethernet/freescale/fman/fman_memac.c  | 559 +-
 .../net/ethernet/freescale/fman/fman_tgec.c   | 131 ++--
 drivers/net/ethernet/freescale/fman/mac.c | 168 +-
 drivers/net/ethernet/freescale/fman/mac.h |  23 +-
 10 files changed, 619 insertions(+), 916 deletions(-)

diff --git a/drivers/net/ethernet/freescale/dpaa/Kconfig 
b/drivers/net/ethernet/freescale/dpaa/Kconfig
index 0e1439fd00bd..2b560661c82a 100644
--- a/drivers/net/ethernet/freescale/dpaa/Kconfig
+++ b/drivers/net/ethernet/freescale/dpaa/Kconfig
@@ -2,8 +2,8 @@
 menuconfig FSL_DPAA_ETH
tristate "DPAA Ethernet"
depends on FSL_DPAA && FSL_FMAN
-   select PHYLIB
-   select FIXED_PHY
+   select PHYLINK
+   select PCS_LYNX
help
  Data Path Acceleration Architecture Ethernet driver,
  supporting the Freescale QorIQ chips.
diff --git a/drivers/net/ethernet/freescale/dpaa/dpaa_eth.c 
b/drivers/net/ethernet/freescale/dpaa/dpaa_eth.c
index 31cfa121333d..021ba999d86d 100644
--- a/drivers/net/ethernet/freescale/dpaa/dpaa_eth.c
+++ b/drivers/net/ethernet/freescale/dpaa/dpaa_eth.c
@@ -264,8 +264,19 @@ static int dpaa_netdev_init(struct net_device *net_dev,
net_dev->needed_headroom = priv->tx_headroom;
net_dev->watchdog_timeo = msecs_to_jiffies(tx_timeout);
 
-   mac_dev->net_dev = net_dev;
+   /* The rest of the config is filled in by the mac device already */
+   mac_dev->phylink_config.dev = _dev->dev;
+   mac_dev->phylink_config.type = PHYLINK_NETDEV;
mac_dev->update_speed = dpaa_eth_cgr_set_speed;
+   mac_dev->phylink = phylink_create(_dev->phylink_config,
+ dev_fwnode(mac_dev->dev),
+ mac_dev->phy_if,
+ mac_dev->phylink_ops);
+   if (IS_ERR(mac_dev->phylink)) {
+   err = 

[PATCH net-next v7 06/10] net: fman: memac: Use lynx pcs driver

[Sean Anderson]

Although not stated in the datasheet, as far as I can tell PCS for mEMACs
is a "Lynx." By reusing the existing driver, we can remove the PCS
management code from the memac driver. This requires calling some PCS
functions manually which phylink would usually do for us, but we will let
it do that soon.

One problem is that we don't actually have a PCS for QSGMII. We pretend
that each mEMAC's MDIO bus has four QSGMII PCSs, but this is not the case.
Only the "base" mEMAC's MDIO bus has the four QSGMII PCSs. This is not an
issue yet, because we never get the PCS state. However, it will be once the
conversion to phylink is complete, since the links will appear to never
come up. To get around this, we allow specifying multiple PCSs in pcsphy.
This breaks backwards compatibility with old device trees, but only for
QSGMII. IMO this is the only reasonable way to figure out what the actual
QSGMII PCS is.

Additionally, we now also support a separate XFI PCS. This can allow the
SerDes driver to set different addresses for the SGMII and XFI PCSs so they
can be accessed at the same time.

Signed-off-by: Sean Anderson 
---

Changes in v7:
- Fix oops if memac_pcs_create returned -EPROBE_DEFER
- Fix using pcs-names instead of pcs-handle-names
- Fix not checking for -ENODATA when looking for sgmii pcs

Changes in v6:
- Fix 81-character line

Changes in v3:
- Put the PCS mdiodev only after we are done with it (since the PCS
  does not perform a get itself).

Changes in v2:
- Move PCS_LYNX dependency to fman Kconfig

 drivers/net/ethernet/freescale/fman/Kconfig   |   3 +
 .../net/ethernet/freescale/fman/fman_memac.c  | 258 +++---
 2 files changed, 105 insertions(+), 156 deletions(-)

diff --git a/drivers/net/ethernet/freescale/fman/Kconfig 
b/drivers/net/ethernet/freescale/fman/Kconfig
index 48bf8088795d..8f5637db41dd 100644
--- a/drivers/net/ethernet/freescale/fman/Kconfig
+++ b/drivers/net/ethernet/freescale/fman/Kconfig
@@ -4,6 +4,9 @@ config FSL_FMAN
depends on FSL_SOC || ARCH_LAYERSCAPE || COMPILE_TEST
select GENERIC_ALLOCATOR
select PHYLIB
+   select PHYLINK
+   select PCS
+   select PCS_LYNX
select CRC32
default n
help
diff --git a/drivers/net/ethernet/freescale/fman/fman_memac.c 
b/drivers/net/ethernet/freescale/fman/fman_memac.c
index 56a29f505590..43584946cae2 100644
--- a/drivers/net/ethernet/freescale/fman/fman_memac.c
+++ b/drivers/net/ethernet/freescale/fman/fman_memac.c
@@ -11,43 +11,12 @@
 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
 #include 
 
-/* PCS registers */
-#define MDIO_SGMII_CR  0x00
-#define MDIO_SGMII_DEV_ABIL_SGMII  0x04
-#define MDIO_SGMII_LINK_TMR_L  0x12
-#define MDIO_SGMII_LINK_TMR_H  0x13
-#define MDIO_SGMII_IF_MODE 0x14
-
-/* SGMII Control defines */
-#define SGMII_CR_AN_EN 0x1000
-#define SGMII_CR_RESTART_AN0x0200
-#define SGMII_CR_FD0x0100
-#define SGMII_CR_SPEED_SEL1_1G 0x0040
-#define SGMII_CR_DEF_VAL   (SGMII_CR_AN_EN | SGMII_CR_FD | \
-SGMII_CR_SPEED_SEL1_1G)
-
-/* SGMII Device Ability for SGMII defines */
-#define MDIO_SGMII_DEV_ABIL_SGMII_MODE 0x4001
-#define MDIO_SGMII_DEV_ABIL_BASEX_MODE 0x01A0
-
-/* Link timer define */
-#define LINK_TMR_L 0xa120
-#define LINK_TMR_H 0x0007
-#define LINK_TMR_L_BASEX   0xaf08
-#define LINK_TMR_H_BASEX   0x002f
-
-/* SGMII IF Mode defines */
-#define IF_MODE_USE_SGMII_AN   0x0002
-#define IF_MODE_SGMII_EN   0x0001
-#define IF_MODE_SGMII_SPEED_100M   0x0004
-#define IF_MODE_SGMII_SPEED_1G 0x0008
-#define IF_MODE_SGMII_DUPLEX_HALF  0x0010
-
 /* Num of additional exact match MAC adr regs */
 #define MEMAC_NUM_OF_PADDRS 7
 
@@ -326,7 +295,9 @@ struct fman_mac {
struct fman_rev_info fm_rev_info;
bool basex_if;
struct phy *serdes;
-   struct phy_device *pcsphy;
+   struct phylink_pcs *sgmii_pcs;
+   struct phylink_pcs *qsgmii_pcs;
+   struct phylink_pcs *xfi_pcs;
bool allmulti_enabled;
 };
 
@@ -487,91 +458,22 @@ static u32 get_mac_addr_hash_code(u64 eth_addr)
return xor_val;
 }
 
-static void setup_sgmii_internal_phy(struct fman_mac *memac,
-struct fixed_phy_status *fixed_link)
+static void setup_sgmii_internal(struct fman_mac *memac,
+struct phylink_pcs *pcs,
+struct fixed_phy_status *fixed_link)
 {
-   u16 tmp_reg16;
-
-   if (WARN_ON(!memac->pcsphy))
-   return;
-
-   /* SGMII mode */
-   tmp_reg16 = IF_MODE_SGMII_EN;
-   if (!fixed_link)
-   /* AN enable */
-   tmp_reg16 |= IF_MODE_USE_SGMII_AN;
-   else {
-   switch (fixed_link->speed) {
-   case 10:
-  

[PATCH net-next v7 05/10] net: fman: memac: Add serdes support

[Sean Anderson]

This adds support for using a serdes which has to be configured. This is
primarly in preparation for phylink conversion, which will then change the
serdes mode dynamically.

Signed-off-by: Sean Anderson 
---

(no changes since v4)

Changes in v4:
- Don't fail if phy support was not compiled in

 .../net/ethernet/freescale/fman/fman_memac.c  | 49 ++-
 1 file changed, 47 insertions(+), 2 deletions(-)

diff --git a/drivers/net/ethernet/freescale/fman/fman_memac.c 
b/drivers/net/ethernet/freescale/fman/fman_memac.c
index 32d26cf17843..56a29f505590 100644
--- a/drivers/net/ethernet/freescale/fman/fman_memac.c
+++ b/drivers/net/ethernet/freescale/fman/fman_memac.c
@@ -13,6 +13,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 
 /* PCS registers */
@@ -324,6 +325,7 @@ struct fman_mac {
void *fm;
struct fman_rev_info fm_rev_info;
bool basex_if;
+   struct phy *serdes;
struct phy_device *pcsphy;
bool allmulti_enabled;
 };
@@ -1203,17 +1205,56 @@ int memac_initialization(struct mac_device *mac_dev,
}
}
 
+   memac->serdes = devm_of_phy_get(mac_dev->dev, mac_node, "serdes");
+   err = PTR_ERR(memac->serdes);
+   if (err == -ENODEV || err == -ENOSYS) {
+   dev_dbg(mac_dev->dev, "could not get (optional) serdes\n");
+   memac->serdes = NULL;
+   } else if (IS_ERR(memac->serdes)) {
+   dev_err_probe(mac_dev->dev, err, "could not get serdes\n");
+   goto _return_fm_mac_free;
+   } else {
+   err = phy_init(memac->serdes);
+   if (err) {
+   dev_err_probe(mac_dev->dev, err,
+ "could not initialize serdes\n");
+   goto _return_fm_mac_free;
+   }
+
+   err = phy_power_on(memac->serdes);
+   if (err) {
+   dev_err_probe(mac_dev->dev, err,
+ "could not power on serdes\n");
+   goto _return_phy_exit;
+   }
+
+   if (memac->phy_if == PHY_INTERFACE_MODE_SGMII ||
+   memac->phy_if == PHY_INTERFACE_MODE_1000BASEX ||
+   memac->phy_if == PHY_INTERFACE_MODE_2500BASEX ||
+   memac->phy_if == PHY_INTERFACE_MODE_QSGMII ||
+   memac->phy_if == PHY_INTERFACE_MODE_XGMII) {
+   err = phy_set_mode_ext(memac->serdes, PHY_MODE_ETHERNET,
+  memac->phy_if);
+   if (err) {
+   dev_err_probe(mac_dev->dev, err,
+ "could not set serdes mode to 
%s\n",
+ phy_modes(memac->phy_if));
+   goto _return_phy_power_off;
+   }
+   }
+   }
+
if (!mac_dev->phy_node && of_phy_is_fixed_link(mac_node)) {
struct phy_device *phy;
 
err = of_phy_register_fixed_link(mac_node);
if (err)
-   goto _return_fm_mac_free;
+   goto _return_phy_power_off;
 
fixed_link = kzalloc(sizeof(*fixed_link), GFP_KERNEL);
if (!fixed_link) {
err = -ENOMEM;
-   goto _return_fm_mac_free;
+   goto _return_phy_power_off;
}
 
mac_dev->phy_node = of_node_get(mac_node);
@@ -1242,6 +1283,10 @@ int memac_initialization(struct mac_device *mac_dev,
 
goto _return;
 
+_return_phy_power_off:
+   phy_power_off(memac->serdes);
+_return_phy_exit:
+   phy_exit(memac->serdes);
 _return_fixed_link_free:
kfree(fixed_link);
 _return_fm_mac_free:
-- 
2.35.1.1320.gc452695387.dirty

[PATCH net-next v7 04/10] net: phylink: provide phylink_validate_mask_caps() helper

[Sean Anderson]

From: "Russell King (Oracle)" 

Provide a helper that restricts the link modes according to the
phylink capabilities.

Signed-off-by: Russell King (Oracle) 
[rebased on net-next/master and added documentation]
Signed-off-by: Sean Anderson 
---

Changes in v7:
- New

 drivers/net/phy/phylink.c | 43 +++
 include/linux/phylink.h   |  3 +++
 2 files changed, 33 insertions(+), 13 deletions(-)

diff --git a/drivers/net/phy/phylink.c b/drivers/net/phy/phylink.c
index 75464df191ef..ef10f5a70e5a 100644
--- a/drivers/net/phy/phylink.c
+++ b/drivers/net/phy/phylink.c
@@ -561,6 +561,35 @@ unsigned long phylink_get_capabilities(phy_interface_t 
interface,
 }
 EXPORT_SYMBOL_GPL(phylink_get_capabilities);
 
+/**
+ * phylink_validate_mask_caps() - Restrict link modes based on caps
+ * @supported: ethtool bitmask for supported link modes.
+ * @state: an (optional) pointer to a  phylink_link_state.
+ * @mac_capabilities: bitmask of MAC capabilities
+ *
+ * Calculate the supported link modes based on @mac_capabilities, and restrict
+ * @supported and @state based on that. Use this function if your capabiliies
+ * aren't constant, such as if they vary depending on the interface.
+ */
+void phylink_validate_mask_caps(unsigned long *supported,
+   struct phylink_link_state *state,
+   unsigned long mac_capabilities)
+{
+   __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
+   unsigned long caps;
+
+   phylink_set_port_modes(mask);
+   phylink_set(mask, Autoneg);
+   caps = phylink_get_capabilities(state->interface, mac_capabilities,
+   state->rate_matching);
+   phylink_caps_to_linkmodes(mask, caps);
+
+   linkmode_and(supported, supported, mask);
+   if (state)
+   linkmode_and(state->advertising, state->advertising, mask);
+}
+EXPORT_SYMBOL_GPL(phylink_validate_mask_caps);
+
 /**
  * phylink_generic_validate() - generic validate() callback implementation
  * @config: a pointer to a  phylink_config.
@@ -569,24 +598,12 @@ EXPORT_SYMBOL_GPL(phylink_get_capabilities);
  *
  * Generic implementation of the validate() callback that MAC drivers can
  * use when they pass the range of supported interfaces and MAC capabilities.
- * This makes use of phylink_get_linkmodes().
  */
 void phylink_generic_validate(struct phylink_config *config,
  unsigned long *supported,
  struct phylink_link_state *state)
 {
-   __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
-   unsigned long caps;
-
-   phylink_set_port_modes(mask);
-   phylink_set(mask, Autoneg);
-   caps = phylink_get_capabilities(state->interface,
-   config->mac_capabilities,
-   state->rate_matching);
-   phylink_caps_to_linkmodes(mask, caps);
-
-   linkmode_and(supported, supported, mask);
-   linkmode_and(state->advertising, state->advertising, mask);
+   phylink_validate_mask_caps(supported, state, config->mac_capabilities);
 }
 EXPORT_SYMBOL_GPL(phylink_generic_validate);
 
diff --git a/include/linux/phylink.h b/include/linux/phylink.h
index 664dd409feb9..c29c3f174972 100644
--- a/include/linux/phylink.h
+++ b/include/linux/phylink.h
@@ -556,6 +556,9 @@ void phylink_caps_to_linkmodes(unsigned long *linkmodes, 
unsigned long caps);
 unsigned long phylink_get_capabilities(phy_interface_t interface,
   unsigned long mac_capabilities,
   int rate_matching);
+void phylink_validate_mask_caps(unsigned long *supported,
+   struct phylink_link_state *state,
+   unsigned long caps);
 void phylink_generic_validate(struct phylink_config *config,
  unsigned long *supported,
  struct phylink_link_state *state);
-- 
2.35.1.1320.gc452695387.dirty

[PATCH net-next v7 03/10] dt-bindings: net: fman: Add additional interface properties

[Sean Anderson]

At the moment, mEMACs are configured almost completely based on the
phy-connection-type. That is, if the phy interface is RGMII, it assumed
that RGMII is supported. For some interfaces, it is assumed that the
RCW/bootloader has set up the SerDes properly. This is generally OK, but
restricts runtime reconfiguration. The actual link state is never
reported.

To address these shortcomings, the driver will need additional
information. First, it needs to know how to access the PCS/PMAs (in
order to configure them and get the link status). The SGMII PCS/PMA is
the only currently-described PCS/PMA. Add the XFI and QSGMII PCS/PMAs as
well. The XFI (and 10GBASE-KR) PCS/PMA is a c45 "phy" which sits on the
same MDIO bus as SGMII PCS/PMA. By default they will have conflicting
addresses, but they are also not enabled at the same time by default.
Therefore, we can let the XFI PCS/PMA be the default when
phy-connection-type is xgmii. This will allow for
backwards-compatibility.

QSGMII, however, cannot work with the current binding. This is because
the QSGMII PCS/PMAs are only present on one MAC's MDIO bus. At the
moment this is worked around by having every MAC write to the PCS/PMA
addresses (without checking if they are present). This only works if
each MAC has the same configuration, and only if we don't need to know
the status. Because the QSGMII PCS/PMA will typically be located on a
different MDIO bus than the MAC's SGMII PCS/PMA, there is no fallback
for the QSGMII PCS/PMA.

Signed-off-by: Sean Anderson 
Reviewed-by: Rob Herring 
---

(no changes since v3)

Changes in v3:
- Add vendor prefix 'fsl,' to rgmii and mii properties.
- Set maxItems for pcs-names
- Remove phy-* properties from example because dt-schema complains and I
  can't be bothered to figure out how to make it work.
- Add pcs-handle as a preferred version of pcsphy-handle
- Deprecate pcsphy-handle
- Remove mii/rmii properties

Changes in v2:
- Better document how we select which PCS to use in the default case

 .../bindings/net/fsl,fman-dtsec.yaml  | 53 ++-
 .../devicetree/bindings/net/fsl-fman.txt  |  5 +-
 2 files changed, 43 insertions(+), 15 deletions(-)

diff --git a/Documentation/devicetree/bindings/net/fsl,fman-dtsec.yaml 
b/Documentation/devicetree/bindings/net/fsl,fman-dtsec.yaml
index 3a35ac1c260d..c80c880a9dab 100644
--- a/Documentation/devicetree/bindings/net/fsl,fman-dtsec.yaml
+++ b/Documentation/devicetree/bindings/net/fsl,fman-dtsec.yaml
@@ -85,9 +85,39 @@ properties:
 $ref: /schemas/types.yaml#/definitions/phandle
 description: A reference to the IEEE1588 timer
 
+  phys:
+description: A reference to the SerDes lane(s)
+maxItems: 1
+
+  phy-names:
+items:
+  - const: serdes
+
   pcsphy-handle:
-$ref: /schemas/types.yaml#/definitions/phandle
-description: A reference to the PCS (typically found on the SerDes)
+$ref: /schemas/types.yaml#/definitions/phandle-array
+minItems: 1
+maxItems: 3
+deprecated: true
+description: See pcs-handle.
+
+  pcs-handle:
+minItems: 1
+maxItems: 3
+description: |
+  A reference to the various PCSs (typically found on the SerDes). If
+  pcs-handle-names is absent, and phy-connection-type is "xgmii", then the 
first
+  reference will be assumed to be for "xfi". Otherwise, if 
pcs-handle-names is
+  absent, then the first reference will be assumed to be for "sgmii".
+
+  pcs-handle-names:
+minItems: 1
+maxItems: 3
+items:
+  enum:
+- sgmii
+- qsgmii
+- xfi
+description: The type of each PCS in pcsphy-handle.
 
   tbi-handle:
 $ref: /schemas/types.yaml#/definitions/phandle
@@ -100,6 +130,10 @@ required:
   - fsl,fman-ports
   - ptp-timer
 
+dependencies:
+  pcs-handle-names:
+- pcs-handle
+
 allOf:
   - $ref: ethernet-controller.yaml#
   - if:
@@ -110,14 +144,6 @@ allOf:
 then:
   required:
 - tbi-handle
-  - if:
-  properties:
-compatible:
-  contains:
-const: fsl,fman-memac
-then:
-  required:
-- pcsphy-handle
 
 unevaluatedProperties: false
 
@@ -138,8 +164,9 @@ examples:
 reg = <0xe8000 0x1000>;
 fsl,fman-ports = <_rx_0x0c _tx_0x2c>;
 ptp-timer = <_timer0>;
-pcsphy-handle = <>;
-phy-handle = <_phy1>;
-phy-connection-type = "sgmii";
+pcs-handle = <>, <_pcs1>;
+pcs-handle-names = "sgmii", "qsgmii";
+phys = < 1>;
+phy-names = "serdes";
 };
 ...
diff --git a/Documentation/devicetree/bindings/net/fsl-fman.txt 
b/Documentation/devicetree/bindings/net/fsl-fman.txt
index b9055335db3b..bda4b41af074 100644
--- a/Documentation/devicetree/bindings/net/fsl-fman.txt
+++ b/Documentation/devicetree/bindings/net/fsl-fman.txt
@@ -320,8 +320,9 @@ For internal PHY device on internal mdio bus, a PHY node 
should be created.
 See the definition of the PHY node in 

[PATCH net-next v7 02/10] dt-bindings: net: Add Lynx PCS binding

[Sean Anderson]

This binding is fairly bare-bones for now, since the Lynx driver doesn't
parse any properties (or match based on the compatible). We just need it
in order to prevent the PCS nodes from having phy devices attached to
them. This is not really a problem, but it is a bit inefficient.

This binding is really for three separate PCSs (SGMII, QSGMII, and XFI).
However, the driver treats all of them the same. This works because the
SGMII and XFI devices typically use the same address, and the SerDes
driver (or RCW) muxes between them. The QSGMII PCSs have the same
register layout as the SGMII PCSs. To do things properly, we'd probably
do something like

ethernet-pcs@0 {
#pcs-cells = <1>;
compatible = "fsl,lynx-pcs";
reg = <0>, <1>, <2>, <3>;
};

but that would add complexity, and we can describe the hardware just
fine using separate PCSs for now.

Signed-off-by: Sean Anderson 
Reviewed-by: Rob Herring 
---

(no changes since v5)

Changes in v5:
- New

 .../bindings/net/pcs/fsl,lynx-pcs.yaml| 40 +++
 1 file changed, 40 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/net/pcs/fsl,lynx-pcs.yaml

diff --git a/Documentation/devicetree/bindings/net/pcs/fsl,lynx-pcs.yaml 
b/Documentation/devicetree/bindings/net/pcs/fsl,lynx-pcs.yaml
new file mode 100644
index ..fbedf696c555
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/pcs/fsl,lynx-pcs.yaml
@@ -0,0 +1,40 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/pcs/fsl,lynx-pcs.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP Lynx PCS
+
+maintainers:
+  - Ioana Ciornei 
+
+description: |
+  NXP Lynx 10G and 28G SerDes have Ethernet PCS devices which can be used as
+  protocol controllers. They are accessible over the Ethernet interface's MDIO
+  bus.
+
+properties:
+  compatible:
+const: fsl,lynx-pcs
+
+  reg:
+maxItems: 1
+
+required:
+  - compatible
+  - reg
+
+additionalProperties: false
+
+examples:
+  - |
+mdio-bus {
+  #address-cells = <1>;
+  #size-cells = <0>;
+
+  qsgmii_pcs1: ethernet-pcs@1 {
+compatible = "fsl,lynx-pcs";
+reg = <1>;
+  };
+};
-- 
2.35.1.1320.gc452695387.dirty

[PATCH net-next v7 01/10] dt-bindings: net: Expand pcs-handle to an array

[Sean Anderson]

This allows multiple phandles to be specified for pcs-handle, such as
when multiple PCSs are present for a single MAC. To differentiate
between them, also add a pcs-handle-names property.

Signed-off-by: Sean Anderson 
Reviewed-by: Rob Herring 
---
This was previously submitted as [1]. I expect to update this series
more, so I have moved it here. Changes from that version include:
- Add maxItems to existing bindings
- Add a dependency from pcs-names to pcs-handle.

[1] 
https://lore.kernel.org/netdev/20220711160519.741990-3-sean.ander...@seco.com/

(no changes since v6)

Changes in v6:
- Remove unnecessary $ref from renesas,rzn1-a5psw
- Remove unnecessary type from pcs-handle-names
- Add maxItems to pcs-handle

Changes in v4:
- Use pcs-handle-names instead of pcs-names, as discussed

Changes in v3:
- New

 .../bindings/net/dsa/renesas,rzn1-a5psw.yaml  |  2 +-
 .../devicetree/bindings/net/ethernet-controller.yaml  | 11 ++-
 .../devicetree/bindings/net/fsl,qoriq-mc-dpmac.yaml   |  2 +-
 3 files changed, 12 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/net/dsa/renesas,rzn1-a5psw.yaml 
b/Documentation/devicetree/bindings/net/dsa/renesas,rzn1-a5psw.yaml
index 7ca9c19a157c..0a0d62b6c00e 100644
--- a/Documentation/devicetree/bindings/net/dsa/renesas,rzn1-a5psw.yaml
+++ b/Documentation/devicetree/bindings/net/dsa/renesas,rzn1-a5psw.yaml
@@ -74,10 +74,10 @@ properties:
 
 properties:
   pcs-handle:
+maxItems: 1
 description:
   phandle pointing to a PCS sub-node compatible with
   renesas,rzn1-miic.yaml#
-$ref: /schemas/types.yaml#/definitions/phandle
 
 unevaluatedProperties: false
 
diff --git a/Documentation/devicetree/bindings/net/ethernet-controller.yaml 
b/Documentation/devicetree/bindings/net/ethernet-controller.yaml
index 4b3c590fcebf..3aef506fa158 100644
--- a/Documentation/devicetree/bindings/net/ethernet-controller.yaml
+++ b/Documentation/devicetree/bindings/net/ethernet-controller.yaml
@@ -108,11 +108,17 @@ properties:
 $ref: "#/properties/phy-connection-type"
 
   pcs-handle:
-$ref: /schemas/types.yaml#/definitions/phandle
+$ref: /schemas/types.yaml#/definitions/phandle-array
+items:
+  maxItems: 1
 description:
   Specifies a reference to a node representing a PCS PHY device on a MDIO
   bus to link with an external PHY (phy-handle) if exists.
 
+  pcs-handle-names:
+description:
+  The name of each PCS in pcs-handle.
+
   phy-handle:
 $ref: /schemas/types.yaml#/definitions/phandle
 description:
@@ -216,6 +222,9 @@ properties:
 required:
   - speed
 
+dependencies:
+  pcs-handle-names: [pcs-handle]
+
 allOf:
   - if:
   properties:
diff --git a/Documentation/devicetree/bindings/net/fsl,qoriq-mc-dpmac.yaml 
b/Documentation/devicetree/bindings/net/fsl,qoriq-mc-dpmac.yaml
index 7f620a71a972..600240281e8c 100644
--- a/Documentation/devicetree/bindings/net/fsl,qoriq-mc-dpmac.yaml
+++ b/Documentation/devicetree/bindings/net/fsl,qoriq-mc-dpmac.yaml
@@ -31,7 +31,7 @@ properties:
   phy-mode: true
 
   pcs-handle:
-$ref: /schemas/types.yaml#/definitions/phandle
+maxItems: 1
 description:
   A reference to a node representing a PCS PHY device found on
   the internal MDIO bus.
-- 
2.35.1.1320.gc452695387.dirty

[PATCH net-next v7 00/10] net: dpaa: Convert to phylink

[Sean Anderson]

This series converts the DPAA driver to phylink.

I have tried to maintain backwards compatibility with existing device
trees whereever possible. However, one area where I was unable to
achieve this was with QSGMII. Please refer to patch 2 for details.

All mac drivers have now been converted. I would greatly appreciate if
anyone has T-series or P-series boards they can test/debug this series
on. I only have an LS1046ARDB. Everything but QSGMII should work without
breakage; QSGMII needs patches 7 and 8. For this reason, the last 4
patches in this series should be applied together (and should not go
through separate trees).

Changes in v7:
- provide phylink_validate_mask_caps() helper
- Fix oops if memac_pcs_create returned -EPROBE_DEFER
- Fix using pcs-names instead of pcs-handle-names
- Fix not checking for -ENODATA when looking for sgmii pcs
- Fix 81-character line
- Simplify memac_validate with phylink_validate_mask_caps

Changes in v6:
- Remove unnecessary $ref from renesas,rzn1-a5psw
- Remove unnecessary type from pcs-handle-names
- Add maxItems to pcs-handle
- Fix 81-character line
- Fix uninitialized variable in dtsec_mac_config

Changes in v5:
- Add Lynx PCS binding

Changes in v4:
- Use pcs-handle-names instead of pcs-names, as discussed
- Don't fail if phy support was not compiled in
- Split off rate adaptation series
- Split off DPAA "preparation" series
- Split off Lynx 10G support
- t208x: Mark MAC1 and MAC2 as 10G
- Add XFI PCS for t208x MAC1/MAC2

Changes in v3:
- Expand pcs-handle to an array
- Add vendor prefix 'fsl,' to rgmii and mii properties.
- Set maxItems for pcs-names
- Remove phy-* properties from example because dt-schema complains and I
  can't be bothered to figure out how to make it work.
- Add pcs-handle as a preferred version of pcsphy-handle
- Deprecate pcsphy-handle
- Remove mii/rmii properties
- Put the PCS mdiodev only after we are done with it (since the PCS
  does not perform a get itself).
- Remove _return label from memac_initialization in favor of returning
  directly
- Fix grabbing the default PCS not checking for -ENODATA from
  of_property_match_string
- Set DTSEC_ECNTRL_R100M in dtsec_link_up instead of dtsec_mac_config
- Remove rmii/mii properties
- Replace 1000Base... with 1000BASE... to match IEEE capitalization
- Add compatibles for QSGMII PCSs
- Split arm and powerpcs dts updates

Changes in v2:
- Better document how we select which PCS to use in the default case
- Move PCS_LYNX dependency to fman Kconfig
- Remove unused variable slow_10g_if
- Restrict valid link modes based on the phy interface. This is easier
  to set up, and mostly captures what I intended to do the first time.
  We now have a custom validate which restricts half-duplex for some SoCs
  for RGMII, but generally just uses the default phylink validate.
- Configure the SerDes in enable/disable
- Properly implement all ethtool ops and ioctls. These were mostly
  stubbed out just enough to compile last time.
- Convert 10GEC and dTSEC as well
- Fix capitalization of mEMAC in commit messages
- Add nodes for QSGMII PCSs
- Add nodes for QSGMII PCSs

Russell King (Oracle) (1):
  net: phylink: provide phylink_validate_mask_caps() helper

Sean Anderson (9):
  dt-bindings: net: Expand pcs-handle to an array
  dt-bindings: net: Add Lynx PCS binding
  dt-bindings: net: fman: Add additional interface properties
  net: fman: memac: Add serdes support
  net: fman: memac: Use lynx pcs driver
  net: dpaa: Convert to phylink
  powerpc: dts: t208x: Mark MAC1 and MAC2 as 10G
  powerpc: dts: qoriq: Add nodes for QSGMII PCSs
  arm64: dts: layerscape: Add nodes for QSGMII PCSs

 .../bindings/net/dsa/renesas,rzn1-a5psw.yaml  |   2 +-
 .../bindings/net/ethernet-controller.yaml |  11 +-
 .../bindings/net/fsl,fman-dtsec.yaml  |  53 +-
 .../bindings/net/fsl,qoriq-mc-dpmac.yaml  |   2 +-
 .../devicetree/bindings/net/fsl-fman.txt  |   5 +-
 .../bindings/net/pcs/fsl,lynx-pcs.yaml|  40 +
 .../boot/dts/freescale/fsl-ls1043-post.dtsi   |  24 +
 .../boot/dts/freescale/fsl-ls1046-post.dtsi   |  25 +
 .../fsl/qoriq-fman3-0-10g-0-best-effort.dtsi  |   3 +-
 .../boot/dts/fsl/qoriq-fman3-0-10g-0.dtsi |  10 +-
 .../fsl/qoriq-fman3-0-10g-1-best-effort.dtsi  |  10 +-
 .../boot/dts/fsl/qoriq-fman3-0-10g-1.dtsi |  10 +-
 .../boot/dts/fsl/qoriq-fman3-0-10g-2.dtsi |  45 ++
 .../boot/dts/fsl/qoriq-fman3-0-10g-3.dtsi |  45 ++
 .../boot/dts/fsl/qoriq-fman3-0-1g-0.dtsi  |   3 +-
 .../boot/dts/fsl/qoriq-fman3-0-1g-1.dtsi  |  10 +-
 .../boot/dts/fsl/qoriq-fman3-0-1g-2.dtsi  |  10 +-
 .../boot/dts/fsl/qoriq-fman3-0-1g-3.dtsi  |  10 +-
 .../boot/dts/fsl/qoriq-fman3-0-1g-4.dtsi  |   3 +-
 .../boot/dts/fsl/qoriq-fman3-0-1g-5.dtsi  |  10 +-
 .../boot/dts/fsl/qoriq-fman3-1-10g-0.dtsi |  10 +-
 .../boot/dts/fsl/qoriq-fman3-1-10g-1.dtsi |  10 +-
 .../boot/dts/fsl/qoriq-fman3-1-1g-0.dtsi  |   3 +-
 .../boot/dts/fsl/qoriq-fman3-1-1g-1.dtsi  |  10 +-
 

Re: [PATCH net-next v5 05/14] net: fman: Map the base address once

[Geert Uytterhoeven]

Hi Sean,

On Mon, Oct 17, 2022 at 5:34 PM Sean Anderson  wrote:
> On 10/17/22 11:15 AM, Geert Uytterhoeven wrote:
> > On Sat, Sep 3, 2022 at 12:00 AM Sean Anderson  
> > wrote:
> >> We don't need to remap the base address from the resource twice (once in
> >> mac_probe() and again in set_fman_mac_params()). We still need the
> >> resource to get the end address, but we can use a single function call
> >> to get both at once.
> >>
> >> While we're at it, use platform_get_mem_or_io and devm_request_resource
> >> to map the resource. I think this is the more "correct" way to do things
> >> here, since we use the pdev resource, instead of creating a new one.
> >> It's still a bit tricky, since we need to ensure that the resource is a
> >> child of the fman region when it gets requested.
> >>
> >> Signed-off-by: Sean Anderson 
> >> Acked-by: Camelia Groza 
> >
> > Thanks for your patch, which is now commit 262f2b782e255b79
> > ("net: fman: Map the base address once") in v6.1-rc1.
> >
> >> --- a/drivers/net/ethernet/freescale/dpaa/dpaa_eth_sysfs.c
> >> +++ b/drivers/net/ethernet/freescale/dpaa/dpaa_eth_sysfs.c
> >> @@ -18,7 +18,7 @@ static ssize_t dpaa_eth_show_addr(struct device *dev,
> >>
> >> if (mac_dev)
> >> return sprintf(buf, "%llx",
> >> -   (unsigned long long)mac_dev->res->start);
> >> +   (unsigned long long)mac_dev->vaddr);
> >
> > On 32-bit:
> >
> > warning: cast from pointer to integer of different size
> > [-Wpointer-to-int-cast]
> >
> > Obviously you should cast to "uintptr_t" or "unsigned long" instead,
> > and change the "%llx" to "%p" or "%lx"...
>
> Isn't there a %px for this purpose?

Yes there is.  But if it makes sense to use that depends on the
still to be answered questions at the bottom...

> > However, taking a closer look:
> >   1. The old code exposed a physical address to user space, the new
> >  code exposes the mapped virtual address.
> >  Is that change intentional?
>
> No, this is not intentional. So to make this backwards-compatible, I
> suppose I need a virt_to_phys?

I think virt_to_phys() will work only on real memory, not on MMIO,
so you may need to reintroduce the resource again.

> >   2. Virtual addresses are useless in user space.
> >  Moreover, addresses printed by "%p" are obfuscated, as this is
> >  considered a security issue. Likewise for working around this by
> >  casting to an integer.
>
> Yes, you're right that this probably shouldn't be exposed to userspace.
>
> > What's the real purpose of dpaa_eth_show_addr()?
>
> I have no idea. This is a question for Madalin.
>
> > Perhaps it should be removed?
>
> That would be reasonable IMO.

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

Re: [PATCH 1/2] tools/perf/tests/shell: Update stat+csv_output.sh to include sanity check for topology

[Disha Goel]

On 10/6/22 9:21 PM, Athira Rajeev wrote:

Testcase stat+csv_output.sh fails in powerpc:

84: perf stat CSV output linter: FAILED!

The testcase "stat+csv_output.sh" verifies perf stat
CSV output. The test covers aggregation modes like
per-socket, per-core, per-die, -A (no_aggr mode) along
with few other tests. It counts expected fields for
various commands. For example say -A (i.e, AGGR_NONE
mode), expects 7 fields in the output having "CPU" as
first field. Same way, for per-socket, it expects the
first field in result to point to socket id. The testcases
compares the result with expected count.

The values for socket, die, core and cpu are fetched
from topology directory:
/sys/devices/system/cpu/cpu*/topology.
For example, socket value is fetched from
"physical_package_id" file of topology directory.
(cpu__get_topology_int() in util/cpumap.c)

If a platform fails to fetch the topology information,
values will be set to -1. For example, incase of pSeries
platform of powerpc, value for  "physical_package_id" is
restricted and not exposed. So, -1 will be assigned.

Perf code has a checks for valid cpu id in "aggr_printout"
(stat-display.c), which displays the fields. So, in cases
where topology values not exposed, first field of the
output displaying will be empty. This cause the testcase
to fail, as it counts  number of fields in the output.

Incase of -A (AGGR_NONE mode,), testcase expects 7 fields
in the output, becos of -1 value obtained from topology
files for some, only 6 fields are printed. Hence a testcase
failure reported due to mismatch in number of fields in
the output.

Patch here adds a sanity check in the testcase for topology.
Check will help to skip the test if -1 value found.

Fixes: 7473ee56dbc9 ("perf test: Add checking for perf stat CSV output.")
Reported-by: Disha Goel 
Signed-off-by: Athira Rajeev 
Suggested-by: James Clark 
Suggested-by: Ian Rogers 


For the patchset,

Tested-by: Disha Goel 


---
  tools/perf/tests/shell/stat+csv_output.sh | 43 ---
  1 file changed, 39 insertions(+), 4 deletions(-)

diff --git a/tools/perf/tests/shell/stat+csv_output.sh 
b/tools/perf/tests/shell/stat+csv_output.sh
index eb5196f58190..b7f050aa6210 100755
--- a/tools/perf/tests/shell/stat+csv_output.sh
+++ b/tools/perf/tests/shell/stat+csv_output.sh
@@ -6,6 +6,8 @@

  set -e

+skip_test=0
+
  function commachecker()
  {
local -i cnt=0
@@ -156,14 +158,47 @@ check_per_socket()
echo "[Success]"
  }

+# The perf stat options for per-socket, per-core, per-die
+# and -A ( no_aggr mode ) uses the info fetched from this
+# directory: "/sys/devices/system/cpu/cpu*/topology". For
+# example, socket value is fetched from "physical_package_id"
+# file in topology directory.
+# Reference: cpu__get_topology_int in util/cpumap.c
+# If the platform doesn't expose topology information, values
+# will be set to -1. For example, incase of pSeries platform
+# of powerpc, value for  "physical_package_id" is restricted
+# and set to -1. Check here validates the socket-id read from
+# topology file before proceeding further
+
+FILE_LOC="/sys/devices/system/cpu/cpu*/topology/"
+FILE_NAME="physical_package_id"
+
+check_for_topology()
+{
+   if ! ParanoidAndNotRoot 0
+   then
+   socket_file=`ls $FILE_LOC/$FILE_NAME | head -n 1`
+   [ -z $socket_file ] && return 0
+   socket_id=`cat $socket_file`
+   [ $socket_id == -1 ] && skip_test=1
+   return 0
+   fi
+}
+
+check_for_topology
  check_no_args
  check_system_wide
-check_system_wide_no_aggr
  check_interval
  check_event
-check_per_core
  check_per_thread
-check_per_die
  check_per_node
-check_per_socket
+if [ $skip_test -ne 1 ]
+then
+   check_system_wide_no_aggr
+   check_per_core
+   check_per_die
+   check_per_socket
+else
+   echo "[Skip] Skipping tests for system_wide_no_aggr, per_core, per_die and 
per_socket since socket id exposed via topology is invalid"
+fi
  exit 0

Re: [PATCH net-next v5 05/14] net: fman: Map the base address once

[Sean Anderson]

On 10/17/22 11:15 AM, Geert Uytterhoeven wrote:
> Hi Sean,
> 
> On Sat, Sep 3, 2022 at 12:00 AM Sean Anderson  wrote:
>> We don't need to remap the base address from the resource twice (once in
>> mac_probe() and again in set_fman_mac_params()). We still need the
>> resource to get the end address, but we can use a single function call
>> to get both at once.
>>
>> While we're at it, use platform_get_mem_or_io and devm_request_resource
>> to map the resource. I think this is the more "correct" way to do things
>> here, since we use the pdev resource, instead of creating a new one.
>> It's still a bit tricky, since we need to ensure that the resource is a
>> child of the fman region when it gets requested.
>>
>> Signed-off-by: Sean Anderson 
>> Acked-by: Camelia Groza 
> 
> Thanks for your patch, which is now commit 262f2b782e255b79
> ("net: fman: Map the base address once") in v6.1-rc1.
> 
>> --- a/drivers/net/ethernet/freescale/dpaa/dpaa_eth_sysfs.c
>> +++ b/drivers/net/ethernet/freescale/dpaa/dpaa_eth_sysfs.c
>> @@ -18,7 +18,7 @@ static ssize_t dpaa_eth_show_addr(struct device *dev,
>>
>> if (mac_dev)
>> return sprintf(buf, "%llx",
>> -   (unsigned long long)mac_dev->res->start);
>> +   (unsigned long long)mac_dev->vaddr);
> 
> On 32-bit:
> 
> warning: cast from pointer to integer of different size
> [-Wpointer-to-int-cast]
> 
> Obviously you should cast to "uintptr_t" or "unsigned long" instead,
> and change the "%llx" to "%p" or "%lx"...

Isn't there a %px for this purpose?

> However, taking a closer look:
>   1. The old code exposed a physical address to user space, the new
>  code exposes the mapped virtual address.
>  Is that change intentional?

No, this is not intentional. So to make this backwards-compatible, I
suppose I need a virt_to_phys?

>   2. Virtual addresses are useless in user space.
>  Moreover, addresses printed by "%p" are obfuscated, as this is
>  considered a security issue. Likewise for working around this by
>  casting to an integer.

Yes, you're right that this probably shouldn't be exposed to userspace.

> What's the real purpose of dpaa_eth_show_addr()?

I have no idea. This is a question for Madalin.

> Perhaps it should be removed?

That would be reasonable IMO.

--Sean

>> else
>> return sprintf(buf, "none");
>>  }
> 
> Gr{oetje,eeting}s,
> 
> Geert
> 
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- 
> ge...@linux-m68k.org
> 
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like 
> that.
> -- Linus Torvalds
> 

Re: [PATCH net-next v5 05/14] net: fman: Map the base address once

[Geert Uytterhoeven]

Hi Sean,

On Sat, Sep 3, 2022 at 12:00 AM Sean Anderson  wrote:
> We don't need to remap the base address from the resource twice (once in
> mac_probe() and again in set_fman_mac_params()). We still need the
> resource to get the end address, but we can use a single function call
> to get both at once.
>
> While we're at it, use platform_get_mem_or_io and devm_request_resource
> to map the resource. I think this is the more "correct" way to do things
> here, since we use the pdev resource, instead of creating a new one.
> It's still a bit tricky, since we need to ensure that the resource is a
> child of the fman region when it gets requested.
>
> Signed-off-by: Sean Anderson 
> Acked-by: Camelia Groza 

Thanks for your patch, which is now commit 262f2b782e255b79
("net: fman: Map the base address once") in v6.1-rc1.

> --- a/drivers/net/ethernet/freescale/dpaa/dpaa_eth_sysfs.c
> +++ b/drivers/net/ethernet/freescale/dpaa/dpaa_eth_sysfs.c
> @@ -18,7 +18,7 @@ static ssize_t dpaa_eth_show_addr(struct device *dev,
>
> if (mac_dev)
> return sprintf(buf, "%llx",
> -   (unsigned long long)mac_dev->res->start);
> +   (unsigned long long)mac_dev->vaddr);

On 32-bit:

warning: cast from pointer to integer of different size
[-Wpointer-to-int-cast]

Obviously you should cast to "uintptr_t" or "unsigned long" instead,
and change the "%llx" to "%p" or "%lx"...

However, taking a closer look:
  1. The old code exposed a physical address to user space, the new
 code exposes the mapped virtual address.
 Is that change intentional?
  2. Virtual addresses are useless in user space.
 Moreover, addresses printed by "%p" are obfuscated, as this is
 considered a security issue. Likewise for working around this by
 casting to an integer.

What's the real purpose of dpaa_eth_show_addr()?
Perhaps it should be removed?

> else
> return sprintf(buf, "none");
>  }

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

Re: [PATCH] powerpc/perf: Fix hv-24x7 metric events for power10

[Arnaldo Carvalho de Melo]

Em Fri, Oct 14, 2022 at 07:32:20PM +0530, Kajol Jain escreveu:
> Testcase stat_all_metrics.sh fails in powerpc:
> 
> 90: perf all metrics test : FAILED!
> 
> The testcase "stat_all_metrics.sh" verifies perf stat
> result for all the metric events present in perf list.
> It runs perf metric events with various commands and
> expects non-empty metric result.
> 
> Incase of powerpc:hv-24x7 events, some of the event count can
> be 0 based on system configuration. And if that event used as
> denominator in divide equation, it can cause divide by 0
> error. The current nest_metric.json file creating divide by 0
> issue for some of the metric events, which results in failure
> of the "stat_all_metrics.sh" test case.
> 
> Most of the metrics events have cycles or an event which
> expect to have a larger value as denominator, so adding 1
> to the denominator of the metric expression as a fix.
> 
> Result in powerpc box after this patch changes:
> 
> 90: perf all metrics test : Ok

Looks ok, applied. Next time please try to ask others to provide a
Reviewed-by or at least an Acked-by.

- Arnaldo
 
> Fixes: a3cbcadfdfc3 ("perf vendor events power10: Adds 24x7 nest
> metric events for power10 platform")
> Signed-off-by: Kajol Jain 
> ---
>  .../arch/powerpc/power10/nest_metrics.json| 72 +--
>  1 file changed, 36 insertions(+), 36 deletions(-)
> 
> diff --git a/tools/perf/pmu-events/arch/powerpc/power10/nest_metrics.json 
> b/tools/perf/pmu-events/arch/powerpc/power10/nest_metrics.json
> index 8ba3e81c9808..fe050d44374b 100644
> --- a/tools/perf/pmu-events/arch/powerpc/power10/nest_metrics.json
> +++ b/tools/perf/pmu-events/arch/powerpc/power10/nest_metrics.json
> @@ -1,13 +1,13 @@
>  [
>  {
>"MetricName": "VEC_GROUP_PUMP_RETRY_RATIO_P01",
> -  "MetricExpr": "(hv_24x7@PM_PB_RTY_VG_PUMP01\\,chip\\=?@ / 
> hv_24x7@PM_PB_VG_PUMP01\\,chip\\=?@) * 100",
> +  "MetricExpr": "(hv_24x7@PM_PB_RTY_VG_PUMP01\\,chip\\=?@ / (1 + 
> hv_24x7@PM_PB_VG_PUMP01\\,chip\\=?@)) * 100",
>"ScaleUnit": "1%",
>"AggregationMode": "PerChip"
>  },
>  {
>"MetricName": "VEC_GROUP_PUMP_RETRY_RATIO_P23",
> -  "MetricExpr": "(hv_24x7@PM_PB_RTY_VG_PUMP23\\,chip\\=?@ / 
> hv_24x7@PM_PB_VG_PUMP23\\,chip\\=?@) * 100",
> +  "MetricExpr": "(hv_24x7@PM_PB_RTY_VG_PUMP23\\,chip\\=?@ / (1 + 
> hv_24x7@PM_PB_VG_PUMP23\\,chip\\=?@)) * 100",
>"ScaleUnit": "1%",
>"AggregationMode": "PerChip"
>  },
> @@ -61,13 +61,13 @@
>  },
>  {
>"MetricName": "REMOTE_NODE_PUMPS_RETRIES_RATIO_P01",
> -  "MetricExpr": "(hv_24x7@PM_PB_RTY_RNS_PUMP01\\,chip\\=?@ / 
> hv_24x7@PM_PB_RNS_PUMP01\\,chip\\=?@) * 100",
> +  "MetricExpr": "(hv_24x7@PM_PB_RTY_RNS_PUMP01\\,chip\\=?@ / (1 + 
> hv_24x7@PM_PB_RNS_PUMP01\\,chip\\=?@)) * 100",
>"ScaleUnit": "1%",
>"AggregationMode": "PerChip"
>  },
>  {
>"MetricName": "REMOTE_NODE_PUMPS_RETRIES_RATIO_P23",
> -  "MetricExpr": "(hv_24x7@PM_PB_RTY_RNS_PUMP23\\,chip\\=?@ / 
> hv_24x7@PM_PB_RNS_PUMP23\\,chip\\=?@) * 100",
> +  "MetricExpr": "(hv_24x7@PM_PB_RTY_RNS_PUMP23\\,chip\\=?@ / (1 + 
> hv_24x7@PM_PB_RNS_PUMP23\\,chip\\=?@)) * 100",
>"ScaleUnit": "1%",
>"AggregationMode": "PerChip"
>  },
> @@ -151,193 +151,193 @@
>  },
>  {
>"MetricName": "XLINK0_OUT_TOTAL_UTILIZATION",
> -  "MetricExpr": "((hv_24x7@PM_XLINK0_OUT_ODD_TOTAL_UTIL\\,chip\\=?@ + 
> hv_24x7@PM_XLINK0_OUT_EVEN_TOTAL_UTIL\\,chip\\=?@) / 
> (hv_24x7@PM_XLINK0_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + 
> hv_24x7@PM_XLINK0_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
> +  "MetricExpr": "((hv_24x7@PM_XLINK0_OUT_ODD_TOTAL_UTIL\\,chip\\=?@ + 
> hv_24x7@PM_XLINK0_OUT_EVEN_TOTAL_UTIL\\,chip\\=?@) / (1 + 
> hv_24x7@PM_XLINK0_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + 
> hv_24x7@PM_XLINK0_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
>"ScaleUnit": "1%",
>"AggregationMode": "PerChip"
>  },
>  {
>"MetricName": "XLINK1_OUT_TOTAL_UTILIZATION",
> -  "MetricExpr": "((hv_24x7@PM_XLINK1_OUT_ODD_TOTAL_UTIL\\,chip\\=?@ + 
> hv_24x7@PM_XLINK1_OUT_EVEN_TOTAL_UTIL\\,chip\\=?@) / 
> (hv_24x7@PM_XLINK1_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + 
> hv_24x7@PM_XLINK1_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
> +  "MetricExpr": "((hv_24x7@PM_XLINK1_OUT_ODD_TOTAL_UTIL\\,chip\\=?@ + 
> hv_24x7@PM_XLINK1_OUT_EVEN_TOTAL_UTIL\\,chip\\=?@) / (1 + 
> hv_24x7@PM_XLINK1_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + 
> hv_24x7@PM_XLINK1_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
>"ScaleUnit": "1%",
>"AggregationMode": "PerChip"
>  },
>  {
>"MetricName": "XLINK2_OUT_TOTAL_UTILIZATION",
> -  "MetricExpr": "((hv_24x7@PM_XLINK2_OUT_ODD_TOTAL_UTIL\\,chip\\=?@ + 
> hv_24x7@PM_XLINK2_OUT_EVEN_TOTAL_UTIL\\,chip\\=?@) / 
> (hv_24x7@PM_XLINK2_OUT_ODD_AVLBL_CYCLES\\,chip\\=?@ + 
> hv_24x7@PM_XLINK2_OUT_EVEN_AVLBL_CYCLES\\,chip\\=?@)) * 100",
> +  "MetricExpr": 

Re: [PATCH v2] perf: Rewrite core context handling

[Ravi Bangoria]

On 14-Oct-22 3:26 PM, Ravi Bangoria wrote:
> On 13-Oct-22 4:29 PM, Peter Zijlstra wrote:
>> On Thu, Oct 13, 2022 at 03:37:23PM +0530, Ravi Bangoria wrote:
>>
 -  refcount_t  refcount;
 +  refcount_t  refcount; /* event <-> ctx */
>>>
>>> Ok. We need to remove all those // XXX get/put_ctx() from code
>>> which we added to make refcount a pmu_ctx <-> ctx.
>>
>> Them already gone :-) I've not yet fixed up the typoes, but current
>> version should be here:
>>
>>   
>> https://git.kernel.org/pub/scm/linux/kernel/git/peterz/queue.git/log/?h=perf/core
>>
>> Thanks!
> 
> I've been running perf-fuzzer on Xeon machine since yesterday and I don't see 
> any
> issue. Will do the same on my AMD machine as well over the weekend.

Only one WARN_ON() hit. Otherwise all good.
https://lore.kernel.org/lkml/8d91528b-e830-6ad0-8a92-621ce9f94...@amd.com

Thanks,
Ravi

Re: [PATCH] powerpc/xive: add missing iounmap() in error path in xive_spapr_populate_irq_data()

[Cédric Le Goater]

On 10/17/22 05:23, Yang Yingliang wrote:

If remapping 'data->trig_page' fails, the 'data->eoi_mmio' need be unmapped
before returning from xive_spapr_populate_irq_data().

Fixes: eac1e731b59e ("powerpc/xive: guest exploitation of the XIVE interrupt 
controller")
Signed-off-by: Yang Yingliang 


Reviewed-by: Cédric Le Goater 

Thanks,

C.

---
  arch/powerpc/sysdev/xive/spapr.c | 1 +
  1 file changed, 1 insertion(+)

diff --git a/arch/powerpc/sysdev/xive/spapr.c b/arch/powerpc/sysdev/xive/spapr.c
index e2c8f93b535b..e45419264391 100644
--- a/arch/powerpc/sysdev/xive/spapr.c
+++ b/arch/powerpc/sysdev/xive/spapr.c
@@ -439,6 +439,7 @@ static int xive_spapr_populate_irq_data(u32 hw_irq, struct 
xive_irq_data *data)
  
  	data->trig_mmio = ioremap(data->trig_page, 1u << data->esb_shift);

if (!data->trig_mmio) {
+   iounmap(data->eoi_mmio);
pr_err("Failed to map trigger page for irq 0x%x\n", hw_irq);
return -ENOMEM;
}

Re: Issues with the first PowerPC updates for the kernel 6.1

[Christian Zigotzky]

> On 17. Oct 2022, at 02:43, Michael Ellerman  wrote:
> Previously BIG_ENDIAN && GENERIC_CPU would use -mcpu=power5, now it uses
> -mcpu=power4.

Maybe this is the issue. We will wait and not release the RC1 for testing 
because it is a risk for our testers to test these new kernels because of this 
issue.

It is really important do not to rewrite code, that is well worked before.
Bugfixing and adding some new features is ok but rewriting of good code is 
expensive and doesn’t make any sense.

— Christian

> 
> 
> cheers
> 
 On 16. Oct 2022, at 18:51, Segher Boessenkool  
 wrote:
>>> 
>>> On Fri, Oct 14, 2022 at 06:11:21PM +0200, Christian Zigotzky wrote:
 make oldconfig has asked because of the CPU family. I choosed GENERIC for 
 my P.A. Semi PWRficient PA6T-1682M. Is this correct? Maybe this is the 
 problem.
 
 config GENERIC_CPU
 -bool "Generic (POWER4 and above)"
 +bool "Generic (POWER5 and PowerPC 970 and above)"
   depends on PPC_BOOK3S_64 && !CPU_LITTLE_ENDIAN
   select PPC_64S_HASH_MMU
 
 There isn’t a POWER4 anymore and I used it via CONFIG_GENERIC_CPU=y before.
>>> 
>>> PA6T is ISA 2.04, just like POWER5+.  It should be fine.
>>> 
>>> 
>>> Segher

Re: [PATCH v4 5/5] drm/ofdrm: Support big-endian scanout buffers

[Benjamin Herrenschmidt]

On Thu, 2022-10-13 at 09:39 +0200, Javier Martinez Canillas wrote:
> > In absence of such test results I think the most reasonable thing is to
> > keep the logic that nobody complained about for 10+ years.
> > 
> 
> I agree with Michal and Thomas on this. I don't see a strong reason to not
> use the same heuristic that the offb fbdev driver has been doing for this.
> 
> Otherwise if this turns out to be needed, it will cause a regression for a
> user that switches to this driver instead. Specially since both fbdev and
> DRM drivers match against the same "display" OF compatible string.

I agree.

In the end, what it boils down to is, we don't know, we should guess. The
endianness of the kernel is as good a guess as anything here.

If not that, then assume BE.

That code was originally written for old macs. Those could simply not boot
anything other than a BE kernel. OF would always setup a 8bpp fb (so endianness
is irrelevant) but BootX could setup something else.

There's almost no old LE powerpc system out there, and I'm reasonably sure
actually none of any relevance to this code.

That leaves us with newer systems capable of endian switching. Those should just
get the property added.

I don't know of many cases out there. There' SLOS on powerpc which still won't
set it (which is what qemu uses). That could just be fixed. In the meantime
it makes sense for the kernel to follow its existing behaviour.

Cheers,
Ben.