On Fri, 30 May 2008 11:13:23 +1000
Benjamin Herrenschmidt [EMAIL PROTECTED] wrote:
Currently, this is the only interface I know that can do native-endian
accesses, so if you take it away, I'm gonna need an alternative
interface that doesn't do byteswapping.
Are you aware that these
This patch extends the FSL UPM NAND driver from Anton Vorontsov to
support for the TQM85xx modules. Unfortunately, the hardware does
not support the R/B pins of the NAND chip and therefore the specified
maximum delay time must used. It therefore re-introduces the chip-delay
property.
Note: this
the following series of patches adds support for the TQM8548 modules from
TQ Components (http://www.tqc.de) and fixes furthermore some issues with
other TQM85xx modules.
The NAND support is based on the patch with the subject
[PATCH] [NAND] driver extension to support NAND on TQM85xx modules
Some TQM85xx boards could be equipped with up to 1 GiB (NOR) flash
memory and therefore a modified memory map is required and setup by
the board loader. This patch adds an appropriate DTS file.
Signed-off-by: Wolfgang Grandegger [EMAIL PROTECTED]
---
arch/powerpc/boot/dts/tqm8548-bigflash.dts |
This patch adds support for the TQM8548 modules from TQ-Components
GmbH (http://www.tqc.de).
Signed-off-by: Wolfgang Grandegger [EMAIL PROTECTED]
---
arch/powerpc/boot/Makefile |1 +
arch/powerpc/boot/dts/tqm8548.dts | 370 +
arch/powerpc/boot/wrapper
Signed-off-by: Wolfgang Grandegger [EMAIL PROTECTED]
---
arch/powerpc/boot/dts/tqm8560.dts | 66 +
1 files changed, 66 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/boot/dts/tqm8560.dts
b/arch/powerpc/boot/dts/tqm8560.dts
index b9ac6c9..c2c25cd
Like for the TQM5200, the vendor prefix tqc, is now used for all
TQM85xx modules from TQ-Components GmbH (http://www.tqc.de) in the
corresponding DTS files.
Signed-off-by: Wolfgang Grandegger [EMAIL PROTECTED]
---
arch/powerpc/boot/dts/tqm8540.dts |4 ++--
Hi Wolfgang,
On Fri, 30 May 2008 08:49:45 +0200 Wolfgang Grandegger [EMAIL PROTECTED]
wrote:
+++ b/arch/powerpc/platforms/85xx/tqm85xx.c
@@ -120,8 +120,17 @@ static void __init tqm85xx_setup_arch(void)
#endif
#ifdef CONFIG_PCI
- for_each_compatible_node(np, pci, fsl,mpc8540-pci)
Stephen Rothwell wrote:
Hi Wolfgang,
On Fri, 30 May 2008 08:49:45 +0200 Wolfgang Grandegger [EMAIL PROTECTED]
wrote:
+++ b/arch/powerpc/platforms/85xx/tqm85xx.c
@@ -120,8 +120,17 @@ static void __init tqm85xx_setup_arch(void)
#endif
#ifdef CONFIG_PCI
-
On Fri, 2008-05-30 at 08:07 +0200, Haavard Skinnemoen wrote:
On Fri, 30 May 2008 11:13:23 +1000
Benjamin Herrenschmidt [EMAIL PROTECTED] wrote:
Currently, this is the only interface I know that can do native-endian
accesses, so if you take it away, I'm gonna need an alternative
On Friday 30 May 2008, Wolfgang Grandegger wrote:
#ifdef CONFIG_PCI
- for_each_compatible_node(np, pci, fsl,mpc8540-pci)
- fsl_add_bridge(np, 1);
+ for_each_node_by_type(np, pci) {
+ if (of_device_is_compatible(np, fsl,mpc8540-pci) ||
+
On Fri, 30 May 2008 17:24:27 +1000
Benjamin Herrenschmidt [EMAIL PROTECTED] wrote:
On Fri, 2008-05-30 at 08:07 +0200, Haavard Skinnemoen wrote:
I think the drivers I've written have the necessary barriers (or dma
ops with implicit barriers) that they don't actually depend on any
DMA vs.
On Fri, 30 May 2008, Haavard Skinnemoen wrote:
Maybe we need another interface that does not do byteswapping but
provides stronger ordering guarantees?
The byte swapping depends on the device/bus.
So what happened to the old idea of putting the accessor function pointers
in the device/bus
James Bottomley wrote:
The only way to guarantee ordering in the above setup, is to either
make writel() fully ordered or adding the mmiowb()'s inbetween the two
writel's. On Altix you have to go and read from the PCI brige to
ensure all writes to it have been flushed, which is also what
Jesse Barnes wrote:
On Thursday, May 29, 2008 2:40 pm Benjamin Herrenschmidt wrote:
On Thu, 2008-05-29 at 10:47 -0400, Jes Sorensen wrote:
The only way to guarantee ordering in the above setup, is to either
make writel() fully ordered or adding the mmiowb()'s inbetween the two
writel's. On
Benjamin Herrenschmidt wrote:
On Thu, 2008-05-29 at 10:47 -0400, Jes Sorensen wrote:
The only way to guarantee ordering in the above setup, is to either
make writel() fully ordered or adding the mmiowb()'s inbetween the two
writel's. On Altix you have to go and read from the PCI brige to
ensure
On Fri, May 30, 2008 at 08:49:46AM +0200, Wolfgang Grandegger wrote:
Some TQM85xx boards could be equipped with up to 1 GiB (NOR) flash
memory and therefore a modified memory map is required and setup by
the board loader. This patch adds an appropriate DTS file.
Signed-off-by: Wolfgang
On Fri, May 30, 2008 at 08:36:32AM +0200, Wolfgang Grandegger wrote:
This patch extends the FSL UPM NAND driver from Anton Vorontsov to
support for the TQM85xx modules. Unfortunately, the hardware does
not support the R/B pins of the NAND chip and therefore the specified
maximum delay time
From: Wolfgang Grandegger [EMAIL PROTECTED]
Since commit 7560fa60fcdcdb0da662f6a9fad9064b554ef46c (gpio: linux/gpio.h
and no GPIO support here stubs) drivers can use GPIOs if they're available,
but don't require them.
This patch actually enables this feature.
Signed-off-by: Wolfgang Grandegger
On Tue, May 27, 2008 at 07:16:28PM +0400, Anton Vorontsov wrote:
On Tue, May 27, 2008 at 10:04:20AM -0500, Kumar Gala wrote:
On May 23, 2008, at 11:39 AM, Anton Vorontsov wrote:
This is needed to access QE GPIOs via Linux GPIO API.
Signed-off-by: Anton Vorontsov [EMAIL PROTECTED]
On May 30, 2008, at 1:36 AM, Wolfgang Grandegger wrote:
This patch extends the FSL UPM NAND driver from Anton Vorontsov to
support for the TQM85xx modules. Unfortunately, the hardware does
not support the R/B pins of the NAND chip and therefore the specified
maximum delay time must used. It
Kumar Gala wrote:
On May 30, 2008, at 1:36 AM, Wolfgang Grandegger wrote:
This patch extends the FSL UPM NAND driver from Anton Vorontsov to
support for the TQM85xx modules. Unfortunately, the hardware does
not support the R/B pins of the NAND chip and therefore the specified
maximum
Hi,
On May 30, 2008, at 12:25 AM, Stephen Rothwell wrote:
On Thu, 29 May 2008 15:05:44 -0500 Olof Johansson [EMAIL PROTECTED]
wrote:
electra_cf: Add MODULE_DEVICE_TABLE()
Add a module device table to electra_cf so that modules can be
auto-probed/loaded.
[will be included in git pull
On May 15, 2008, at 5:46 PM, Timur Tabi wrote:
The i2c_devices[] array in fsl_soc.c lists all the I2C nodes that
are supported
on Freescale boards. Add an entry for the Cirrus Logic CS4270 so
that a
new-style CS4270 driver will work.
Signed-off-by: Timur Tabi [EMAIL PROTECTED]
---
On May 15, 2008, at 5:04 PM, Timur Tabi wrote:
Update of_find_i2c_driver in fsl_soc.c to display a warning message
if an
I2C node in the device tree isn't found in the i2c_devices[] array.
Signed-off-by: Timur Tabi [EMAIL PROTECTED]
---
arch/powerpc/sysdev/fsl_soc.c |4
1 files
On May 8, 2008, at 7:47 AM, Bryan O'Donoghue wrote:
Greetings.
Attached is a patchset to support the ASP8347E.
http://www.analogue-micro.com/ASP8347.html. Due to the fact that the
board
shipped with a root filesystem that requires devfs, you have to run
a different
rootfs with all
On Friday, May 30, 2008 2:36 am Jes Sorensen wrote:
James Bottomley wrote:
The only way to guarantee ordering in the above setup, is to either
make writel() fully ordered or adding the mmiowb()'s inbetween the two
writel's. On Altix you have to go and read from the PCI brige to
ensure all
Anton Vorontsov wrote:
On Fri, May 30, 2008 at 08:49:46AM +0200, Wolfgang Grandegger wrote:
Some TQM85xx boards could be equipped with up to 1 GiB (NOR) flash
memory and therefore a modified memory map is required and setup by
the board loader. This patch adds an appropriate DTS file.
Hi.
On Thu, May 29, 2008 at 02:12:50PM -0500, Kim Phillips ([EMAIL PROTECTED])
wrote:
+static irqreturn_t talitos_interrupt(int irq, void *data)
+{
+ struct device *dev = data;
+ struct talitos_private *priv = dev_get_drvdata(dev);
+
+ priv-status = in_be32(priv-reg +
David Gibson wrote:
What I don't like is the combination of the two. Using the /word/
form in (1) suggests that each /word/ is a lexically distinct symbol
with functions in different contexts: consider /dts-v1/, /include/,
/memreserve/ - they're all used only in their own distinct context.
Use
On Fri, 30 May 2008 22:09:04 +0400
Evgeniy Polyakov [EMAIL PROTECTED] wrote:
Hi.
On Thu, May 29, 2008 at 02:12:50PM -0500, Kim Phillips ([EMAIL PROTECTED])
wrote:
+static irqreturn_t talitos_interrupt(int irq, void *data)
+{
+ struct device *dev = data;
+ struct
Kim Phillips wrote:
On Fri, 30 May 2008 22:09:04 +0400
Evgeniy Polyakov [EMAIL PROTECTED] wrote:
Don't you want to protect against simultaneous access to register space
from different CPUs? Or it is single processor board only?
Doesn't linux mask the IRQ line for the interrupt currently being
On May 30, 2008, at 1:49 AM, Wolfgang Grandegger wrote:
Some TQM85xx boards could be equipped with up to 1 GiB (NOR) flash
memory and therefore a modified memory map is required and setup by
the board loader. This patch adds an appropriate DTS file.
Signed-off-by: Wolfgang Grandegger [EMAIL
Kumar Gala wrote:
+mpic: [EMAIL PROTECTED] {
+clock-frequency = 0;
remove clock-frequency
Where would one express the PIC timer frequency, then?
+interrupt-controller;
+#address-cells = 0;
+#interrupt-cells = 2;
+reg =
On May 30, 2008, at 3:07 PM, Scott Wood wrote:
Kumar Gala wrote:
+mpic: [EMAIL PROTECTED] {
+clock-frequency = 0;
remove clock-frequency
Where would one express the PIC timer frequency, then?
+interrupt-controller;
+#address-cells = 0;
+
On Fri, May 30, 2008 at 02:41:17PM -0500, Scott Wood ([EMAIL PROTECTED]) wrote:
Don't you want to protect against simultaneous access to register space
from different CPUs? Or it is single processor board only?
Doesn't linux mask the IRQ line for the interrupt currently being
serviced, and
On Fri, 30 May 2008 14:41:17 -0500
Scott Wood [EMAIL PROTECTED] wrote:
Kim Phillips wrote:
On Fri, 30 May 2008 22:09:04 +0400
Evgeniy Polyakov [EMAIL PROTECTED] wrote:
Don't you want to protect against simultaneous access to register space
from different CPUs? Or it is single processor
Kim Phillips wrote:
On Fri, 30 May 2008 14:41:17 -0500
Scott Wood [EMAIL PROTECTED] wrote:
Kim Phillips wrote:
On Fri, 30 May 2008 22:09:04 +0400
Evgeniy Polyakov [EMAIL PROTECTED] wrote:
Don't you want to protect against simultaneous access to register space
from different CPUs? Or it is
Removed clock-frequency and big-endian props as they aren't specified
anywhere.
---
In my powerpc-next branch.
Documentation/powerpc/booting-without-of.txt |6 --
arch/powerpc/boot/dts/mpc7448hpc2.dts|2 --
arch/powerpc/boot/dts/mpc8540ads.dts |2 --
Added next-level-cache to the L1 and a reference to the new L2 label.
---
In my powerpc-next branch.
arch/powerpc/boot/dts/ksi8560.dts |3 ++-
arch/powerpc/boot/dts/mpc8540ads.dts |3 ++-
arch/powerpc/boot/dts/mpc8541cds.dts |3 ++-
arch/powerpc/boot/dts/mpc8544ds.dts|
Kim Phillips wrote:
On Fri, 30 May 2008 15:19:43 -0500
Scott Wood [EMAIL PROTECTED] wrote:
Kim Phillips wrote:
On Fri, 30 May 2008 14:41:17 -0500
Scott Wood [EMAIL PROTECTED] wrote:
Kim Phillips wrote:
On Fri, 30 May 2008 22:09:04 +0400
Evgeniy Polyakov [EMAIL PROTECTED] wrote:
Don't you
On Fri, 30 May 2008 15:19:43 -0500
Scott Wood [EMAIL PROTECTED] wrote:
Kim Phillips wrote:
On Fri, 30 May 2008 14:41:17 -0500
Scott Wood [EMAIL PROTECTED] wrote:
Kim Phillips wrote:
On Fri, 30 May 2008 22:09:04 +0400
Evgeniy Polyakov [EMAIL PROTECTED] wrote:
Don't you want to
On Fri, 30 May 2008 15:36:50 -0500
Scott Wood [EMAIL PROTECTED] wrote:
Kim Phillips wrote:
On Fri, 30 May 2008 15:19:43 -0500
Scott Wood [EMAIL PROTECTED] wrote:
Kim Phillips wrote:
On Fri, 30 May 2008 14:41:17 -0500
Scott Wood [EMAIL PROTECTED] wrote:
Kim Phillips wrote:
On
On Fri, May 30, 2008 at 03:48:20PM -0500, Kim Phillips ([EMAIL PROTECTED])
wrote:
sorry, by ISR I meant interrupt status registers. but I can't tell
where the suspected simultaneous accesses are. Evgeniy, can you point
out the register accesses you're talking about?
priv-status is accessed
Nice cleanup! Just one thing...
+- compatible : Should contain entries for all compatible SEC
versions,
+ high to low, e.g., fsl,sec2.1, fsl,sec2.0
*All* compatible versions? That's not really correct -- for
example that would include *future* versions!
The first entry should
Removed clock-frequency and big-endian props as they aren't specified
anywhere.
If you remove big-endian, you'll have to provide some other way
to get that information (like, some new compatible value).
Dunno if we need clock-frequency.
This patch also removes built-in properties. I'm all
Added next-level-cache to the L1 and a reference to the new L2 label.
Where is this property defined? I can't find it.
The PowerPC binding defines an l2-cache property for this (it
points from CPU node to L2 cache node, from L2 cache node to L3
cache node, from L3 cache node to L4 cache node,
Kumar Gala wrote:
From: Ashish Kalra [EMAIL PROTECTED]
PMP support for sata_fsl driver.
Signed-off-by: Ashish Kalra [EMAIL PROTECTED]
---
Jeff,
The following commit (4c9bf4e799ce06a7378f1196587084802a414c03):
libata: replace tf_read with qc_fill_rtf for non-SFF drivers
Broke the sata_fsl.c
The node for DMA2 in the MPC8610 HPCD device tree has the wrong compatible
properties. This breaks the DMA driver and the sound driver.
Signed-off-by: Timur Tabi [EMAIL PROTECTED]
---
I have no idea how I let this bug slip in, but this is a must-fix for 2.6.26.
On Sat, 31 May 2008 01:12:08 +0400
Evgeniy Polyakov [EMAIL PROTECTED] wrote:
On Fri, May 30, 2008 at 03:48:20PM -0500, Kim Phillips ([EMAIL PROTECTED])
wrote:
sorry, by ISR I meant interrupt status registers. but I can't tell
where the suspected simultaneous accesses are. Evgeniy, can
Alessandro Zummo wrote:
On Wed, 20 Feb 2008 10:11:23 -0600
Kumar Gala [EMAIL PROTECTED] wrote:
Is the functionality provided by drivers/char/gen_rtc.c completely
handled by the rtc subsystem in drivers/rtc?
I ask for two reasons:
1. should we make it mutually exclusive in Kconfig
2.
Add support for the SEC available on a wide range of PowerQUICC devices,
e.g. MPC8349E, MPC8548E.
this initial version supports authenc(hmac(sha1),cbc(aes)) for use with IPsec.
Signed-off-by: Kim Phillips [EMAIL PROTECTED]
---
removed priv-status hw interrupt status assignment. Done tasklet now
Laurent Pinchart wrote:
This patch adds an MDIO bitbang driver that uses the GPIO library and its
OF bindings to access the bus I/Os.
Signed-off-by: Laurent Pinchart [EMAIL PROTECTED]
---
Documentation/powerpc/booting-without-of.txt | 21 +++
drivers/net/phy/Kconfig |
Kumar Gala writes:
For the additonal exception levels (critical, debug, machine check) on
40x/book-e we were using static allocations of the stack in the
associated head.S.
Move to a runtime allocation to make the code a bit easier to read as
we mimic how we handle IRQ stacks. Its also a
Timur Tabi writes:
The node for DMA2 in the MPC8610 HPCD device tree has the wrong compatible
properties. This breaks the DMA driver and the sound driver.
Signed-off-by: Timur Tabi [EMAIL PROTECTED]
---
I have no idea how I let this bug slip in, but this is a must-fix for 2.6.26.
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