On Tue, 2008-12-09 at 17:46 +1100, Benjamin Herrenschmidt wrote:
> We're soon running out of CPU features and I need to add some new
> ones for various MMU related bits, so this patch separates the MMU
> features from the CPU features. I moved over the 32-bit MMU related
> ones, added base features
This patch moves the whole no-hash TLB handling out of line into a
new tlb_nohash.c file, and implements some basic SMP support using
IPIs and/or broadcast tlbivax instructions.
Signed-off-by: Benjamin Herrenschmidt <[EMAIL PROTECTED]>
---
v2. This variant fixes usage of linux/spinlock.h instead
This makes the MMU context code used for CPUs with no hash table
(except 603) dynamically allocate the various maps used to track
the state of contexts.
Only the main free map and CPU 0 stale map are allocated at boot
time. Other CPU maps are allocated when those CPUs are brought up
and freed if t
This splits the mmu_context handling between 32-bit hash based processors,
64-bit hash based processors and everybody else. This is preliminary work
for adding SMP support for BookE processors.
Signed-off-by: Benjamin Herrenschmidt <[EMAIL PROTECTED]>
---
v2. address various comments for Josh and
On Mon, 2008-12-08 at 19:14 -0800, Trent Piepho wrote:
> On Tue, 2 Dec 2008, Kumar Gala wrote:
> > Added 85xx specifc smp_ops structure. We use ePAPR style boot release
> > and the MPIC for IPIs at this point.
> >
> > Additionally added routines for secondary cpu entry and initializtion.
> >
> > @
On Tue, 2008-12-02 at 01:55 -0600, Kumar Gala wrote:
> Added 85xx specifc smp_ops structure. We use ePAPR style boot release
> and the MPIC for IPIs at this point.
>
> Additionally added routines for secondary cpu entry and initializtion.
For some internal stuff, I did differently.
I have a sep
On 12/8/08 9:57 PM, Stefan Roese wrote:
> On Tuesday 09 December 2008, Grant Erickson wrote:
>>> Just to make sure, are you planning on just implementing a driver to
>>> deal with whatever settings the bootloader configured? E.g., if ECC is
>>> enabled deal with correctable/uncorrectable errors an
On Tuesday 09 December 2008, Sean MacLennan wrote:
> On Thu, 4 Dec 2008 09:01:07 -0500
>
> "Josh Boyer" <[EMAIL PROTECTED]> wrote:
> > In addition to an example DTS patch (probably to warp itself), could
> > you briefly write up a binding and put it in
> > Documentation/powerpc/dts-bindings/amcc (o
This patch moves the whole no-hash TLB handling out of line into a
new tlb_nohash.c file, and implements some basic SMP support using
IPIs and/or broadcast tlbivax instructions.
Signed-off-by: Benjamin Herrenschmidt <[EMAIL PROTECTED]>
---
This variant fixes usage of linux/spinlock.h instead of a
Hi Grant,
On Tuesday 09 December 2008, Grant Erickson wrote:
> > Just to make sure, are you planning on just implementing a driver to
> > deal with whatever settings the bootloader configured? E.g., if ECC is
> > enabled deal with correctable/uncorrectable errors and if not, do
> > nothing? Basi
On Mon, 8 Dec 2008 22:32:27 -0500
"Josh Boyer" <[EMAIL PROTECTED]> wrote:
> Except there is no controller in front of the NOR. It's all just
> MMIOs. With NDFC, there is a controller, you have to do things to it
> to talk to different chips, etc.
Ok, I have the following dts working... would th
Please pull from the 'merge' branch of
git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc.git merge
to get two more small commits for powerpc; one is a very small
defconfig update, and the other fixes a bug that can lead to an oops
on some 440-family embedded powerpc processors.
Thanks
The code that maps kernel low memory would only use page sizes up to 256
MB. On E500v2 pages up to 4 GB are supported.
However, a page must be aligned to a multiple of the page's size. I.e.
256 MB pages must aligned to a 256 MB boundary. This was enforced by a
requirement that the physical and
On booke processors, the code that maps low memory only uses up to three
CAM entries, even though there are sixteen and nothing else uses them.
Make this number configurable in the advanced options menu along with max
low memory size. If one wants 1 GB of lowmem, then it's typically
necessary to
The code to map lowmem uses three CAM aka TLB[1] entries to cover it. The
size of each is stored in three globals named __cam0, __cam1, and __cam2.
All the code that uses them is duplicated three times for each of the three
variables.
We have these things called arrays and loops
Once convert
This is a global variable defined in fsl_booke_mmu.c with a value that gets
initialized in assembly code in head_fsl_booke.S.
It's never used.
If some code ever does want to know the number of entries in TLB1, then
"numcams = mfspr(SPRN_TLB1CFG) & 0xfff", is a whole lot simpler than a
global init
Some assembly code in head_fsl_booke.S hard-coded the size of struct tlbcam
to 20 when it indexed the TLBCAM table. Anyone changing the size of struct
tlbcam would not know to expect that.
The kernel already has a system to get the size of C structures into
assembly language files, asm-offsets, s
On Mon, 8 Dec 2008 21:45:12 -0500
Sean MacLennan <[EMAIL PROTECTED]> wrote:
> On Tue, 9 Dec 2008 05:11:15 +0300
> "Anton Vorontsov" <[EMAIL PROTECTED]> wrote:
>
> > So this is a controller with partitions? ;-)
>
> Actually, I did it this way to mimic the look of the NOR. Really, we
> shouldn't c
On Tue, 2 Dec 2008, Kumar Gala wrote:
> Added 85xx specifc smp_ops structure. We use ePAPR style boot release
> and the MPIC for IPIs at this point.
>
> Additionally added routines for secondary cpu entry and initializtion.
>
> @@ -740,6 +750,9 @@ finish_tlb_load:
> #else
> rlwimi r12, r11,
On Mon, 2008-12-08 at 15:30 -0500, Josh Boyer wrote:
> Can we call this CPU_FTRS_440x6 please? The H really has no relevance
> here from what I understand as both the hard and synthysized x6 cores
> would do the indexed instructions.
I'll change that.
> I'm wondering how much that is worth it.
On Tue, 9 Dec 2008 05:11:15 +0300
"Anton Vorontsov" <[EMAIL PROTECTED]> wrote:
> So this is a controller with partitions? ;-)
Actually, I did it this way to mimic the look of the NOR. Really, we
shouldn't care about the NAND chip.
Here is the complete NOR and NAND DTS:
[EMAIL PROTECTED],0 {
Hi Sean,
On Mon, Dec 08, 2008 at 07:34:46PM -0500, Sean MacLennan wrote:
> On Thu, 4 Dec 2008 09:01:07 -0500
> "Josh Boyer" <[EMAIL PROTECTED]> wrote:
>
> > In addition to an example DTS patch (probably to warp itself), could
> > you briefly write up a binding and put it in
> > Documentation/powe
On Mon, 2008-12-08 at 16:32 -0600, Scott Wood wrote:
> Benjamin Herrenschmidt wrote:
> > Index: linux-work/arch/powerpc/mm/tlb_nohash.c
> > ===
> > --- /dev/null 1970-01-01 00:00:00.0 +
> > +++ linux-work/arch/powerpc
Hello Josh,
If you are still intending to review our ppc440spe ADMA driver
(thanks in advance if so), then please use the driver from my latest
post as the reference:
http://ozlabs.org/pipermail/linuxppc-dev/2008-December/065983.html
since this has some updates relating to the November ver
Ok, I will remove the unused code for now.
Thanks
James
On Mon, 2008-12-08 at 18:35 -0600, Kim Phillips wrote:
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On Thu, 4 Dec 2008 09:01:07 -0500
"Josh Boyer" <[EMAIL PROTECTED]> wrote:
> You also seem to only support a single NAND chip, however the NDFC can
> support multiple chips. Have you looked at how the the fsl_elbc_nand
> driver does multiple chip support? If not, could you at least
> document the
On Tuesday, December 9, 2008 you wrote:
> On Mon, Dec 8, 2008 at 2:55 PM, Yuri Tikhonov <[EMAIL PROTECTED]> wrote:
>> Using src_list argument of async_xor() as a storage for dma addresses
>> implies sizeof(dma_addr_t) <= sizeof(struct page *) restriction which is
>> not always true (e.g. ppc440spe
On Mon, 08 Dec 2008 13:55:07 -0800
James Hsiao <[EMAIL PROTECTED]> wrote:
> >> + /* figure how many gd is needed */
> >> + if (aad_len) {
> >> + num_gd = get_sg_count(assoc, aad_len) +
> >> + get_sg_count(src, datalen);
>
> > this is dead code - aad_len is
On Thu, 4 Dec 2008 09:01:07 -0500
"Josh Boyer" <[EMAIL PROTECTED]> wrote:
> In addition to an example DTS patch (probably to warp itself), could
> you briefly write up a binding and put it in
> Documentation/powerpc/dts-bindings/amcc (or similar)? Also please CC
> the devicetree-discuss list on t
On Mon, Dec 8, 2008 at 2:55 PM, Yuri Tikhonov <[EMAIL PROTECTED]> wrote:
> Using src_list argument of async_xor() as a storage for dma addresses
> implies sizeof(dma_addr_t) <= sizeof(struct page *) restriction which is
> not always true (e.g. ppc440spe).
>
ppc440spe runs with CONFIG_PHYS_64BIT?
On 12/8/08 3:10 PM, Josh Boyer wrote:
> On Mon, 08 Dec 2008 14:08:01 -0800
> Grant Erickson <[EMAIL PROTECTED]> wrote:
>
> Well, at the moment CONFIG_PPC4xx_IBM_DDR2 doesn't exist, and has no
> meaning. Adding a Kconfig option for it just so you can select an ECC
> option seems superfluous. Beca
On Mon, 08 Dec 2008 14:08:01 -0800
Grant Erickson <[EMAIL PROTECTED]> wrote:
> On 12/8/08 12:21 PM, Josh Boyer wrote:
> > On Mon, Dec 08, 2008 at 11:28:15AM -0800, Grant Erickson wrote:
> >> Does anyone have any strong preferences on where configurations,
> >> definitions
> >> and sources for a P
Benjamin Herrenschmidt wrote:
Index: linux-work/arch/powerpc/mm/tlb_nohash.c
===
--- /dev/null 1970-01-01 00:00:00.0 +
+++ linux-work/arch/powerpc/mm/tlb_nohash.c 2008-12-08 16:21:24.0
+1100
[snip]
+#incl
ioctl(SG_IO) with odd dxfer_len hangs the machine. I have a dual G4 MDD and
and ide dvd-rw and I can't locate che bug. I'm posting here because the
program below doesn't crash on a PC. Any clue? TIA.
Linux Jay 2.6.27 #2 SMP Wed Oct 15 00:33:06 CEST 2008 ppc 7455, altivec
supported PowerMac3,6 GNU
ioctl(SG_IO) with odd dxfer_len hangs the machine. I have a dual G4 MDD and
and ide dvd-rw and I can't locate che bug. I'm posting here because the
program below doesn't crash on a PC. Any clue? TIA.
Linux Jay 2.6.27 #2 SMP Wed Oct 15 00:33:06 CEST 2008 ppc 7455, altivec
supported PowerMac3,6 GNU
On 12/8/08 12:21 PM, Josh Boyer wrote:
> On Mon, Dec 08, 2008 at 11:28:15AM -0800, Grant Erickson wrote:
>> Does anyone have any strong preferences on where configurations, definitions
>> and sources for a PPC4xx ECC monitoring and reporting driver should go?
>>
>> Specifically, this concerns ECC
handle_stripe6 function is changed to do things asynchronously.
Signed-off-by: Yuri Tikhonov <[EMAIL PROTECTED]>
Signed-off-by: Ilya Yanok <[EMAIL PROTECTED]>
---
drivers/md/raid5.c | 130
1 files changed, 90 insertions(+), 40 deletions(-)
di
Some clean-up of the replaced or already unnecessary functions.
Signed-off-by: Yuri Tikhonov <[EMAIL PROTECTED]>
Signed-off-by: Ilya Yanok <[EMAIL PROTECTED]>
---
drivers/md/raid5.c | 246
1 files changed, 0 insertions(+), 246 deletions(-)
d
This patch introduces the state machine for handling the RAID-6 parities
check and repair functionality.
Signed-off-by: Yuri Tikhonov <[EMAIL PROTECTED]>
Signed-off-by: Ilya Yanok <[EMAIL PROTECTED]>
---
drivers/md/raid5.c | 163 +++-
1 files chang
Change handle_stripe_fill6 to work asynchronously and introduce helper
fetch_block6 function for this.
Signed-off-by: Yuri Tikhonov <[EMAIL PROTECTED]>
Signed-off-by: Ilya Yanok <[EMAIL PROTECTED]>
---
drivers/md/raid5.c | 154
1 files changed
Rewrite handle_stripe_dirtying6 function to work asynchronously.
Signed-off-by: Yuri Tikhonov <[EMAIL PROTECTED]>
Signed-off-by: Ilya Yanok <[EMAIL PROTECTED]>
---
drivers/md/raid5.c | 113 ++--
1 files changed, 30 insertions(+), 83 deletions(-)
d
To be able to re-use the schedule_reconstruction5() code in RAID-6
case, this should handle Q-parity strip appropriately. This patch
introduces this.
Signed-off-by: Yuri Tikhonov <[EMAIL PROTECTED]>
Signed-off-by: Ilya Yanok <[EMAIL PROTECTED]>
---
drivers/md/raid5.c | 18 ++
1
The raid_run_ops routine uses the asynchronous offload api and
the stripe_operations member of a stripe_head to carry out xor+pqxor+copy
operations asynchronously, outside the lock.
The operations performed by RAID-6 are the same as in the RAID-5 case
except for no support of STRIPE_OP_PREXOR op
This patch extends async_tx API with two operations for recovery
operations on RAID6 array with two failed disks using new async_pq()
operation. Patch introduces the following functions:
async_r6_dd_recov() recovers after double data disk failure
async_r6_dp_recov() recovers after D+P failure
This adds support for doing asynchronous GF multiplication by adding
four additional functions to async_tx API:
async_pq() does simultaneous XOR of sources and XOR of sources
GF-multiplied by given coefficients.
async_pq_zero_sum() checks if results of calculations match given
ones.
async
Using src_list argument of async_xor() as a storage for dma addresses
implies sizeof(dma_addr_t) <= sizeof(struct page *) restriction which is
not always true (e.g. ppc440spe).
Signed-off-by: Ilya Yanok <[EMAIL PROTECTED]>
Signed-off-by: Yuri Tikhonov <[EMAIL PROTECTED]>
---
crypto/async_tx/async
Hello,
This is the next attempt on asynchronous RAID-6 support. This patch-set
has the Dan Williams' comments (Nov, 15) addressed. These were mainly
about the ASYNC_TX part of the code.
The following patch-set includes enhancements to the async_tx api and
modifications to md-raid6 to issue mem
Hi Kim,
>> + /* figure how many gd is needed */
>> + if (aad_len) {
>> + num_gd = get_sg_count(assoc, aad_len) +
>> + get_sg_count(src, datalen);
> this is dead code - aad_len is never non-zero - is there some code
> missing from crypto4xx_alg.c? Also, II
On Mon, 2008-12-08 at 12:14 -0700, Yuri Tikhonov wrote:
> The destination address may be present in the source list, so we should
> map the addresses from the source list first.
> Otherwise, if page corresponding to destination is not marked as write-
> through (with regards to CPU cache), then ma
On Mon, Dec 08, 2008 at 04:40:03PM +1100, Benjamin Herrenschmidt wrote:
>This adds supports to the "extended" DCR addressing via
>the indirect mfdcrx/mtdcrx instructions supported by some
>4xx cores (440H6 and later)
>
>I enabled the feature for now only on AMCC 460 chips
>
>Signed-off-by: Benjamin
On Mon, Dec 08, 2008 at 11:28:15AM -0800, Grant Erickson wrote:
>Does anyone have any strong preferences on where configurations, definitions
>and sources for a PPC4xx ECC monitoring and reporting driver should go?
>
>Specifically, this concerns ECC handling code for the IBM DDR2 ECC
>controller fo
Does anyone have any strong preferences on where configurations, definitions
and sources for a PPC4xx ECC monitoring and reporting driver should go?
Specifically, this concerns ECC handling code for the IBM DDR2 ECC
controller found in the 405EX[r], 440SP, 440SPe, 460EX and 460GT. However,
I'd lik
The destination address may be present in the source list, so we should
map the addresses from the source list first.
Otherwise, if page corresponding to destination is not marked as write-
through (with regards to CPU cache), then mapping it with DMA_FROM_DEVICE
may lead to data loss, and finall
On Fri, 5 Dec 2008 06:41:13 +0100
Stefan Roese <[EMAIL PROTECTED]> wrote:
> On Friday 05 December 2008, Kim Phillips wrote:
> > > diff --git a/arch/powerpc/boot/dts/canyonlands.dts
> > > b/arch/powerpc/boot/dts/canyonlands.dts index 79fe412..b0f0096 100644
> > > --- a/arch/powerpc/boot/dts/canyonl
On Fri, 05 Dec 2008 15:24:11 -0800
James Hsiao <[EMAIL PROTECTED]> wrote:
> Without the check, nbytes could become negative. The aead test case
> with .np will crash(ie. gcm tests), those test have sg->length >
> nbytes.
>
> About aad_len, we didn't release code that use aad yet. We did test thi
On Mon, Dec 08, 2008 at 11:41:03AM +0800, Jason Jin wrote:
> The ECCM maybe set in bootloader, Get ECCM settings from the bootloader,
> can avoid the image written by bootloader cannot read out by kernel.
>
> But the limitation of doing it this way is that, it could break large page
> NAND if it i
On Thu, 2008-12-04 at 06:51 -0700, Gary Thomas wrote:
> I have a MPC5200 based board which has an FPGA for external
> I/O, etc. This FPGA also funnels interrupts from the various
> external devices through to the CPU.
>
> I've defined this structure in my DTS:
>
> [EMAIL PROTECTED] {
>
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