[PATCH 2/2] dts: Update sata controller compatible for p1022ds board
Update p1022 sata compatible to fsl,p1022-sata, fsl,pq-sata-v2.
p1022ds sata controller is v2 version comparing previous FSL sata
controller, for example, mpc8536.
Signed-off-by: Lei Xu b33...@freescale.com
Signed-off-by: Roy Zang tie-fei.z...@freescale.com
---
arch/powerpc/boot/dts/p1022ds.dts |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/boot/dts/p1022ds.dts
b/arch/powerpc/boot/dts/p1022ds.dts
index 2bbecbb..9ad41dd 100644
--- a/arch/powerpc/boot/dts/p1022ds.dts
+++ b/arch/powerpc/boot/dts/p1022ds.dts
@@ -475,14 +475,14 @@
};
sata@18000 {
- compatible = fsl,mpc8536-sata, fsl,pq-sata;
+ compatible = fsl,p1022-sata, fsl,pq-sata-v2;
reg = 0x18000 0x1000;
cell-index = 1;
interrupts = 74 0x2;
};
sata@19000 {
- compatible = fsl,mpc8536-sata, fsl,pq-sata;
+ compatible = fsl,p1022-sata, fsl,pq-sata-v2;
reg = 0x19000 0x1000;
cell-index = 2;
interrupts = 41 0x2;
--
1.7.0.4
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[PATCH 1/2] ATA: Add FSL sata v2 controller support
In FSL sata v2 block, the snoop bit of PRDT Word3 description
information is at bit28 instead of bit22.
This patch adds FSL sata v2 probe and resolve this difference.
Signed-off-by: Lei Xu b33...@freescale.com
Signed-off-by: Roy Zang tie-fei.z...@freescale.com
Acked-by: Jeff Garzik jgar...@redhat.com
---
drivers/ata/sata_fsl.c | 25 ++---
1 files changed, 18 insertions(+), 7 deletions(-)
diff --git a/drivers/ata/sata_fsl.c b/drivers/ata/sata_fsl.c
index b0214d0..01a5400 100644
--- a/drivers/ata/sata_fsl.c
+++ b/drivers/ata/sata_fsl.c
@@ -6,7 +6,7 @@
* Author: Ashish Kalra ashish.ka...@freescale.com
* Li Yang le...@freescale.com
*
- * Copyright (c) 2006-2007 Freescale Semiconductor, Inc.
+ * Copyright (c) 2006-2007, 2011 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
@@ -158,7 +158,8 @@ enum {
IE_ON_SINGL_DEVICE_ERR | IE_ON_CMD_COMPLETE,
EXT_INDIRECT_SEG_PRD_FLAG = (1 31),
- DATA_SNOOP_ENABLE = (1 22),
+ DATA_SNOOP_ENABLE_V1 = (1 22),
+ DATA_SNOOP_ENABLE_V2 = (1 28),
};
/*
@@ -256,6 +257,7 @@ struct sata_fsl_host_priv {
void __iomem *ssr_base;
void __iomem *csr_base;
int irq;
+ int data_snoop;
};
static inline unsigned int sata_fsl_tag(unsigned int tag,
@@ -308,7 +310,8 @@ static void sata_fsl_setup_cmd_hdr_entry(struct
sata_fsl_port_priv *pp,
}
static unsigned int sata_fsl_fill_sg(struct ata_queued_cmd *qc, void *cmd_desc,
-u32 *ttl, dma_addr_t cmd_desc_paddr)
+u32 *ttl, dma_addr_t cmd_desc_paddr,
+int data_snoop)
{
struct scatterlist *sg;
unsigned int num_prde = 0;
@@ -358,8 +361,7 @@ static unsigned int sata_fsl_fill_sg(struct ata_queued_cmd
*qc, void *cmd_desc,
ttl_dwords += sg_len;
prd-dba = cpu_to_le32(sg_addr);
- prd-ddc_and_ext =
- cpu_to_le32(DATA_SNOOP_ENABLE | (sg_len ~0x03));
+ prd-ddc_and_ext = cpu_to_le32(data_snoop | (sg_len ~0x03));
VPRINTK(sg_fill, ttl=%d, dba=0x%x, ddc=0x%x\n,
ttl_dwords, prd-dba, prd-ddc_and_ext);
@@ -374,7 +376,7 @@ static unsigned int sata_fsl_fill_sg(struct ata_queued_cmd
*qc, void *cmd_desc,
/* set indirect extension flag along with indirect ext. size */
prd_ptr_to_indirect_ext-ddc_and_ext =
cpu_to_le32((EXT_INDIRECT_SEG_PRD_FLAG |
-DATA_SNOOP_ENABLE |
+data_snoop |
(indirect_ext_segment_sz ~0x03)));
}
@@ -417,7 +419,8 @@ static void sata_fsl_qc_prep(struct ata_queued_cmd *qc)
if (qc-flags ATA_QCFLAG_DMAMAP)
num_prde = sata_fsl_fill_sg(qc, (void *)cd,
- ttl_dwords, cd_paddr);
+ ttl_dwords, cd_paddr,
+ host_priv-data_snoop);
if (qc-tf.protocol == ATA_PROT_NCQ)
desc_info |= FPDMA_QUEUED_CMD;
@@ -1336,6 +1339,11 @@ static int sata_fsl_probe(struct platform_device *ofdev,
}
host_priv-irq = irq;
+ if (of_device_is_compatible(ofdev-dev.of_node, fsl,pq-sata-v2))
+ host_priv-data_snoop = DATA_SNOOP_ENABLE_V2;
+ else
+ host_priv-data_snoop = DATA_SNOOP_ENABLE_V1;
+
/* allocate host structure */
host = ata_host_alloc_pinfo(ofdev-dev, ppi, SATA_FSL_MAX_PORTS);
@@ -1418,6 +1426,9 @@ static struct of_device_id fsl_sata_match[] = {
{
.compatible = fsl,pq-sata,
},
+ {
+ .compatible = fsl,pq-sata-v2,
+ },
{},
};
--
1.7.0.4
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Re: Problem with Busybox shell
I further debugged and found that flush_to_ldisc() function is not called which actually wakes up the readers. This is a worker function and is not being scheduled. I suspected whether timer interrupts are generated or not. powerpc uses decrementer exceptions as timer interrupts. I see that timer_interrupt() function in arch/powerpc/kernel/time.c is not called at all. I printed even jiffies values and it is not incremented. And I beleivethis makes scheduler is not scheduling this worker thread. I think if flush_to_ldisc is not called nothing can be read from the tty. Please let me know what could be the reason for timer interrupt being not called. Thanks, Mohan On Wed, Jan 19, 2011 at 12:37 AM, tiejun.chen tiejun.c...@windriver.com wrote: MohanReddy koppula wrote: But, if there is any problem with cable I could not have seen any character in the interrupt routine of the driver. I turned off both I suppose the bootloader, i.e u-boot, works well so looks this should not be issued by the cable at least. software and hardware flow control as by board doesn't have hardware flow control. tty_read is called and it hangs at ldisc-read. And I Any panic information? Or any dead lock? Which line in detail? see that data is put into the tty buffer by the driver. Will there be any problem with copy_to_user() if there is some problem in the memory? Can the serial driver support the poll mode? If so maybe you can take a try to exclude any interrupt reason. And even you can remove all codes to initialize the corresponding PIN CLK dedicated to the serial port, then try again since the bootloader already did this. Tiejun Thanks, Mohan On Tue, Jan 18, 2011 at 12:55 PM, Nicholas Mc Guire der.h...@hofr.at wrote: On Tue, 18 Jan 2011, MohanReddy koppula wrote: Hi All, I am working on an MPC885 based custom board. I am able to boot up the linux (linux-2.6.33.7). I could see busybox shell (ash) prompt. But it is not accepting any inputs, I am not able to enter any command, it just hangs there. I am using ttyCPM0 terminal. I suspected if there was any problem in CPM driver interrupts generation and put some printk's in the interrupt handler and could see interrupts are raised and data is read, but shell is not taking the input. I wrote an init.c and opened the ttyCPM0 and tried to read from it, but couldn't. I am able to write to ttyCPM0 and see it on the host minicom. if you are using minicom to connect check if you have hardware/software flow control turned on - it also could be a cabling problem - had this with the beagle board where the tx line was on the wrong pin - so I got output but could not get any response to input. hofrat ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH] powerpc/83xx: fix build failures on dt compatible list.
Commit a4f740cf, of/flattree: Add of_flat_dt_match() helper function
introduced build failures in arch/powerpc/platform/83xx by mistyping
'static' as 'struct' in the compatible string list, and omitting a few
semicolons. This patch fixes it.
Reported-by: Stephen Rothwell s...@canb.auug.org.au
Signed-off-by: Grant Likely grant.lik...@secretlab.ca
---
Ben, I can put this one into my merge-devicetree branch and I'll ask Linus
to merge it in a few days.
arch/powerpc/platforms/83xx/mpc830x_rdb.c |4 ++--
arch/powerpc/platforms/83xx/mpc831x_rdb.c |4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/platforms/83xx/mpc830x_rdb.c
b/arch/powerpc/platforms/83xx/mpc830x_rdb.c
index 661d354..d0c4e15 100644
--- a/arch/powerpc/platforms/83xx/mpc830x_rdb.c
+++ b/arch/powerpc/platforms/83xx/mpc830x_rdb.c
@@ -57,12 +57,12 @@ static void __init mpc830x_rdb_init_IRQ(void)
ipic_set_default_priority();
}
-struct const char *board[] __initdata = {
+static const char *board[] __initdata = {
MPC8308RDB,
fsl,mpc8308rdb,
denx,mpc8308_p1m,
NULL
-}
+};
/*
* Called very early, MMU is off, device-tree isn't unflattened
diff --git a/arch/powerpc/platforms/83xx/mpc831x_rdb.c
b/arch/powerpc/platforms/83xx/mpc831x_rdb.c
index b54cd73..f859ead 100644
--- a/arch/powerpc/platforms/83xx/mpc831x_rdb.c
+++ b/arch/powerpc/platforms/83xx/mpc831x_rdb.c
@@ -60,11 +60,11 @@ static void __init mpc831x_rdb_init_IRQ(void)
ipic_set_default_priority();
}
-struct const char *board[] __initdata = {
+static const char *board[] __initdata = {
MPC8313ERDB,
fsl,mpc8315erdb,
NULL
-}
+};
/*
* Called very early, MMU is off, device-tree isn't unflattened
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Re: [PATCH V7 07/10] USB/ppc4xx: Add Synopsys DWC OTG PCD function
On Tue, 18 Jan 2011 tma...@apm.com wrote:
From: Tirumala Marri tma...@apm.com
The PCD is responsible for translating requests from the gadget driver
to appropriate actions on the DWC OTG controller.
Signed-off-by: Tirumala R Marri tma...@apm.com
Signed-off-by: Fushen Chen fc...@apm.com
Signed-off-by: Mark Miesfeld mmiesf...@apm.com
---
drivers/usb/dwc_otg/dwc_otg_pcd.c | 1752
+
drivers/usb/dwc_otg/dwc_otg_pcd.h | 139 +++
2 files changed, 1891 insertions(+), 0 deletions(-)
diff --git a/drivers/usb/dwc_otg/dwc_otg_pcd.c
b/drivers/usb/dwc_otg/dwc_otg_pcd.c
new file mode 100644
index 000..857dcee
--- /dev/null
+++ b/drivers/usb/dwc_otg/dwc_otg_pcd.c
...
+static struct usb_ep_ops dwc_otg_pcd_ep_ops = {
+ .enable = dwc_otg_pcd_ep_enable,
+ .disable = dwc_otg_pcd_ep_disable,
+ .alloc_request = dwc_otg_pcd_alloc_request,
+ .free_request = dwc_otg_pcd_free_request,
+ .queue = dwc_otg_pcd_ep_queue,
+ .dequeue = dwc_otg_pcd_ep_dequeue,
+ .set_halt = dwc_otg_pcd_ep_set_halt,
+ .fifo_status = NULL,
+ .fifo_flush = NULL,
+};
This is missing a .set_wedge method.
Alan Stern
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Re: [PATCH] define binding for fsl mpic interrupt controllers
On 01/18/2011 01:47 PM, Yoder Stuart-B08248 wrote: I'm not sure a complete merge into one binding makes sense. The thing that motivated creating this new binding with 4 cells was a thread from last year. See: http://lists.ozlabs.org/pipermail/devicetree-discuss/2010-January/001489.html I agree that one binding may not make sense, but perhaps we could have something like: dts-bindings/ |-- mpic.txt |-- fsl |-- mpic.txt where '.../fsl/mpic.txt' only documents the overrides (and maybe refers to '.../mpic.txt' in the intro). For example, the 'interrupt-controller', '#address-cells', and 'reg' properties are really not that different between the two bindings and could be placed just in '.../mpic.txt'. Where as the specific interrupt specifier definition and the overrides for 'compatible' and '#interrupt-cells' could go in .../fsl/mpic.txt'. Since Freescale had the need to represent additional information in interrupt specifiers (error ints, timers, ipis), the suggestion at the end was to add additional cells in a FSL-specific binding. So this really is a Freescale specific thing and does belong in the Freescale binding directory. Agreed. That being said, if there is consensus on the AMP related properties, I should probably incorporate those as well-- protected-sources and no-reset. I'll separately comment on your mpic binding patch. Great, thanks. -- Meador Inge | meador_inge AT mentor.com Mentor Embedded | http://www.mentor.com/embedded-software ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
RE: [PATCH 1/2] powerpc: document the MPIC device tree binding
-Original Message- From: Meador Inge [mailto:meador_i...@mentor.com] Sent: Wednesday, January 19, 2011 2:25 PM To: Yoder Stuart-B08248 Cc: linuxppc-dev@lists.ozlabs.org; devicetree-disc...@lists.ozlabs.org; Blanchard, Hollis Subject: Re: [PATCH 1/2] powerpc: document the MPIC device tree binding On 01/18/2011 02:21 PM, Yoder Stuart-B08248 wrote: Documentation/powerpc/dts-bindings/mpic.txt | 78 This is really the binding for an open-pic interrupt controller and I think the name should reflect that-- open-pic.txt. Yup, agreed. +This binding specifies what properties and child nodes must be +available on the device tree representation of the MPIC interrupt +controller. This binding is based on the binding defined for Open +PIC in [1] and is a superset of that binding. I think it would be better to base this on the ePAPR binding which was based on the original chrp binding. Properties like name and device_type are deprecated not being used in flat device trees. http://www.power.org/resources/downloads/Power_ePAPR_APPROVED_v1.0.pd f The proposed new properties really should go back into the ePAPR. I read portions of ePAPR while writing this binding and considered that. My only worry was that ePAPR is focused on embedded systems and this binding will have to cover non-embedded systems that exist in the kernel. However, perhaps that is not a legitimate concern? The ePAPR tried to codify what was previously implemented in Linux, so I don't think lack of things like name and device_type in the binding are an issue. + +** Required properties: + + NOTE: Many of these descriptions were paraphrased from [1] to aid + readability. + + - name : Specifies the name of the MPIC. Drop this. No DTS files use it. Done. + - device_type : Specifies the device type of this MPIC. The + value of this + property shall be open-pic. device_type is deprecated, since this is not real open-firmware. In practice the kernel is matching on device_type, but we want to move away from that to match on compatible, just hasn't been implemented yet. I will drop this property with the expectation that the kernel will be fixed. From a quick grep of '.../arch/powerpc' it looks like most uses are of the form: np = of_find_node_by_type(NULL, open-pic); if (np == NULL) return; In most of these cases I suppose the 'of_find_node_by_type' calls could just be replaced with calls to 'of_find_compatible_node(NULL, open-pic)'. For backwards compatibility, we should continue to accept the old/deprecated device_type=open-pic, but in addition we should accept the compatible=open-pic. + - reg : Specifies the base physical address(s) and size(s) of this + MPIC's + addressable register space. + - compatible : Specifies the compatibility list for the MPIC. The + property + value shall include chrp,open-pic. In the ePAPR we modified this to just open-pic, because this has nothing to do with chrp anymore. I think just open-pic is what we want. OK, but as a migration path we should allow the kernel to accept both (Scott mentioned this in another reply), but open-pic is the documented correct way. Right. + - interrupt-controller : The presence of this property identifies + the node +as a MPIC. No property value should be defined. + - #address-cells : Specifies the number of cells needed to encode an + address. The value of this property shall always + be 0 + so that 'interrupt-map' nodes do not have to + specify a + parent unit address. + - #interrupt-cells : Specifies the number of cells needed to encode + an +interrupt source. Should be 2, correct? Yup. +** Optional properties: + + - no-reset : The presence of this property indicates that the MPIC +should not be reset during runtime initialization. + - protected-sources : Specifies a list of interrupt sources that are + not + available for use and whose corresponding + vectors + should not be initialized. A typical use case + for + this property is in AMP systems where multiple + independent operating systems need to share + the MPIC + without clobbering each other. I do think you need to include the definition of interrupt specifiers here. Feel free to cut/paste text from my Freescale mpic binding. OK, I will look into that. Thanks. I have a version 2 I hope to send out later today. Stuart ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
RE: [PATCH 1/2] powerpc: document the MPIC device tree binding
+** Optional properties: + + - no-reset : The presence of this property indicates that the MPIC + should not be reset during runtime initialization. + - protected-sources : Specifies a list of interrupt sources that are + not + available for use and whose corresponding + vectors + should not be initialized. A typical use case + for + this property is in AMP systems where multiple + independent operating systems need to share + the MPIC + without clobbering each other. Is protected-sources really needed for AMP systems to tell the OSes not to clobber each other? Won't each OS be given a device tree with only its interrupt sources? ...so you know what you are allowed to touch. Stuart ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: 2.6.37-git17 virtual IO boot failure
On 19.01.2011 [17:06:18 +1100], Benjamin Herrenschmidt wrote: On Tue, 2011-01-18 at 16:48 -0800, Nishanth Aravamudan wrote: Ben, if you're ok with waiting to see if Milton or Sonny have any ideas, I'd like to hold off on asking for a revert. In the case they do, I'll be able to test and send out any proposed fix rapidly. I don't believe this specific error is causing the lockup, I think we only hit a spurrious message on devices that don't have DMA capabilities in the first place. (But I may be wrong, I'll wait for you guys to dig more or I'll have a look myself tomorrow if I manage to get out of meetings). Yes, this seems accurate. Like I mentioned elsewhere, this box came up ok even with these messages and seemed ok (up until the disk locked up). So there's another problem with SCSI tho it -could- also be a DMA issue, hard to tell at this point. Right, I'm not sure how to determine that. I did see the lockup, though, with both my patches reverted (the patches for vio, I mean, after 2.6.37) BTW. I'm not too happy with those defaults set to 64-bit. Probably not an issue until your other patches go in, but some devices like veth cannot do 64-bit DMA. I think we should default to 32-bit in the VIO base code and explicitely enable 64-bit DMA from drivers that support it (in theory vscsi but I haven't verified the implementation). Ok, so change the bit-mask to 32-bit? Or would it be appropriate to attempt 64-bit, if it fails fallback to 32-bit? Seems to be a common pattern throughout the DMA bit-setting callers. Thanks, Nish -- Nishanth Aravamudan n...@us.ibm.com IBM Linux Technology Center ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH][v2] define binding for fsl mpic interrupt controllers
From: Stuart Yoder stuart.yo...@freescale.com define the binding for compatible = fsl,mpic, including the definition of 4-cell interrupt specifiers. The 3rd and 4th cells are needed to define additional types of interrupt source outside the normal external and internal interrupts in FSL SoCs. Define error interrupt, IPIs, and PIC timer sources. Signed-off-by: Stuart Yoder stuart.yo...@freescale.com --- -version 2 -fix some typos -move defintion of interrupt number to the interrupt type 0 -defined no-reset property -added some examples Documentation/powerpc/dts-bindings/fsl/mpic.txt | 251 +++ 1 files changed, 209 insertions(+), 42 deletions(-) diff --git a/Documentation/powerpc/dts-bindings/fsl/mpic.txt b/Documentation/powerpc/dts-bindings/fsl/mpic.txt index 71e39cf..a6160b5 100644 --- a/Documentation/powerpc/dts-bindings/fsl/mpic.txt +++ b/Documentation/powerpc/dts-bindings/fsl/mpic.txt @@ -1,42 +1,209 @@ -* OpenPIC and its interrupt numbers on Freescale's e500/e600 cores - -The OpenPIC specification does not specify which interrupt source has to -become which interrupt number. This is up to the software implementation -of the interrupt controller. The only requirement is that every -interrupt source has to have an unique interrupt number / vector number. -To accomplish this the current implementation assigns the number zero to -the first source, the number one to the second source and so on until -all interrupt sources have their unique number. -Usually the assigned vector number equals the interrupt number mentioned -in the documentation for a given core / CPU. This is however not true -for the e500 cores (MPC85XX CPUs) where the documentation distinguishes -between internal and external interrupt sources and starts counting at -zero for both of them. - -So what to write for external interrupt source X or internal interrupt -source Y into the device tree? Here is an example: - -The memory map for the interrupt controller in the MPC8544[0] shows, -that the first interrupt source starts at 0x5_ (PIC Register Address -Map-Interrupt Source Configuration Registers). This source becomes the -number zero therefore: - External interrupt 0 = interrupt number 0 - External interrupt 1 = interrupt number 1 - External interrupt 2 = interrupt number 2 - ... -Every interrupt number allocates 0x20 bytes register space. So to get -its number it is sufficient to shift the lower 16bits to right by five. -So for the external interrupt 10 we have: - 0x0140 5 = 10 - -After the external sources, the internal sources follow. The in core I2C -controller on the MPC8544 for instance has the internal source number -27. Oo obtain its interrupt number we take the lower 16bits of its memory -address (0x5_0560) and shift it right: - 0x0560 5 = 43 - -Therefore the I2C device node for the MPC8544 CPU has to have the -interrupt number 43 specified in the device tree. - -[0] MPC8544E PowerQUICCTM III, Integrated Host Processor Family Reference Manual -MPC8544ERM Rev. 1 10/2007 += +Freescale MPIC Interrupt Controller Node +Copyright (C) 2010,2011 Freescale Semiconductor Inc. += + +The Freescale MPIC interrupt controller is found on all PowerQUICC +and QorIQ processors and is compatible with the Open PIC. The +notable difference from Open PIC binding is the addition of 2 +additional cells in the interrupt specifier defining interrupt type +information. + +PROPERTIES + + - compatible + Usage: required + Value type: string + Definition: Shall include fsl,mpic. Freescale MPIC + controllers compatible with this binding have Block + Revision Registers BRR1 and BRR2 at offset 0x0 and + 0x10 in the MPIC. + + - reg + Usage: required + Value type: prop-encoded-array + Definition: A standard property. Specifies the physical + offset and length of the device's registers within the + CCSR address space. + + - interrupt-controller + Usage: required + Value type: empty + Definition: Specifies that this node is an interrupt + controller + + - #interrupt-cells + Usage: required + Value type: u32 + Definition: Shall be 2 or 4. A value of 2 means that interrupt + specifiers do not contain the interrupt-type or type-specific + information cells. + + - #address-cells + Usage: required + Value type: u32 + Definition: Shall be 0. + + - no-reset + Usage: optional + Value type: empty + Definition: The presence of this property specifies that the + MPIC must not be reset by the client program, and that + the boot program has initialized all interrupt source + configuration registers to a sane state-- masked or + directed at other cores. This ensures that the client +
[PATCH V8 01/10] USB/ppc4xx: Add Synopsys DWC OTG Register definitions
From: Tirumala Marri tma...@apm.com Add Synopsys Design Ware core register definitions. Signed-off-by: Tirumala R Marri tma...@apm.com Signed-off-by: Fushen Chen fc...@apm.com Signed-off-by: Mark Miesfeld mmiesf...@apm.com --- drivers/usb/dwc_otg/dwc_otg_regs.h | 1325 1 files changed, 1325 insertions(+), 0 deletions(-) diff --git a/drivers/usb/dwc_otg/dwc_otg_regs.h b/drivers/usb/dwc_otg/dwc_otg_regs.h new file mode 100644 index 000..bd53bf6 --- /dev/null +++ b/drivers/usb/dwc_otg/dwc_otg_regs.h @@ -0,0 +1,1325 @@ +/* + * DesignWare HS OTG controller driver + * Copyright (C) 2006 Synopsys, Inc. + * Portions Copyright (C) 2010 Applied Micro Circuits Corporation. + * + * This program is free software: you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License version 2 for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see http://www.gnu.org/licenses + * or write to the Free Software Foundation, Inc., 51 Franklin Street, + * Suite 500, Boston, MA 02110-1335 USA. + * + * Based on Synopsys driver version 2.60a + * Modified by Mark Miesfeld mmiesf...@apm.com + * + * Revamped register difinitions by Tirumala R Marri(tma...@apm.com) + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS AS IS + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL SYNOPSYS, INC. BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES + * (INCLUDING BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __DWC_OTG_REGS_H__ +#define __DWC_OTG_REGS_H__ + +#include linux/types.h + +/* + * This file contains the Macro defintions for accessing the DWC_otg core + * registers. + * + * The application interfaces with the HS OTG core by reading from and + * writing to the Control and Status Register (CSR) space through the + * AHB Slave interface. These registers are 32 bits wide, and the + * addresses are 32-bit-block aligned. + * CSRs are classified as follows: + * - Core Global Registers + * - Device Mode Registers + * - Device Global Registers + * - Device Endpoint Specific Registers + * - Host Mode Registers + * - Host Global Registers + * - Host Port CSRs + * - Host Channel Specific Registers + * + * Only the Core Global registers can be accessed in both Device and + * Host modes. When the HS OTG core is operating in one mode, either + * Device or Host, the application must not access registers from the + * other mode. When the core switches from one mode to another, the + * registers in the new mode of operation must be reprogrammed as they + * would be after a power-on reset. + */ + +/* + * DWC_otg Core registers. The core_global_regs structure defines the + * size and relative field offsets for the Core Global registers. + */ +#defineDWC_GOTGCTL 0x000 +#defineDWC_GOTGINT 0x004 +#defineDWC_GAHBCFG 0x008 +#defineDWC_GUSBCFG 0x00C +#defineDWC_GRSTCTL 0x010 +#defineDWC_GINTSTS 0x014 +#defineDWC_GINTMSK 0x018 +#defineDWC_GRXSTSR 0x01C +#defineDWC_GRXSTSP 0x020 +#defineDWC_GRXFSIZ 0x024 +#defineDWC_GNPTXFSIZ 0x028 +#defineDWC_GNPTXSTS0x02C +#defineDWC_GI2CCTL 0x030 +#defineDWC_VDCTL 0x034 +#defineDWC_GGPIO 0x038 +#defineDWC_GUID0x03C +#defineDWC_GSNPSID 0x040 +#defineDWC_GHWCFG1 0x044 +#defineDWC_GHWCFG2 0x048 +#defineDWC_GHWCFG3 0x04c +#defineDWC_GHWCFG4 0x050 +#defineDWC_HPTXFSIZ0x100 +#defineDWC_DPTX_FSIZ_DIPTXF(x) (0x104 + x * 4) /* 15 = x 1 */ + +#define DWC_GLBINTRMASK0x0001 +#define DWC_DMAENABLE 0x0020 +#define DWC_NPTXEMPTYLVL_EMPTY 0x0080 +#define DWC_NPTXEMPTYLVL_HALFEMPTY 0x +#define DWC_PTXEMPTYLVL_EMPTY
[PATCH V8 02/10] USB/ppc4xx: Add Synopsys DWC OTG driver framework
From: Tirumala Marri tma...@apm.com
Platform probing is in dwc_otg_apmppc.c.
Driver parameter and parameter checking are in dwc_otg_param.c.
Signed-off-by: Tirumala R Marri tma...@apm.com
Signed-off-by: Fushen Chen fc...@apm.com
Signed-off-by: Mark Miesfeld mmiesf...@apm.com
---
drivers/usb/dwc_otg/dwc_otg_apmppc.c | 414 ++
drivers/usb/dwc_otg/dwc_otg_driver.h | 76 ++
drivers/usb/dwc_otg/dwc_otg_param.c | 180 +++
3 files changed, 670 insertions(+), 0 deletions(-)
diff --git a/drivers/usb/dwc_otg/dwc_otg_apmppc.c
b/drivers/usb/dwc_otg/dwc_otg_apmppc.c
new file mode 100644
index 000..d925548
--- /dev/null
+++ b/drivers/usb/dwc_otg/dwc_otg_apmppc.c
@@ -0,0 +1,414 @@
+/*
+ * DesignWare HS OTG controller driver
+ * Copyright (C) 2006 Synopsys, Inc.
+ * Portions Copyright (C) 2010 Applied Micro Circuits Corporation.
+ *
+ * This program is free software: you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License version 2 for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see http://www.gnu.org/licenses
+ * or write to the Free Software Foundation, Inc., 51 Franklin Street,
+ * Suite 500, Boston, MA 02110-1335 USA.
+ *
+ * Based on Synopsys driver version 2.60a
+ * Modified by Mark Miesfeld mmiesf...@apm.com
+ * Modified by Stefan Roese s...@denx.de, DENX Software Engineering
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS AS IS
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL SYNOPSYS, INC. BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/*
+ * The dwc_otg module provides the initialization and cleanup entry
+ * points for the dwcotg driver. This module will be dynamically installed
+ * after Linux is booted using the insmod command. When the module is
+ * installed, the dwc_otg_driver_init function is called. When the module is
+ * removed (using rmmod), the dwc_otg_driver_cleanup function is called.
+ *
+ * This module also defines a data structure for the dwc_otg driver, which is
+ * used in conjunction with the standard device structure. These
+ * structures allow the OTG driver to comply with the standard Linux driver
+ * model in which devices and drivers are registered with a bus driver. This
+ * has the benefit that Linux can expose attributes of the driver and device
+ * in its special sysfs file system. Users can then read or write files in
+ * this file system to perform diagnostics on the driver components or the
+ * device.
+ */
+
+#include linux/of_platform.h
+
+#include dwc_otg_driver.h
+
+#define DWC_DRIVER_VERSION 1.05
+#define DWC_DRIVER_DESCHS OTG USB Controller driver
+static const char dwc_driver_name[] = dwc_otg;
+
+/**
+ * This function is the top level interrupt handler for the Common
+ * (Device and host modes) interrupts.
+ */
+static irqreturn_t dwc_otg_common_irq(int _irq, void *dev)
+{
+ struct dwc_otg_device *dwc_dev = dev;
+ int retval;
+
+ retval = dwc_otg_handle_common_intr(dwc_dev-core_if);
+ return IRQ_RETVAL(retval);
+}
+
+/**
+ * This function is the interrupt handler for the OverCurrent condition
+ * from the external charge pump (if enabled)
+ */
+static irqreturn_t dwc_otg_externalchgpump_irq(int _irq, void *dev)
+{
+ struct dwc_otg_device *dwc_dev = dev;
+
+ if (dwc_otg_is_host_mode(dwc_dev-core_if)) {
+ struct dwc_hcd *dwc_hcd;
+ u32 hprt0 = 0;
+
+ dwc_hcd = dwc_dev-hcd;
+ spin_lock(dwc_hcd-lock);
+ dwc_hcd-flags.b.port_over_current_change = 1;
+
+ hprt0 = DWC_HPRT0_PRT_PWR_RW(hprt0, 0);
+ dwc_write32(dwc_dev-core_if-host_if-hprt0, hprt0);
+ spin_unlock(dwc_hcd-lock);
+ } else {
+ /* Device mode - This int is n/a for device mode */
+ dev_dbg(dev, DeviceMode: OTG OverCurrent Detected\n);
+ }
+
+ return IRQ_HANDLED;
+}
+
+/**
+ * This function is called when a device is
[PATCH V8 05/10] USB/ppc4xx: Add Synopsys DWC OTG HCD interrupt function
From: Tirumala Marri tma...@apm.com
Implements DWC OTG USB HCD interrupt service routine.
Signed-off-by: Tirumala R Marri tma...@apm.com
Signed-off-by: Fushen Chen fc...@apm.com
Signed-off-by: Mark Miesfeld mmiesf...@apm.com
---
drivers/usb/dwc_otg/dwc_otg_hcd_intr.c | 1477
1 files changed, 1477 insertions(+), 0 deletions(-)
diff --git a/drivers/usb/dwc_otg/dwc_otg_hcd_intr.c
b/drivers/usb/dwc_otg/dwc_otg_hcd_intr.c
new file mode 100644
index 000..027635d
--- /dev/null
+++ b/drivers/usb/dwc_otg/dwc_otg_hcd_intr.c
@@ -0,0 +1,1477 @@
+/*
+ * DesignWare HS OTG controller driver
+ * Copyright (C) 2006 Synopsys, Inc.
+ * Portions Copyright (C) 2010 Applied Micro Circuits Corporation.
+ *
+ * This program is free software: you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License version 2 for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see http://www.gnu.org/licenses
+ * or write to the Free Software Foundation, Inc., 51 Franklin Street,
+ * Suite 500, Boston, MA 02110-1335 USA.
+ *
+ * Based on Synopsys driver version 2.60a
+ * Modified by Mark Miesfeld mmiesf...@apm.com
+ * Modified by Stefan Roese s...@denx.de, DENX Software Engineering
+ * Modified by Chuck Meade ch...@theptrgroup.com
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS AS IS
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL SYNOPSYS, INC. BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include dwc_otg_hcd.h
+
+/* This file contains the implementation of the HCD Interrupt handlers.
*/
+static const int erratum_usb09_patched;
+static const int deferral_on = 1;
+static const int nak_deferral_delay = 8;
+static const int nyet_deferral_delay = 1;
+
+/**
+ * Handles the start-of-frame interrupt in host mode. Non-periodic
+ * transactions may be queued to the DWC_otg controller for the current
+ * (micro)frame. Periodic transactions may be queued to the controller for the
+ * next (micro)frame.
+ */
+static int dwc_otg_hcd_handle_sof_intr(struct dwc_hcd *hcd)
+{
+ u32 hfnum = 0;
+ struct list_head *qh_entry;
+ struct dwc_qh *qh;
+ enum dwc_transaction_type tr_type;
+ u32 gintsts = 0;
+
+ hfnum =
+ dwc_read32((u32) hcd-core_if-host_if-host_global_regs +
+ DWC_HFNUM);
+
+ hcd-frame_number = DWC_HFNUM_FRNUM_RD(hfnum);
+
+ /* Determine whether any periodic QHs should be executed. */
+ qh_entry = hcd-periodic_sched_inactive.next;
+ while (qh_entry != hcd-periodic_sched_inactive) {
+ qh = list_entry(qh_entry, struct dwc_qh, qh_list_entry);
+ qh_entry = qh_entry-next;
+
+ /*
+* If needed, move QH to the ready list to be executed next
+* (micro)frame.
+*/
+ if (dwc_frame_num_le(qh-sched_frame, hcd-frame_number))
+ list_move(qh-qh_list_entry,
+ hcd-periodic_sched_ready);
+ }
+
+ tr_type = dwc_otg_hcd_select_transactions(hcd);
+ if (tr_type != DWC_OTG_TRANSACTION_NONE)
+ dwc_otg_hcd_queue_transactions(hcd, tr_type);
+
+ /* Clear interrupt */
+ gintsts |= DWC_INTMSK_STRT_OF_FRM;
+ dwc_write32(gintsts_reg(hcd), gintsts);
+ return 1;
+}
+
+/**
+ * Handles the Rx Status Queue Level Interrupt, which indicates that there is
at
+ * least one packet in the Rx FIFO. The packets are moved from the FIFO to
+ * memory if the DWC_otg controller is operating in Slave mode.
+ */
+static int dwc_otg_hcd_handle_rx_status_q_level_intr(struct dwc_hcd *hcd)
+{
+ u32 grxsts;
+ struct dwc_hc *hc;
+
+ grxsts = dwc_read32((u32) hcd-core_if-core_global_regs + DWC_GRXSTSP);
+ hc = hcd-hc_ptr_array[grxsts DWC_HM_RXSTS_CHAN_NUM_RD(grxsts)];
+
+ /* Packet Status */
+ switch (DWC_HM_RXSTS_PKT_STS_RD(grxsts)) {
+ case DWC_GRXSTS_PKTSTS_IN:
+ /* Read the data into the host
[PATCH V8 06/10] USB/ppc4xx: Add Synopsys DWC OTG HCD queue function
From: Tirumala Marri tma...@apm.com
Implements functions to manage Queue Heads and Queue
Transfer Descriptors of DWC USB OTG Controller.
Signed-off-by: Tirumala R Marri tma...@apm.com
Signed-off-by: Fushen Chen fc...@apm.com
Signed-off-by: Mark Miesfeld mmiesf...@apm.com
---
drivers/usb/dwc_otg/dwc_otg_hcd_queue.c | 696 +++
1 files changed, 696 insertions(+), 0 deletions(-)
diff --git a/drivers/usb/dwc_otg/dwc_otg_hcd_queue.c
b/drivers/usb/dwc_otg/dwc_otg_hcd_queue.c
new file mode 100644
index 000..a083a54
--- /dev/null
+++ b/drivers/usb/dwc_otg/dwc_otg_hcd_queue.c
@@ -0,0 +1,696 @@
+/*
+ * DesignWare HS OTG controller driver
+ * Copyright (C) 2006 Synopsys, Inc.
+ * Portions Copyright (C) 2010 Applied Micro Circuits Corporation.
+ *
+ * This program is free software: you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License version 2 for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see http://www.gnu.org/licenses
+ * or write to the Free Software Foundation, Inc., 51 Franklin Street,
+ * Suite 500, Boston, MA 02110-1335 USA.
+ *
+ * Based on Synopsys driver version 2.60a
+ * Modified by Mark Miesfeld mmiesf...@apm.com
+ * Modified by Stefan Roese s...@denx.de, DENX Software Engineering
+ * Modified by Chuck Meade ch...@theptrgroup.com
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS AS IS
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL SYNOPSYS, INC. BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/*
+ * This file contains the functions to manage Queue Heads and Queue
+ * Transfer Descriptors.
+ */
+
+#include dwc_otg_hcd.h
+
+static inline int is_fs_ls(enum usb_device_speed speed)
+{
+ return speed == USB_SPEED_FULL || speed == USB_SPEED_LOW;
+}
+
+/* Allocates memory for a QH structure. */
+static inline struct dwc_qh *dwc_otg_hcd_qh_alloc(void)
+{
+ return kmalloc(sizeof(struct dwc_qh), GFP_ATOMIC);
+}
+
+/**
+ * Initializes a QH structure to initialize the QH.
+ */
+#define SCHEDULE_SLOP 10
+static void dwc_otg_hcd_qh_init(struct dwc_hcd *hcd, struct dwc_qh *qh,
+ struct urb *urb)
+{
+ memset(qh, 0, sizeof(struct dwc_qh));
+
+ /* Initialize QH */
+ switch (usb_pipetype(urb-pipe)) {
+ case PIPE_CONTROL:
+ qh-ep_type = USB_ENDPOINT_XFER_CONTROL;
+ break;
+ case PIPE_BULK:
+ qh-ep_type = USB_ENDPOINT_XFER_BULK;
+ break;
+ case PIPE_ISOCHRONOUS:
+ qh-ep_type = USB_ENDPOINT_XFER_ISOC;
+ break;
+ case PIPE_INTERRUPT:
+ qh-ep_type = USB_ENDPOINT_XFER_INT;
+ break;
+ }
+
+ qh-ep_is_in = usb_pipein(urb-pipe) ? 1 : 0;
+ qh-data_toggle = DWC_OTG_HC_PID_DATA0;
+ qh-maxp = usb_maxpacket(urb-dev, urb-pipe, !(usb_pipein(urb-pipe)));
+
+ INIT_LIST_HEAD(qh-qtd_list);
+ INIT_LIST_HEAD(qh-qh_list_entry);
+
+ qh-channel = NULL;
+ qh-speed = urb-dev-speed;
+
+ /*
+* FS/LS Enpoint on HS Hub NOT virtual root hub
+*/
+ qh-do_split = 0;
+ if (is_fs_ls(urb-dev-speed) urb-dev-tt urb-dev-tt-hub
+ urb-dev-tt-hub-devnum != 1)
+ qh-do_split = 1;
+
+ if (qh-ep_type == USB_ENDPOINT_XFER_INT ||
+ qh-ep_type == USB_ENDPOINT_XFER_ISOC) {
+ /* Compute scheduling parameters once and save them. */
+ u32 hprt;
+ int bytecount = dwc_hb_mult(qh-maxp) *
+ dwc_max_packet(qh-maxp);
+
+ qh-usecs = NS_TO_US(usb_calc_bus_time(urb-dev-speed,
+ usb_pipein(urb-pipe),
+ (qh-ep_type ==
+ USB_ENDPOINT_XFER_ISOC),
+ bytecount));
+
+ /* Start in a slightly future (micro)frame. */
+
[PATCH V8 07/10] USB/ppc4xx: Add Synopsys DWC OTG PCD function
From: Tirumala Marri tma...@apm.com
The PCD is responsible for translating requests from the gadget driver
to appropriate actions on the DWC OTG controller.
Signed-off-by: Tirumala R Marri tma...@apm.com
Signed-off-by: Fushen Chen fc...@apm.com
Signed-off-by: Mark Miesfeld mmiesf...@apm.com
---
drivers/usb/dwc_otg/dwc_otg_pcd.c | 1766 +
drivers/usb/dwc_otg/dwc_otg_pcd.h | 139 +++
2 files changed, 1905 insertions(+), 0 deletions(-)
diff --git a/drivers/usb/dwc_otg/dwc_otg_pcd.c
b/drivers/usb/dwc_otg/dwc_otg_pcd.c
new file mode 100644
index 000..79c63c4
--- /dev/null
+++ b/drivers/usb/dwc_otg/dwc_otg_pcd.c
@@ -0,0 +1,1766 @@
+/*
+ * DesignWare HS OTG controller driver
+ * Copyright (C) 2006 Synopsys, Inc.
+ * Portions Copyright (C) 2010 Applied Micro Circuits Corporation.
+ *
+ * This program is free software: you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License version 2 for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see http://www.gnu.org/licenses
+ * or write to the Free Software Foundation, Inc., 51 Franklin Street,
+ * Suite 500, Boston, MA 02110-1335 USA.
+ *
+ * Based on Synopsys driver version 2.60a
+ * Modified by Mark Miesfeld mmiesf...@apm.com
+ * Modified by Stefan Roese s...@denx.de, DENX Software Engineering
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS AS IS
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL SYNOPSYS, INC. BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/*
+ * This file implements the Peripheral Controller Driver.
+ *
+ * The Peripheral Controller Driver (PCD) is responsible for
+ * translating requests from the Function Driver into the appropriate
+ * actions on the DWC_otg controller. It isolates the Function Driver
+ * from the specifics of the controller by providing an API to the
+ * Function Driver.
+ *
+ * The Peripheral Controller Driver for Linux will implement the
+ * Gadget API, so that the existing Gadget drivers can be used.
+ * (Gadget Driver is the Linux terminology for a Function Driver.)
+ *
+ * The Linux Gadget API is defined in the header file linux/usb/gadget.h. The
+ * USB EP operations API is defined in the structure usb_ep_ops and the USB
+ * Controller API is defined in the structure usb_gadget_ops
+ *
+ * An important function of the PCD is managing interrupts generated
+ * by the DWC_otg controller. The implementation of the DWC_otg device
+ * mode interrupt service routines is in dwc_otg_pcd_intr.c.
+ */
+
+#include linux/dma-mapping.h
+#include linux/delay.h
+
+#include dwc_otg_pcd.h
+
+/*
+ * Static PCD pointer for use in usb_gadget_register_driver and
+ * usb_gadget_unregister_driver. Initialized in dwc_otg_pcd_init.
+ */
+static struct dwc_pcd *s_pcd;
+
+static inline int need_stop_srp_timer(struct core_if *core_if)
+{
+ if (core_if-core_params-phy_type != DWC_PHY_TYPE_PARAM_FS ||
+ !core_if-core_params-i2c_enable)
+ return core_if-srp_timer_started ? 1 : 0;
+ return 0;
+}
+
+/**
+ * Tests if the module is set to FS or if the PHY_TYPE is FS. If so, then the
+ * gadget should not report as dual-speed capable.
+ */
+static inline int check_is_dual_speed(struct core_if *core_if)
+{
+ if (core_if-core_params-speed == DWC_SPEED_PARAM_FULL ||
+ (DWC_HWCFG2_HS_PHY_TYPE_RD(core_if-hwcfg2) == 2
+DWC_HWCFG2_P_2_P_RD(core_if-hwcfg2) == 1
+core_if-core_params-ulpi_fs_ls))
+ return 0;
+ return 1;
+}
+
+/**
+ * Tests if driver is OTG capable.
+ */
+static inline int check_is_otg(struct core_if *core_if)
+{
+ if (DWC_HWCFG2_OP_MODE_RD(core_if-hwcfg2) ==
+ DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE ||
+ DWC_HWCFG2_OP_MODE_RD(core_if-hwcfg2) ==
+ DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST ||
+ DWC_HWCFG2_OP_MODE_RD(core_if-hwcfg2) ==
+ DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE ||
+ DWC_HWCFG2_OP_MODE_RD(core_if-hwcfg2) ==
+
[PATCH V8 09/10] USB/ppc4xx:Synopsys DWC OTG driver enable gadget support
From: Tirumala Marri tma...@apm.com Enable gadget support Signed-off-by: Tirumala R Marri tma...@apm.com Signed-off-by: Fushen Chen fc...@apm.com Signed-off-by: Mark Miesfeld mmiesf...@apm.com --- drivers/usb/gadget/Kconfig| 22 ++ drivers/usb/gadget/gadget_chips.h |9 + 2 files changed, 31 insertions(+), 0 deletions(-) diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig index 1dc9739..ab7d210 100644 --- a/drivers/usb/gadget/Kconfig +++ b/drivers/usb/gadget/Kconfig @@ -365,6 +365,28 @@ config USB_GADGET_MUSB_HDRC This OTG-capable silicon IP is used in dual designs including the TI DaVinci, OMAP 243x, OMAP 343x, TUSB 6010, and ADI Blackfin +# dwc_otg builds in ../dwc_otg along with host support +config USB_GADGET_DWC_HDRC + boolean DesignWare USB Peripheral + depends on DWC_OTG_MODE || DWC_DEVICE_ONLY + select USB_GADGET_DUALSPEED + select USB_GADGET_SELECTED + select USB_GADGET_DWC_OTG + help + This OTG-capable Designware USB IP + +config USB_GADGET_DWC_OTG + boolean OTG Support + depends on USB_GADGET_DWC_HDRC + help + The most notable feature of USB OTG is support for a + Dual-Role device, which can act as either a device + or a host. The initial role choice can be changed + later, when two dual-role devices talk to each other. + Select this only if your board has a Mini-AB connector. + + + config USB_GADGET_M66592 boolean Renesas M66592 USB Peripheral Controller select USB_GADGET_DUALSPEED diff --git a/drivers/usb/gadget/gadget_chips.h b/drivers/usb/gadget/gadget_chips.h index 5c2720d..7a7623a 100644 --- a/drivers/usb/gadget/gadget_chips.h +++ b/drivers/usb/gadget/gadget_chips.h @@ -142,6 +142,12 @@ #define gadget_is_s3c_hsotg(g)0 #endif +#if defined(CONFIG_DWC_OTG_MODE) || defined(CONFIG_DWC_DEVICE_ONLY) +#define gadget_is_dwc_otg_pcd(g) (!strcmp(dwc_otg_pcd, (g)-name)) +#else +#define gadget_is_dwc_otg_pcd(g) 0 +#endif + #ifdef CONFIG_USB_GADGET_EG20T #definegadget_is_pch(g)(!strcmp(pch_udc, (g)-name)) #else @@ -215,6 +221,9 @@ static inline int usb_gadget_controller_number(struct usb_gadget *gadget) return 0x27; else if (gadget_is_ci13xxx_msm(gadget)) return 0x28; + else if (gadget_is_dwc_otg_pcd(gadget)) + return 0x29; + return -ENOENT; } -- 1.6.1.rc3 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH V8 10/10] USB ppc4xx: Add Synopsys DWC OTG driver kernel configuration and Makefile
From: Tirumala Marri tma...@apm.com Add Synopsys DesignWare HS USB OTG driver kernel configuration. Synopsys OTG driver may operate in host only, device only, or OTG mode. The driver also allows user configure the core to use its internal DMA or Slave (PIO) mode. Signed-off-by: Tirumala R Marri tma...@apm.com Signed-off-by: Fushen Chen fc...@apm.com Signed-off-by: Mark Miesfeld mmiesf...@apm.com --- drivers/Makefile |2 + drivers/usb/Kconfig |3 +- drivers/usb/dwc_otg/Kconfig | 96 ++ drivers/usb/dwc_otg/Makefile | 19 4 files changed, 119 insertions(+), 1 deletions(-) diff --git a/drivers/Makefile b/drivers/Makefile index 2cbb4b7..9a9aa05 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -67,6 +67,7 @@ obj-$(CONFIG_UWB) += uwb/ obj-$(CONFIG_USB_OTG_UTILS)+= usb/otg/ obj-$(CONFIG_USB) += usb/ obj-$(CONFIG_USB_MUSB_HDRC)+= usb/musb/ +obj-$(CONFIG_USB_DWC_OTG) += usb/dwc_otg/ obj-$(CONFIG_PCI) += usb/ obj-$(CONFIG_USB_GADGET) += usb/gadget/ obj-$(CONFIG_SERIO)+= input/serio/ @@ -105,6 +106,7 @@ obj-$(CONFIG_ARCH_SHMOBILE) += sh/ ifndef CONFIG_ARCH_USES_GETTIMEOFFSET obj-y += clocksource/ endif +obj-$(CONFIG_DMA_ENGINE) += dma/ obj-$(CONFIG_DCA) += dca/ obj-$(CONFIG_HID) += hid/ obj-$(CONFIG_PPC_PS3) += ps3/ diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig index fceea5e..fa8b879 100644 --- a/drivers/usb/Kconfig +++ b/drivers/usb/Kconfig @@ -56,7 +56,6 @@ config USB_ARCH_HAS_OHCI config USB_ARCH_HAS_EHCI boolean default y if PPC_83xx - default y if PPC_MPC512x default y if SOC_AU1200 default y if ARCH_IXP4XX default y if ARCH_W90X900 @@ -116,6 +115,8 @@ source drivers/usb/host/Kconfig source drivers/usb/musb/Kconfig +source drivers/usb/dwc_otg/Kconfig + source drivers/usb/class/Kconfig source drivers/usb/storage/Kconfig diff --git a/drivers/usb/dwc_otg/Kconfig b/drivers/usb/dwc_otg/Kconfig new file mode 100644 index 000..4d33d72 --- /dev/null +++ b/drivers/usb/dwc_otg/Kconfig @@ -0,0 +1,96 @@ +# +# USB Dual Role (OTG-ready) Controller Drivers +# for silicon based on Synopsys DesignWare IP +# + +comment Enable Host or Gadget support for DesignWare OTG controller + depends on !USB USB_GADGET=n + +config USB_DWC_OTG + depends on (USB || USB_GADGET) + select NOP_USB_XCEIV + select USB_OTG_UTILS + tristate Synopsys DWC OTG Controller + default USB_GADGET + help + This driver provides USB Device Controller support for the + Synopsys DesignWare USB OTG Core used on the AppliedMicro PowerPC SoC. + +config DWC_DEBUG + bool Enable DWC Debugging + depends on USB_DWC_OTG + default n + help + Enable DWC driver debugging + +choice + prompt DWC Mode Selection + depends on USB_DWC_OTG + default DWC_HOST_ONLY + help + Select the DWC Core in OTG, Host only, or Device only mode. + +config DWC_HOST_ONLY + bool DWC Host Only Mode + +config DWC_OTG_MODE + bool DWC OTG Mode + select USB_GADGET_SELECTED + +config DWC_DEVICE_ONLY + bool DWC Device Only Mode + select USB_GADGET_SELECTED + +endchoice + +# enable peripheral support (including with OTG) +config USB_GADGET_DWC_HDRC + bool + depends on USB_DWC_OTG (DWC_DEVICE_ONLY || USB_DWC_OTG) + +choice + prompt DWC DMA/SlaveMode Selection + depends on USB_DWC_OTG + default DWC_DMA_MODE + help + Select the DWC DMA or Slave Mode. + DMA mode uses the DWC core internal DMA engines. + Slave mode uses the processor PIO to tranfer data. + In Slave mode, processor's DMA channels can be used if available. + +config DWC_SLAVE + bool DWC Slave Mode + +config DWC_DMA_MODE + bool DWC DMA Mode + +endchoice + +config USB_OTG_WHITELIST + bool Rely on OTG Targeted Peripherals List + depends on !USB_SUSPEND USB_DWC_OTG + default n + help + This is the same flag as in ../core/Kconfig. + It is here for easy deselect. + +config DWC_OTG_REG_LE + depends on USB_DWC_OTG + bool DWC Little Endian Register + default y + help + OTG core register access is Little-Endian. + +config DWC_OTG_FIFO_LE + depends on USB_DWC_OTG + bool DWC FIFO Little Endian + default n + help + OTG core FIFO access is Little-Endian. + +config DWC_LIMITED_XFER_SIZE + depends on USB_GADGET_DWC_HDRC + bool DWC Endpoint Limited Xfer Size + default n + help + Bit fields in the Device EP Transfer Size Register is 11 bits. diff --git a/drivers/usb/dwc_otg/Makefile b/drivers/usb/dwc_otg/Makefile new file mode 100644 index 000..31dd5e8 --- /dev/null +++
Re: [PATCH 1/2] powerpc: document the MPIC device tree binding
On 01/19/2011 04:14 PM, Yoder Stuart-B08248 wrote: +** Optional properties: + + - no-reset : The presence of this property indicates that the MPIC +should not be reset during runtime initialization. + - protected-sources : Specifies a list of interrupt sources that are + not + available for use and whose corresponding + vectors + should not be initialized. A typical use case + for + this property is in AMP systems where multiple + independent operating systems need to share + the MPIC + without clobbering each other. Is protected-sources really needed for AMP systems to tell the OSes not to clobber each other? Won't each OS be given a device tree with only its interrupt sources? ...so you know what you are allowed to touch. This was discussed a little bit already [1, 2]. The MPIC driver currently initializes the VECPRI register for all interrupt sources, which can lead to the aforementioned clobbering. -- Meador Inge | meador_inge AT mentor.com Mentor Embedded | http://www.mentor.com/embedded-software [1] http://lists.ozlabs.org/pipermail/devicetree-discuss/2010-December/003850.html [2] http://lists.ozlabs.org/pipermail/devicetree-discuss/2011-January/003936.html ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: Problem with Busybox shell
MohanReddy koppula wrote:
I further debugged and found that flush_to_ldisc() function is not
called which actually wakes up the readers. This is a worker function
and is not being scheduled. I suspected whether timer interrupts are
generated or not. powerpc uses decrementer exceptions as timer
interrupts. I see that timer_interrupt() function in
arch/powerpc/kernel/time.c is not called at all. I printed even
jiffies values and it is not incremented. And I beleivethis makes
scheduler is not scheduling this worker thread.
I think if flush_to_ldisc is not called nothing can be read from the tty.
Please let me know what could be the reason for timer interrupt being
not called.
As you know the decrement exception always is invoked by the TB REGs, unless
there is one higher priority exception to block that.
Here I show the jiffies updating path simply as follows (only one simple path,
actually the timer framework should be more complicated.):
---
DECREMENT Exception
- timer_interrupt
|
+ evt-event_handler(evt);
|
+ tick_handle_periodic()
|
+ tick_periodic(cpu);
Then
--
static void tick_periodic(int cpu)
{
if (tick_do_timer_cpu == cpu) {
write_seqlock(xtime_lock);
/* Keep track of the next tick event */
tick_next_period = ktime_add(tick_next_period, tick_period);
do_timer(1);
write_sequnlock(xtime_lock);
}
update_process_times(user_mode(get_irq_regs()));
profile_tick(CPU_PROFILING);
}
So if we cannot set/update TB we would have no decrement exception. Or the
kernel is locked/looped somewhere.
Can you track the whole process via print? Maybe you can find out something. And
I'm not familiar with 885, is is SMP?
Tiejun
Thanks,
Mohan
On Wed, Jan 19, 2011 at 12:37 AM, tiejun.chen tiejun.c...@windriver.com
wrote:
MohanReddy koppula wrote:
But, if there is any problem with cable I could not have seen any
character in the interrupt routine of the driver. I turned off both
I suppose the bootloader, i.e u-boot, works well so looks this should not be
issued by the cable at least.
software and hardware flow control as by board doesn't have hardware
flow control. tty_read is called and it hangs at ldisc-read. And I
Any panic information? Or any dead lock? Which line in detail?
see that data is put into the tty buffer by the driver. Will there be
any problem with copy_to_user() if there is some problem in the
memory?
Can the serial driver support the poll mode? If so maybe you can take a try
to
exclude any interrupt reason.
And even you can remove all codes to initialize the corresponding PIN CLK
dedicated to the serial port, then try again since the bootloader already
did this.
Tiejun
Thanks,
Mohan
On Tue, Jan 18, 2011 at 12:55 PM, Nicholas Mc Guire der.h...@hofr.at
wrote:
On Tue, 18 Jan 2011, MohanReddy koppula wrote:
Hi All,
I am working on an MPC885 based custom board. I am able to boot up the
linux (linux-2.6.33.7). I could see busybox shell (ash) prompt. But it
is not accepting any inputs, I am not able to enter any command, it
just hangs there. I am using ttyCPM0 terminal.
I suspected if there was any problem in CPM driver interrupts
generation and put some printk's in the interrupt handler and could
see interrupts are raised and data is read, but shell is not taking
the input.
I wrote an init.c and opened the ttyCPM0 and tried to read from it,
but couldn't. I am able to write to ttyCPM0 and see it on the host
minicom.
if you are using minicom to connect check if you have hardware/software
flow
control turned on - it also could be a cabling problem - had this with the
beagle board where the tx line was on the wrong pin - so I got output but
could not get any response to input.
hofrat
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