The e500mc and e5500 based cores are only available on corenet based
SoCs. We use this name for the P204x, P3040, P4040, P4080, P50x0 SoCs
and any future processors in these families.
Signed-off-by: Kumar Gala ga...@kernel.crashing.org
---
arch/powerpc/configs/corenet32_smp_defconfig | 183
Rather than trying to use the core name we use corenet to distinquish
the platform/core combo. corenet64 will be a 64-bit kernel build and
we'll add a new defconfig for corenet32 for a 32-bit platforms.
Signed-off-by: Kumar Gala ga...@kernel.crashing.org
---
Add basic device tree for P5020DS board. This device tree excludes
support for DPAA and RapidIO nodes.
Signed-off-by: Kumar Gala ga...@kernel.crashing.org
---
arch/powerpc/boot/dts/p5020ds.dts | 745 +
1 files changed, 745 insertions(+), 0 deletions(-)
Add basic device tree for P3041DS board. This device tree excludes
support for DPAA and RapidIO nodes.
Signed-off-by: Kumar Gala ga...@kernel.crashing.org
---
arch/powerpc/boot/dts/p3041ds.dts | 752 +
1 files changed, 752 insertions(+), 0 deletions(-)
Several changes on PCIe support on P3041DS/P4080DS/P5020DS boards:
* Add support for fsl,qoriq-pcie-v2.2 needed by P3041 P5020
* Removed support for setting primary_phb_addr as we have no ISA need
* Add PCI controller to of_platform_bus_probe (for EDAC)
* Cleanup building w/SWIOTLB off on P4080DS
* Added BSD dual-license
* Moved mpic-parent to root so we dont need to duplicate everywhere
* Added next level cache from L2 to CPC
* Moved to 4-cell MPIC interrupt properties
* Added 3 MSI banks
* Added numerous missing nodes: soc-sram-error, guts, pins, clockgen,
rcpm, sfp, serdes, etc.
*
We fixup every FSL PCIe Root Complex we need to fixup a few things.
Rather than adding every device under the sun we move to just matching
only on the vendor (PCI_VENDOR_ID_FREESCALE) and than check that we are
a PCIe controller in host mode in the fixup.
Signed-off-by: Kumar Gala
Before if we didn't support or enable HW table walk we'd get a messaage
like:
MMU: Book3E Page Tables Disabled
Which is a bit misleading. Now it will say:
MMU: Book3E HW tablewalk not supported
Signed-off-by: Kumar Gala ga...@kernel.crashing.org
---
arch/powerpc/mm/tlb_nohash.c |4 ++--
From: Scott Wood scottw...@freescale.com
In cases like when the platform is used under hypervisor we will NOT
have an MPIC controller but still want doorbells setup.
Signed-off-by: Scott Wood scottw...@freescale.com
Signed-off-by: Kumar Gala ga...@kernel.crashing.org
---
From: Ashish Kalra ashish.ka...@freescale.com
We expect this is actually faster, and we end up needing more space than we
can get from the SPRGs in some instances. This is also useful when running
as a guest OS - SPRGs4-7 do not have guest versions.
8 slots are allocated in thread_info for this
We need the FSL specific header fixup code on both 32-bit and 64-bit
platforms so just move the code into pci-common.c.
Signed-off-by: Kumar Gala ga...@kernel.crashing.org
---
arch/powerpc/kernel/pci-common.c | 18 ++
arch/powerpc/kernel/pci_32.c | 19 ---
From: Roy Zang tie-fei.z...@freescale.com
The P1023 processor is an e500v2 based SoC that utilizes the DPAA
networking architecture. This adds basic board support for non-DPAA
functionality (device tree, board file, etc).
Signed-off-by: Roy Zang tie-fei.z...@freescale.com
Signed-off-by: Haiying
Signed-off-by: Kumar Gala ga...@kernel.crashing.org
---
arch/powerpc/platforms/85xx/corenet_ds.c |5 +
1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/platforms/85xx/corenet_ds.c
b/arch/powerpc/platforms/85xx/corenet_ds.c
index 10af3c7..338e6dc 100644
---
Only 32-bit SoCs have a QUICC Engine so limit the config option to PPC32.
Signed-off-by: Kumar Gala ga...@kernel.crashing.org
---
arch/powerpc/platforms/Kconfig |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/platforms/Kconfig
This was left as a sysdev, breaking the build
Signed-off-by: Benjamin Herrenschmidt b...@kernel.crashing.org
---
drivers/macintosh/via-pmu.c | 56 +-
1 files changed, 12 insertions(+), 44 deletions(-)
diff --git a/drivers/macintosh/via-pmu.c
commit 9d07bc841c9779b4d7902e417f4e509996ce805d
powerpc: Properly handshake CPUs going out of boot spin loop
Would cause a miscalculation of the hard CPU ID. It removes breaking
out of the loop when finding a match with a processor, thus the i
used as an index in the intserv array is always
Hi Linus
Here's the bulk of powerpc changes for this merge window.
Some of the highlights are:
- Basic support for the new PowerEN processor (Power Edge of Network, I
didn't come up with that name), and known in the linux code by one of
it's former code names wsp (aka Wirespeed Processor).
Hi,
gcc 4.6 with -Werror does not like setting but not using variables
anymore.
So remove it, it does not seem necessary.
Signed-off-by: Marcus Meissner meiss...@suse.de
Ciao, Marcus
---
arch/powerpc/include/asm/pgtable-ppc64.h |8 ++--
1 files changed, 2 insertions(+), 6
On Thu, 19 May 2011 11:05:49 -0500
Timur Tabi ti...@freescale.com wrote:
Alan Cox wrote:
+/* Pass the received data to the tty layer. Note that
this
+ * function calls tty_buffer_request_room(), so I'm not
sure if
+ * we should
Kumar,
Are you planning to release support for dual-port SRIO controller?
If yes, it may be just merged into it (unless dual-port implementation
already has it).
Alex.
-Original Message-
From: linuxppc-dev-bounces+alexandre.bounine=idt@lists.ozlabs.org
[mailto:linuxppc-dev-
Any reason for me not to apply this and send it upstream for now?
- k
On May 20, 2011, at 7:14 AM, Bounine, Alexandre wrote:
Kumar,
Are you planning to release support for dual-port SRIO controller?
If yes, it may be just merged into it (unless dual-port implementation
already has it).
On Thu, May 19, 2011 at 10:52 PM, Benjamin Herrenschmidt
b...@kernel.crashing.org wrote:
Unfortunately, the firmware is also required:
- to configure Blue Gene Interrupt Controller(BIC)
- to configure Torus DMA unit. e.g. fifo
- to configure global interrupt (even we don't use, we need to
On Thu, May 19, 2011 at 02:06:18PM +1000, Benjamin Herrenschmidt wrote:
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc.git merge
When I try to build 'next' (now at 208b3a4c), it does not compile due
to a change from the following commit.
Not at all. I tested it earlier and it works for me on 8548 platform.
-Original Message-
From: Kumar Gala [mailto:ga...@kernel.crashing.org]
Sent: Friday, May 20, 2011 8:42 AM
To: Bounine, Alexandre
Cc: Li Yang-R58472; Xie Shaohui-B21989; Zang Roy-R61911; akpm@linux-
foundation.org;
Hi Alex,
Just for your information as you mentioned about it. The dual port support is
being worked on, but not likely to be ready in this merge window.
- Leo
发件人: Bounine, Alexandre [alexandre.boun...@idt.com]
发送时间: 2011年5月20日 21:18
到: Kumar Gala
Cc:
On Nov 18, 2010, at 12:57 AM, Shaohui Xie wrote:
The sRIO controller reports errors to the core with one signal, it uses
register EPWISR to provides the core quick access to where the error occurred.
The EPWISR indicates that there are 4 interrupts sources, port1, port2,
message
unit and
On Nov 18, 2010, at 12:57 AM, Shaohui Xie wrote:
Signed-off-by: Shaohui Xie b21...@freescale.com
Cc: Li Yang le...@freescale.com
Cc: Kumar Gala kumar.g...@freescale.com
Cc: Roy Zang tie-fei.z...@freescale.com
Cc: Alexandre Bounine alexandre.boun...@idt.com
---
On Fri, May 20, 2011 at 03:23:29PM +0200, Richard Cochran wrote:
When I try to build 'next' (now at 208b3a4c), it does not compile due
to a change from the following commit.
Benjamin Herrenschmidt (1):
powerpc/smp: Make start_secondary_resume available to all CPU variants
I would
On Fri, May 20, 2011 at 09:58:45AM -0400, Josh Boyer wrote:
On Fri, May 20, 2011 at 03:23:29PM +0200, Richard Cochran wrote:
When I try to build 'next' (now at 208b3a4c), it does not compile due
to a change from the following commit.
Benjamin Herrenschmidt (1):
powerpc/smp: Make
A bug/erratum fix, and a 2 long standing SRIO patches...
The following changes since commit 208b3a4c196e733b9cec006dc132cfc149b2810a:
powerpc: Fix hard CPU IDs detection (2011-05-20 17:50:18 +1000)
are available in the git repository at:
On Fri, May 20, 2011 at 04:32:59PM +0200, Richard Cochran wrote:
On Fri, May 20, 2011 at 09:58:45AM -0400, Josh Boyer wrote:
On Fri, May 20, 2011 at 03:23:29PM +0200, Richard Cochran wrote:
When I try to build 'next' (now at 208b3a4c), it does not compile due
to a change from the following
On Fri, May 20, 2011 at 1:09 AM, Kumar Gala ga...@kernel.crashing.org wrote:
+CONFIG_MATH_EMULATION=y
Don't these chips have hardware floating point?
+CONFIG_FORCE_MAX_ZONEORDER=13
This may be unnecessary. I originally set CONFIG_FORCE_MAX_ZONEORDER
to 12 because the DIU driver needs to be
This patch set defines a binding for FSL MPIC message registers and implements
an API for accessing those message registers. Testing was done on a MPC8572DS
in an Linux-Linux AMP setup using OpenMCAPI (www.openmcapi.org) to communicate
between OS instances. The message register API is used by
Some MPIC implementations contain one or more blocks of message registers
that are used to send messages between cores via IPIs. A simple API has
been added to access (get/put, read, write, etc ...) these message registers.
The available message registers are initially discovered via nodes in the
Signed-off-by: Scott Wood scottw...@freescale.com
---
arch/powerpc/kernel/exceptions-64e.S | 22 +-
1 files changed, 21 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/kernel/exceptions-64e.S
b/arch/powerpc/kernel/exceptions-64e.S
index b60f49e..87ca569 100644
---
On Fri, 20 May 2011 01:09:22 -0500
Kumar Gala ga...@kernel.crashing.org wrote:
* Added BSD dual-license
* Moved mpic-parent to root so we dont need to duplicate everywhere
* Added next level cache from L2 to CPC
* Moved to 4-cell MPIC interrupt properties
* Added 3 MSI banks
* Added
On May 20, 2011, at 2:04 PM, Scott Wood wrote:
On Fri, 20 May 2011 01:09:22 -0500
Kumar Gala ga...@kernel.crashing.org wrote:
* Added BSD dual-license
* Moved mpic-parent to root so we dont need to duplicate everywhere
* Added next level cache from L2 to CPC
* Moved to 4-cell MPIC
Kumar Gala wrote:
This may be unnecessary. I originally set CONFIG_FORCE_MAX_ZONEORDER
to 12 because the DIU driver needs to be able to allocate a contiguous
5MB memory block. Setting it to 13 means a max of 16MB. Is there a
reason the default isn't good enough?
Is there some concern
On Fri, 20 May 2011 14:25:23 -0500
Timur Tabi ti...@freescale.com wrote:
Kumar Gala wrote:
This may be unnecessary. I originally set CONFIG_FORCE_MAX_ZONEORDER
to 12 because the DIU driver needs to be able to allocate a contiguous
5MB memory block. Setting it to 13 means a max of
On May 20, 2011, at 2:00 PM, Scott Wood wrote:
In general we will not have EE soft-disabled or be napping when
these exceptions happen, but still it is not correct.
The guest doorbell exceptions can only be triggered with MSR[GS]=1,
and thus for host kernel nesting purposes are base-level
On Fri, 20 May 2011 14:36:09 -0500
Kumar Gala ga...@kernel.crashing.org wrote:
On May 20, 2011, at 2:00 PM, Scott Wood wrote:
In general we will not have EE soft-disabled or be napping when
these exceptions happen, but still it is not correct.
The guest doorbell exceptions can only
The e500mc and e5500 based cores are only available on corenet based
SoCs. We use this name for the P204x, P3040, P4040, P4080, P50x0 SoCs
and any future processors in these families.
Signed-off-by: Kumar Gala ga...@kernel.crashing.org
---
* Removed MATH_EMU
* Added KEXEC
On May 20, 2011, at 9:46 AM, Josh Boyer wrote:
On Fri, May 20, 2011 at 04:32:59PM +0200, Richard Cochran wrote:
On Fri, May 20, 2011 at 09:58:45AM -0400, Josh Boyer wrote:
On Fri, May 20, 2011 at 03:23:29PM +0200, Richard Cochran wrote:
When I try to build 'next' (now at 208b3a4c), it does
Commit 69e3cea8d5fd526 introduced start_secondary_resume to misc_32.S,
however it uses a 64-bit instruction which is not valid on 32-bit
platforms. Use 'stw' instead.
Reported-by: Richard Cochran richardcoch...@gmail.com
Tested-by: Richard Cochran richardcoch...@gmail.com
Signed-off-by: Josh
On 05/20/2011 12:13 PM, Marcus Meissner wrote:
Hi,
gcc 4.6 with -Werror does not like setting but not using variables
anymore.
So remove it, it does not seem necessary.
Signed-off-by: Marcus Meissner meiss...@suse.de
Ciao, Marcus
---
arch/powerpc/include/asm/pgtable-ppc64.h |8
On May 19, 2011, at 8:54 AM, Timur Tabi wrote:
have hypervisor extensions (e.g. the P4080 which has an e500mc core).
I think it makes sense for this patchset to go through Kumar Gala's -next
branch, but I still need ACKs from various people on the parts that are
not e500-specific.
1.
On Thu, 19 May 2011 07:33:55 +1000
Benjamin Herrenschmidt b...@kernel.crashing.org wrote:
On Wed, 2011-05-18 at 16:05 -0500, Scott Wood wrote:
Loads with non-linear access patterns were producing a very high
ratio of recursive pt faults to regular tlb misses. Rather than
choose between a
When using 64K pages with a separate cpio rootfs, U-Boot will align the rootfs
on a 4K
page boundary. When the memory is reserved, and subsequent early memblock_alloc
is called, it will allocate memory between the 64K page alignment and reserved
memory. When the reserved memory is subsequently
On Fri, May 20, 2011 at 04:22:25PM -0400, Josh Boyer wrote:
Commit 69e3cea8d5fd526 introduced start_secondary_resume to misc_32.S,
however it uses a 64-bit instruction which is not valid on 32-bit
platforms. Use 'stw' instead.
Reported-by: Richard Cochran richardcoch...@gmail.com
On Fri, 2011-05-20 at 15:57 -0500, Scott Wood wrote:
I see a 2% cost going from virtual pmd to full 4-level walk in the
benchmark mentioned above (some type of sort), and just under 3% in
page-stride lat_mem_rd from lmbench.
OTOH, the virtual pmd approach still leaves the possibility of
On Fri, 2011-05-20 at 08:01 -0500, Eric Van Hensbergen wrote:
On Thu, May 19, 2011 at 10:52 PM, Benjamin Herrenschmidt
b...@kernel.crashing.org wrote:
Unfortunately, the firmware is also required:
- to configure Blue Gene Interrupt Controller(BIC)
- to configure Torus DMA unit. e.g. fifo
On Fri, 2011-05-20 at 14:58 -0700, Greg KH wrote:
On Fri, May 20, 2011 at 04:22:25PM -0400, Josh Boyer wrote:
Commit 69e3cea8d5fd526 introduced start_secondary_resume to misc_32.S,
however it uses a 64-bit instruction which is not valid on 32-bit
platforms. Use 'stw' instead.
On Fri, 2011-05-20 at 15:26 -0600, Dave Carroll wrote:
When using 64K pages with a separate cpio rootfs, U-Boot will align the
rootfs on a 4K
page boundary. When the memory is reserved, and subsequent early
memblock_alloc
is called, it will allocate memory between the 64K page alignment and
On Fri, 2011-05-20 at 14:00 -0500, Scott Wood wrote:
In general we will not have EE soft-disabled or be napping when
these exceptions happen, but still it is not correct.
The guest doorbell exceptions can only be triggered with MSR[GS]=1,
and thus for host kernel nesting purposes are
On Fri, 2011-05-20 at 14:00 -0500, Scott Wood wrote:
Signed-off-by: Scott Wood scottw...@freescale.com
---
arch/powerpc/kernel/exceptions-64e.S | 22 +-
1 files changed, 21 insertions(+), 1 deletions(-)
You can probably remove the doorbell re-check when enabling
On Fri, 2011-05-20 at 15:23 +0200, Richard Cochran wrote:
On Thu, May 19, 2011 at 02:06:18PM +1000, Benjamin Herrenschmidt wrote:
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc.git merge
When I try to build 'next' (now at 208b3a4c),
When using 64K pages with a separate cpio rootfs, U-Boot will align the rootfs
on a 4K page boundary. When the memory is reserved, and subsequent early
memblock_alloc is called, it will allocate memory between the 64K page alignment
and reserved memory. When the reserved memory is subsequently
On Fri, May 20, 2011 at 5:58 PM, Greg KH g...@kroah.com wrote:
On Fri, May 20, 2011 at 04:22:25PM -0400, Josh Boyer wrote:
Commit 69e3cea8d5fd526 introduced start_secondary_resume to misc_32.S,
however it uses a 64-bit instruction which is not valid on 32-bit
platforms. Use 'stw' instead.
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