On Fri, Aug 26, 2011 at 03:05:52PM +0530, K.Prasad wrote:
On Wed, Aug 24, 2011 at 01:59:39PM +1000, David Gibson wrote:
On Tue, Aug 23, 2011 at 02:55:13PM +0530, K.Prasad wrote:
On Tue, Aug 23, 2011 at 03:08:50PM +1000, David Gibson wrote:
On Fri, Aug 19, 2011 at 01:21:36PM +0530,
Hi all,
we're using your driver for espi controller on P1015 freescale micro.
We're testing an issue trying to do multiple operation into a single
chip select window.
We've noted that the driver disables and enables the ESPI_SPMODE[EN] bit
in order to change the ESPI_SPMODE x register; probably
Hi,
We are porting Linux on MPC7410 based board. As there was some issue with
the processor DECrementer and timebase registers, we were using an external
count down timer as our DECementer. We used timer_interrupt() function in
arch/powerpc/kernel/time.c as our interrupt handler. Things were
From: Shengzhou Liu shengzhou@freescale.com
The P3060QDS is a Freescale reference board that hosts the six-core P3060 SOC.
The P3060 Processor combines six e500mc Power Architecture processor cores with
high-performance datapath acceleration architecture(DPAA), CoreNet fabric
infrastructure,
From: Stephen George stephen.geo...@freescale.com
Adding new device tree binding file for the DCSR node. Modifying device
tree dtsi files to add DCSR node for P2041, P3041, P3060, P4080, P5020.
Signed-off-by: Stephen George stephen.geo...@freescale.com
Signed-off-by: Kumar Gala
From: Laurentiu Tudor laurentiu.tu...@freescale.com
e500mc and e5500 share some eary setup code that need r5 to point to the
cpu spec structure. setup_cpu_e500mc() sets it but setup_cpu_e5500()
didn't.
This caused a crash on 32 bit e5500 running under hypervisor, when
__setup_e500mc_ivors()
For those MMUs that have some form of bolt'd linear mapping (TLB)
required its rare that one ever sets mem= smaller than the size of that
mapping.
However, on Book-E 64 parts the initial linear mapping is quite large
(1G) so its quite reasonable that mem= is set smaller than that.
We need to
On FSL Book-E devices we support multiple large TLB sizes and so we can
get into situations in which the initial 1G TLB size is too big and
we're asked for a size that is not mappable by a single entry (like
512M). The single entry is important because when we bring up secondary
cores they need
On 09/16/2011 06:43 AM, Vineeth wrote:
Hi,
We are porting Linux on MPC7410 based board. As there was some issue
with the processor DECrementer and timebase registers,
What was the issue? You really should try to make this work rather than
hack around it.
lately we moved to Linux 3.0.3.
On 09/16/2011 10:37 AM, Kumar Gala wrote:
From: Laurentiu Tudor laurentiu.tu...@freescale.com
e500mc and e5500 share some eary setup code that need r5 to point to the
cpu spec structure. setup_cpu_e500mc() sets it but setup_cpu_e5500()
didn't.
This caused a crash on 32 bit e5500 running
Sorry for the late reply,
On Thu, 01 Sep 2011 15:35:11 +1000
Benjamin Herrenschmidt b...@kernel.crashing.org wrote:
On Wed, 2011-06-29 at 17:19 +0900, FUJITA Tomonori wrote:
On Fri, 24 Jun 2011 12:05:23 -0700
Nishanth Aravamudan n...@us.ibm.com wrote:
From: Milton Miller
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