On Jan 17, 2012 7:17 PM, Benjamin Herrenschmidt b...@kernel.crashing.org
wrote:
On Tue, 2012-01-17 at 17:28 -0700, Grant Likely wrote:
BTW: Ben, if you can carve out some time, I'd appreciate a look over
my series and make sure you're okay with it. Once it's had some
testing by arm and
From: Fanzc b32...@freeescale.com
Signed-off-by: Fanzc b32...@freeescale.com
---
arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 24
1 files changed, 24 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
From: Fanzc b32...@freeescale.com
P1025RDB Overview
--
1Gbyte DDR3 SDRAM
32 Mbyte NAND flash
16Mbyte NOR flash
16 Mbyte SPI flash
SD connector to interface with the SD memory card
Real-time clock on I2C bus
PCIe:
- x1 PCIe slot
- x1 mini-PCIe slot
10/100/1000 BaseT Ethernet
On 17.1.2012 18:20, Stephen Warren wrote:
Michal Marek wrote at Saturday, January 14, 2012 3:51 PM:
As the C6X port has been merged in this merge window, I can't easily
apply this patch to my kbuild branch and at the same time please Linus
by basing the pull request on a tagged release. So I'm
On 01/17/12 23:09, Scott Wood wrote:
...
If CPU is stuck in sleep, JTAG will send HRESET or SRESET (i'm nor sure
which one it is) and u-boot is needed to reconfigure CPU and DDR2 SDRAM
ctrl.
Why is a reset needed in order to examine physical memory?
Because CPU is stuck in sleep and I
Hi Matthias,
On Tue, 17 Jan 2012 15:12:50 +0100
Matthias Fuchs matthias.fu...@esd.eu wrote:
On 06.01.2012 19:03, Alan Stern wrote:
On Fri, 6 Jan 2012, Matthias Fuchs wrote:
For my eyes it does not really look like a general USB issue.
It looks like a problem with the Freescale EHCI
Hi Anatolij,
On 18.01.2012 12:08, Anatolij Gustschin wrote:
Hi Matthias,
On Tue, 17 Jan 2012 15:12:50 +0100
Matthias Fuchs matthias.fu...@esd.eu wrote:
On 06.01.2012 19:03, Alan Stern wrote:
On Fri, 6 Jan 2012, Matthias Fuchs wrote:
For my eyes it does not really look like a general
On Jan 17, 2012, at 11:50 PM, Ramneek Mehresh wrote:
Enable USB2 controller node for P1020RDB. USB2 controller is used only
when board boots from SPI or SD as it is muxed with eLBC
Signed-off-by: Ramneek Mehresh ramneek.mehr...@freescale.com
---
Applies on
On Jan 18, 2012, at 12:48 AM, Ramneek Mehresh wrote:
Add usb2 controller node for P1020RDB, P2020RDB, P2020DS, P1021MDS
Signed-off-by: Ramneek Mehresh ramneek.mehr...@freescale.com
---
Applies on git://git.kernel.org/pub/scm/linux/kernel/git/galak/powerpc.git
(branch next)
Ben,
Dropped the P1020RDB device tree patch as it was for the wrong board
revision and pulled in some additional usb device tree fixes.
- k
The following changes since commit c2bc3a316a7281f67e36b34dac2802cbe36a9128:
Merge branch 'x86/rdrand' of
This patch adds a menuconfig option that allows controlling
the lazy interrupt disabling feature implemented by this
commit:
commit d04c56f73c30a5e593202ecfcf25ed43d42363a2
Author: Paul Mackerras
Date: Wed Oct 4 16:47:49 2006 +1000
[POWERPC] Lazy interrupt disabling for 64-bit machines
The registers that describe size supported by TLB are different on MMU
v2 as well as we support power of two page sizes. For now we continue
to assume that FSL variable size array supports all page sizes up to the
maximum one reported in TLB1PS.
Signed-off-by: Kumar Gala
Add basic support for e6500 core in its single threaded mode.
Signed-off-by: Kumar Gala ga...@kernel.crashing.org
---
arch/powerpc/include/asm/cputable.h | 12
arch/powerpc/kernel/cputable.c | 18 ++
2 files changed, 26 insertions(+), 4 deletions(-)
diff
On Wed, 2012-01-18 at 16:35 +0200, Laurentiu Tudor wrote:
This patch adds a menuconfig option that allows controlling
the lazy interrupt disabling feature implemented by this
commit:
commit d04c56f73c30a5e593202ecfcf25ed43d42363a2
Author: Paul Mackerras
Date: Wed Oct 4 16:47:49 2006
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