-Original Message-
From: Wood Scott-B07421
Sent: Wednesday, April 03, 2013 12:49 AM
To: Leekha Shaveta-B20052
Cc: linuxppc-dev@lists.ozlabs.org; Zhao Chenhui-B35336; Lian Minghuan-B31939;
Leekha Shaveta-B20052; Garg Vakul-B16394; Tang Yuantian-B29983; Fleming
Andy-AFLEMING; Mehresh Ram
> -Original Message-
> From: Wood Scott-B07421
> Sent: Wednesday, April 03, 2013 8:35 AM
> To: Wang Dongsheng-B40534
> Cc: Wood Scott-B07421; Johannes Berg; linuxppc-dev@lists.ozlabs.org
> Subject: Re: [PATCH] powerpc: add Book E support to 64-bit hibernation
>
> On 04/02/2013 12:28:40 A
> -Original Message-
> From: Joerg Roedel [mailto:j...@8bytes.org]
> Sent: Tuesday, April 02, 2013 8:40 PM
> To: Sethi Varun-B16395
> Cc: Yoder Stuart-B08248; Wood Scott-B07421; iommu@lists.linux-
> foundation.org; linuxppc-dev@lists.ozlabs.org; linux-
> ker...@vger.kernel.org; ga...@kern
Kumar/Ben,
Any comments?
(Had checked with Ben (on IRC) sometime back, he was fine with this patch)
Regards
Varun
> -Original Message-
> From: Joerg Roedel [mailto:j...@8bytes.org]
> Sent: Tuesday, April 02, 2013 8:39 PM
> To: Sethi Varun-B16395
> Cc: Yoder Stuart-B08248; Wood Scott-B07
> -Original Message-
> From: Wood Scott-B07421
> Sent: Wednesday, April 03, 2013 7:23 AM
> To: Timur Tabi
> Cc: Joerg Roedel; Sethi Varun-B16395; lkml; Kumar Gala; Yoder Stuart-
> B08248; io...@lists.linux-foundation.org; Benjamin Herrenschmidt;
> linuxppc-dev@lists.ozlabs.org
> Subject:
On 04/02/2013 11:10 PM, Benjamin Herrenschmidt wrote:
On Tue, 2013-04-02 at 19:26 +0800, Yuanquan Chen wrote:
So we move the DMA & IRQ initialization code from pcibios_setup_devices() and
construct a new function pcibios_enable_device. We call this function in
pcibios_enable_device, which will b
> -Original Message-
> From: Wood Scott-B07421
> Sent: Wednesday, April 03, 2013 8:37 AM
> To: Wang Dongsheng-B40534
> Cc: linuxppc-dev@lists.ozlabs.org; Wang Dongsheng-B40534
> Subject: Re: [PATCH v2 1/4] powerpc/mpic: add irq_set_wake support
>
> On 04/02/2013 01:40:37 AM, Wang Dongshe
The MPIC version 2.0 has a MSI errata (errata PIC1 of mpc8544), It causes
that neither MSI nor MSI-X can work fine. This is a workaround to allow
MSI-X to function properly.
Signed-off-by: Liu Shuo
Signed-off-by: Li Yang
Signed-off-by: Jia Hongtao
---
Changes for V2:
* change the name of functi
MPIC version is useful information for both mpic_alloc() and mpic_init().
The patch provide an API to get MPIC version for reusing the code.
Also, some other IP block may need MPIC version for their own use.
The API for external use is also provided.
Signed-off-by: Jia Hongtao
Signed-off-by: Li Y
On 04/02/2013 08:35:54 PM, Timur Tabi wrote:
On Tue, Apr 2, 2013 at 11:18 AM, Joerg Roedel wrote:
> > + panic("\n");
>
> A kernel panic seems like an over-reaction to an access violation.
We have no way to determining what code caused the violation, so we
can't just kill the process. I ag
On Tue, Apr 2, 2013 at 11:18 AM, Joerg Roedel wrote:
> > + panic("\n");
>
> A kernel panic seems like an over-reaction to an access violation.
We have no way to determining what code caused the violation, so we
can't just kill the process. I agree it seems like overkill, but what
else shoul
On 04/02/2013 01:40:37 AM, Wang Dongsheng wrote:
Add irq_set_wake support. Just add IRQF_NO_SUSPEND to
desc->action->flag.
So the wake up interrupt will not be disable in suspend_device_irqs.
Signed-off-by: Wang Dongsheng
---
v2:
* Add: Check freescale chip in mpic_irq_set_wake().
* Remove: S
On 04/02/2013 12:28:40 AM, Wang Dongsheng-B40534 wrote:
Hi scott & Johannes,
Thanks for reviewing.
@scott, About this patch, could you please help ack this patch?
Please investigate the issue of whether we are loading kernel module
code in this step, and whether cache flushing is needed as
From: Michael Neuling
We are currently out of free bits in AT_HWCAP. With POWER8, we have
several hardware features that we need to advertise. Tested on POWER and
x86.
Signed-off-by: Michael Neuling
Signed-off-by: Nishanth Aravamudan
diff --git a/arch/powerpc/include/asm/cputable.h
b/arch/po
On Tue, 2 Apr 2013 12:44:34 +0530
wrote:
threading seems broken between patches 1 & 2...
> +crypto: crypto@30 {
> + compatible = "fsl,sec-v5.3", "fsl,sec-v5.0", "fsl,sec-v4.0";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + reg = <0x30 0x1>;
> +
On 04/02/2013 04:28:10 AM, Jia Hongtao-B38951 wrote:
> -Original Message-
> From: Wood Scott-B07421
> Sent: Saturday, March 30, 2013 12:34 AM
> To: Jia Hongtao-B38951
> Cc: Wood Scott-B07421; David Laight; linuxppc-dev@lists.ozlabs.org;
> Stuart Yoder
> Subject: Re: [PATCH V4] powerpc/8
On 04/02/2013 02:16:05 AM, Shaveta Leekha wrote:
+/ {
+ compatible = "fsl,B4860";
+
+ cpus {
+ cpu1: PowerPC,e6500@1 {
+ device_type = "cpu";
+ reg = <2 3>;
+ next-level-cache = <&L2>;
+ };
+
On Apr 2, 2013, at 12:49 PM, Scott Wood wrote:
> On 04/02/2013 01:35:05 AM, Jia Hongtao-B38951 wrote:
>> > -Original Message-
>> > From: Wood Scott-B07421
>> > Sent: Saturday, March 30, 2013 5:55 AM
>> > To: Jia Hongtao-B38951
>> > Cc: linuxppc-dev@lists.ozlabs.org; ga...@kernel.crashing.
> -Original Message-
> From: Joerg Roedel [mailto:j...@8bytes.org]
> Sent: Tuesday, April 02, 2013 9:53 PM
> To: Sethi Varun-B16395
> Cc: Yoder Stuart-B08248; Wood Scott-B07421; iommu@lists.linux-
> foundation.org; linuxppc-dev@lists.ozlabs.org; linux-
> ker...@vger.kernel.org; ga...@kern
On 04/02/2013 01:35:05 AM, Jia Hongtao-B38951 wrote:
> -Original Message-
> From: Wood Scott-B07421
> Sent: Saturday, March 30, 2013 5:55 AM
> To: Jia Hongtao-B38951
> Cc: linuxppc-dev@lists.ozlabs.org; ga...@kernel.crashing.org; Wood
Scott-
> B07421; Li Yang-R58472; Jia Hongtao-B389
On Fri, Mar 29, 2013 at 01:23:57AM +0530, Varun Sethi wrote:
> This patchset provides the Freescale PAMU (Peripheral Access Management Unit)
> driver
> and the corresponding IOMMU API implementation. PAMU is the IOMMU present on
> Freescale
> QorIQ platforms. PAMU can authorize memory access, rem
Cc'ing Alex Williamson
Alex, can you please review the iommu-group part of this patch?
My comments so far are below:
On Fri, Mar 29, 2013 at 01:24:02AM +0530, Varun Sethi wrote:
> +config FSL_PAMU
> + bool "Freescale IOMMU support"
> + depends on PPC_E500MC
> + select IOMMU_API
> +
> -Original Message-
> From: Sethi Varun-B16395
> Sent: Thursday, March 28, 2013 2:54 PM
> To: j...@8bytes.org; Yoder Stuart-B08248; Wood Scott-B07421;
> io...@lists.linux-foundation.org; linuxppc-
> d...@lists.ozlabs.org; linux-ker...@vger.kernel.org;
> ga...@kernel.crashing.org; b...@k
SECTIONS
{
/* Read-only sections, merged into text segment: */
PROVIDE (__executable_start = 0xf200); . = 0xf200 +
SIZEOF_HEADERS;
.interp : { *(.interp) } :text :interp
}
So I'm wondering...is this something wrong with our linker script,
or is there a bug in our binutils? I'm no linker
On Tue, 2013-04-02 at 19:26 +0800, Yuanquan Chen wrote:
> So we move the DMA & IRQ initialization code from pcibios_setup_devices() and
> construct a new function pcibios_enable_device. We call this function in
> pcibios_enable_device, which will be called by PCI-e rescan code. At the
> meanwhile,
On Fri, Mar 29, 2013 at 01:24:01AM +0530, Varun Sethi wrote:
> +/* cache stash targets */
> +enum stash_target {
> + IOMMU_ATTR_CACHE_L1 = 1,
> + IOMMU_ATTR_CACHE_L2,
> + IOMMU_ATTR_CACHE_L3,
> +};
> +
> +/* This attribute corresponds to IOMMUs capable of generating
> + * a stash transa
On Fri, Mar 29, 2013 at 01:23:59AM +0530, Varun Sethi wrote:
> Add an iommu domain pointer to device (powerpc) archdata. Devices
> are attached to iommu domains and this pointer provides a mechanism
> to correlate between a device and the associated iommu domain. This
> field is set when a device
lockdep thinks that it might deadlock because it grabs a lock of the
same class while calling the generic_irq_handler(). This annotation will
inform lockdep that it will not.
Signed-off-by: Sebastian Andrzej Siewior
---
arch/powerpc/sysdev/fsl_msi.c |4 +++-
1 files changed, 3 insertions(+),
Tested on MPC5125 Tower evaluation board with
mpc512x_defconfig compile configuration.
In detail, supports for:
- PSC / UART
- RTC
- ETH
- DIU
- I2C
Signed-off-by: Matteo Facchinetti
---
v2:
* change mpc512x_select_psc_compat() implementation
and fix it using const char* return
* drop de
Powerpc initializes the DMA and IRQ information in pci_scan_child_bus()->
pcibios_fixup_bus()->pcibios_setup_bus_devices(). But for the devices
which are hotpluged, bus->is added has been set for the first scan of the
PCI-e bus, so the initialization code won't be called. Then the hotpluged
devices
On Tue, 02 Apr 2013 11:49:22 +0200
Matteo Facchinetti wrote:
...
> > if (of_machine_is_compatible("fsl,mpc5121"))
> > return "fsl,mpc5121-psc";
> >
> > if (of_machine_is_compatible("fsl,mpc5125"))
> > return "fsl,mpc5125-psc";
> >
> > but note th
On 03/30/2013 11:32 PM, Anatolij Gustschin wrote:
+{
+ char *psc_compats[] = {
+ "fsl,mpc5121-psc",
+ "fsl,mpc5125-psc"
+ };
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(psc_compats); i++)
+ if (of_find_compatible_node(NULL, NULL, psc_c
> -Original Message-
> From: Wood Scott-B07421
> Sent: Saturday, March 30, 2013 12:34 AM
> To: Jia Hongtao-B38951
> Cc: Wood Scott-B07421; David Laight; linuxppc-dev@lists.ozlabs.org;
> Stuart Yoder
> Subject: Re: [PATCH V4] powerpc/85xx: Add machine check handler to fix
> PCIe erratum on
The driver provides a way to wake up the system by the MPIC timer.
For example,
echo 5 > /sys/devices/system/mpic/timer_wakeup
echo standby > /sys/power/state
After 5 seconds the MPIC timer will generate an interrupt to wake up
the system.
Signed-off-by: Wang Dongsheng
Signed-off-by: Zhao Chenh
Register a mpic subsystem at /sys/devices/system/
Signed-off-by: Wang Dongsheng
---
arch/powerpc/include/asm/mpic.h | 2 ++
arch/powerpc/sysdev/mpic.c | 8
2 files changed, 10 insertions(+)
diff --git a/arch/powerpc/include/asm/mpic.h b/arch/powerpc/include/asm/mpic.h
index c0f9ef
The MPIC global timer is a hardware timer inside the Freescale PIC complying
with OpenPIC standard. When the specified interval times out, the hardware
timer generates an interrupt. The driver currently is only tested on fsl chip,
but it can potentially support other global timers complying to Open
Add irq_set_wake support. Just add IRQF_NO_SUSPEND to desc->action->flag.
So the wake up interrupt will not be disable in suspend_device_irqs.
Signed-off-by: Wang Dongsheng
---
v2:
* Add: Check freescale chip in mpic_irq_set_wake().
* Remove: Support mpic_irq_set_wake() in ht_chip.
arch/powerpc
B4860 and B4420 are similar that share some commonalities
* common features have been added in b4si-pre.dtsi and b4si-post.dtsi
* differences are added in respective silicon files of B4860 and B4420
There are several things missing from the device trees of B4860 and B4420:
* DPAA related nodes (
Signed-off-by: Shaveta Leekha
---
arch/powerpc/configs/corenet64_smp_defconfig |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/configs/corenet64_smp_defconfig
b/arch/powerpc/configs/corenet64_smp_defconfig
index 1c6eb66..6c8b020 100644
--- a/arch/powerpc/con
B4860QDS and B4420QDS share same QDS board
* common board features have been added in b4qds.dts
* various board differences are in respective files of B4860 and B4420
Signed-off-by: Shaveta Leekha
Signed-off-by: Minghuan Lian
Signed-off-by: Andy Fleming
Signed-off-by: Poonam Aggrwal
Signed-of
- Add support for B4 board in board file b4_qds.c,
It is common for B4860, B4420 and B4220QDS as they share same QDS board
- Add B4QDS support in Kconfig and Makefile
B4860QDS is a high-performance computing evaluation, development and
test platform supporting the B4860 QorIQ Power Architecture
From: Shaveta Leekha
Signed-off-by: Vakul Garg
Signed-off-by: Shaveta Leekha
---
arch/powerpc/boot/dts/fsl/qoriq-sec5.3-0.dtsi | 118 +
1 files changed, 118 insertions(+), 0 deletions(-)
create mode 100644 arch/powerpc/boot/dts/fsl/qoriq-sec5.3-0.dtsi
diff --git a/ar
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