RE: [v1][KVM][PATCH 1/1] kvm:ppc:booehv: direct ISI exception to Guest

2013-05-08 Thread Caraman Mihai Claudiu-B02008
-Original Message- From: kvm-ow...@vger.kernel.org [mailto:kvm-ow...@vger.kernel.org] On Behalf Of tiejun.chen Sent: Wednesday, May 08, 2013 4:54 AM To: Wood Scott-B07421 Cc: ag...@suse.de; kvm-...@vger.kernel.org; k...@vger.kernel.org; linuxppc-dev@lists.ozlabs.org Subject: Re:

Re: [v1][KVM][PATCH 1/1] kvm:ppc:booehv: direct ISI exception to Guest

2013-05-08 Thread tiejun.chen
On 05/08/2013 05:20 PM, Caraman Mihai Claudiu-B02008 wrote: -Original Message- From: kvm-ow...@vger.kernel.org [mailto:kvm-ow...@vger.kernel.org] On Behalf Of tiejun.chen Sent: Wednesday, May 08, 2013 4:54 AM To: Wood Scott-B07421 Cc: ag...@suse.de; kvm-...@vger.kernel.org;

Re: [PATCH] powerpc: fix numa distance for form0 device tree

2013-05-08 Thread Luis Henriques
On Tue, May 07, 2013 at 01:49:34PM +1000, Michael Ellerman wrote: From: Vaidyanathan Srinivasan sva...@linux.vnet.ibm.com Commit 7122b7bc1757682049780179d7c216dd1c83 upstream. Thanks, I'm queuing it for the 3.5 kernel. Cheers, -- Luis ___

Re: ppc/sata-fsl: orphan config value: CONFIG_MPC8315_DS

2013-05-08 Thread Anthony Foiani
Anthony Foiani t...@scrye.com writes: Maybe I need to call ata_set_sata_spd as well. Can I do that before discovery, or should it be a part of the port_start callback? And if the latter, shouldn't it be handled within the ata core, instead of expecting each host driver to do that call? My

RE: [RFC][KVM][PATCH 1/1] kvm:ppc:booke-64: soft-disable interrupts

2013-05-08 Thread Caraman Mihai Claudiu-B02008
This only disable soft interrupt for kvmppc_restart_interrupt() that restarts interrupts if they were meant for the host: a. SOFT_DISABLE_INTS() only for BOOKE_INTERRUPT_EXTERNAL | BOOKE_INTERRUPT_DECREMENTER | BOOKE_INTERRUPT_DOORBELL Those aren't the only exceptions that can end up

[PATCH] rapidio/tsi721: fix bug in MSI interrupt handling

2013-05-08 Thread Alexandre Bounine
Fix bug in MSI interrupt handling which causes loss of event notifications. Typical indication of lost MSI interrupts are stalled message and doorbell transfers between RapidIO endpoints. To avoid loss of MSI interrupts all interrupts from the device must be disabled on entering the interrupt

[PATCH v5, part4 31/41] mm/ppc: prepare for removing num_physpages and simplify mem_init()

2013-05-08 Thread Jiang Liu
Prepare for removing num_physpages and simplify mem_init(). Signed-off-by: Jiang Liu jiang@huawei.com Cc: Benjamin Herrenschmidt b...@kernel.crashing.org Cc: Paul Mackerras pau...@samba.org Cc: linuxppc-dev@lists.ozlabs.org Cc: linux-ker...@vger.kernel.org --- arch/powerpc/mm/mem.c | 56

Re: Invalid perf_branch_entry.to entries question

2013-05-08 Thread Peter Zijlstra
On Tue, May 07, 2013 at 11:35:28AM +1000, Michael Neuling wrote: Peter Stephane, We are plumbing the POWER8 Branch History Rolling Buffer (BHRB) into struct perf_branch_entry. Sometimes on POWER8 we may not be able to fill out the to address. Just because I'm curious.. however does

Re: [v1][KVM][PATCH 1/1] kvm:ppc:booehv: direct ISI exception to Guest

2013-05-08 Thread Scott Wood
On 05/07/2013 08:53:50 PM, tiejun.chen wrote: On 05/08/2013 07:40 AM, Scott Wood wrote: On 05/07/2013 06:06:30 AM, Tiejun Chen wrote: We also can direct ISI exception to Guest like DSI. Signed-off-by: Tiejun Chen tiejun.c...@windriver.com --- arch/powerpc/kvm/booke_emulate.c |3 +++

Re: Invalid perf_branch_entry.to entries question

2013-05-08 Thread Stephane Eranian
On Wed, May 8, 2013 at 5:59 PM, Peter Zijlstra pet...@infradead.org wrote: On Tue, May 07, 2013 at 11:35:28AM +1000, Michael Neuling wrote: Peter Stephane, We are plumbing the POWER8 Branch History Rolling Buffer (BHRB) into struct perf_branch_entry. Sometimes on POWER8 we may not be able

Re: Invalid perf_branch_entry.to entries question

2013-05-08 Thread Michael Neuling
Peter Zijlstra pet...@infradead.org wrote: On Tue, May 07, 2013 at 11:35:28AM +1000, Michael Neuling wrote: Peter Stephane, We are plumbing the POWER8 Branch History Rolling Buffer (BHRB) into struct perf_branch_entry. Sometimes on POWER8 we may not be able to fill out the to

Re: Invalid perf_branch_entry.to entries question

2013-05-08 Thread Michael Neuling
Stephane Eranian eran...@google.com wrote: On Wed, May 8, 2013 at 5:59 PM, Peter Zijlstra pet...@infradead.org wrote: On Tue, May 07, 2013 at 11:35:28AM +1000, Michael Neuling wrote: Peter Stephane, We are plumbing the POWER8 Branch History Rolling Buffer (BHRB) into struct

Re: Invalid perf_branch_entry.to entries question

2013-05-08 Thread Michael Ellerman
On Thu, 2013-05-09 at 08:45 +1000, Michael Neuling wrote: Stephane Eranian eran...@google.com wrote: On Wed, May 8, 2013 at 5:59 PM, Peter Zijlstra pet...@infradead.org wrote: On Tue, May 07, 2013 at 11:35:28AM +1000, Michael Neuling wrote: Peter Stephane, We are plumbing the

Re: [PATCH] powerpc: fix numa distance for form0 device tree

2013-05-08 Thread Michael Ellerman
On Wed, 2013-05-08 at 11:29 +0100, Luis Henriques wrote: On Tue, May 07, 2013 at 01:49:34PM +1000, Michael Ellerman wrote: From: Vaidyanathan Srinivasan sva...@linux.vnet.ibm.com Commit 7122b7bc1757682049780179d7c216dd1c83 upstream. Thanks, I'm queuing it for the 3.5 kernel.

[PATCH] powerpc: Update currituck pci/usb fixup for new board revision

2013-05-08 Thread Alistair Popple
The currituck board uses a different IRQ for the pci usb host controller depending on the board revision. This patch adds support for newer board revisions by retrieving the board revision from the FPGA and mapping the appropriate IRQ. Signed-off-by: Alistair Popple alist...@popple.id.au ---

Re: [PATCH] powerpc: Update currituck pci/usb fixup for new board revision

2013-05-08 Thread Alistair Popple
The currituck board uses a different IRQ for the pci usb host controller depending on the board revision. This patch adds support for newer board revisions by retrieving the board revision from the FPGA and mapping the appropriate IRQ. Signed-off-by: Alistair Popple alist...@popple.id.au ---

[PATCH 1/2] powerpc/pmu: Fix order of interpreting BHRB target entries

2013-05-08 Thread Michael Neuling
The current Branch History Rolling Buffer (BHRB) code misinterprets the order of entries in the hardware buffer. It assumes that a branch target address will be read _after_ its corresponding branch. In reality the branch target comes before (lower mfbhrb entry) it's corresponding branch. This

[PATCH 2/2] powerpc/perf: Fix setting of to addresses for BHRB

2013-05-08 Thread Michael Neuling
Currently we only set the to address in the branch stack when the CPU explicitly gives us a value. Unfortunately it only does this for XL form branches (eg blr, bctr, bctar) and not I and B form branches (eg b, bc). Fortunately if we read the instruction from memory we can extract the offset of