[PATCH 1/5] powerpc/dts: add MPIC v4.3 dts node
For the latest platform T4 and B4, MPIC controller has been updated
to v4.3. This patch adds a new file to describe the latest MPIC.
The MSI blocks number is increased to four, the registers number
of each block is increased to sixteen. MSIIR1 has been added to
access these sixteen MSI registers.
Signed-off-by: Minghuan Lian minghuan.l...@freescale.com
---
arch/powerpc/boot/dts/fsl/b4si-post.dtsi | 2 +-
arch/powerpc/boot/dts/fsl/qoriq-mpic4.3.dtsi | 153 +++
arch/powerpc/boot/dts/fsl/t4240si-post.dtsi | 2 +-
3 files changed, 155 insertions(+), 2 deletions(-)
create mode 100644 arch/powerpc/boot/dts/fsl/qoriq-mpic4.3.dtsi
diff --git a/arch/powerpc/boot/dts/fsl/b4si-post.dtsi
b/arch/powerpc/boot/dts/fsl/b4si-post.dtsi
index 7399154..4c617bf 100644
--- a/arch/powerpc/boot/dts/fsl/b4si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/b4si-post.dtsi
@@ -204,7 +204,7 @@
};
};
-/include/ qoriq-mpic.dtsi
+/include/ qoriq-mpic4.3.dtsi
guts: global-utilities@e {
compatible = fsl,b4-device-config;
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-mpic4.3.dtsi
b/arch/powerpc/boot/dts/fsl/qoriq-mpic4.3.dtsi
new file mode 100644
index 000..e2665b8
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/qoriq-mpic4.3.dtsi
@@ -0,0 +1,153 @@
+/*
+ * QorIQ MPIC device tree stub [ controller @ offset 0x4 ]
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License (GPL) as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+mpic: pic@4 {
+ interrupt-controller;
+ #address-cells = 0;
+ #interrupt-cells = 4;
+ reg = 0x4 0x4;
+ compatible = fsl,mpic;
+ device_type = open-pic;
+ clock-frequency = 0x0;
+};
+
+timer@41100 {
+ compatible = fsl,mpic-global-timer;
+ reg = 0x41100 0x100 0x41300 4;
+ interrupts = 0 0 3 0
+ 1 0 3 0
+ 2 0 3 0
+ 3 0 3 0;
+};
+
+msi0: msi@41600 {
+ compatible = fsl,mpic-msi, fsl,mpic-msi-v4.3;
+ reg = 0x41600 0x200 0x44148 4;
+ msi-available-ranges = 0 0x200;
+ interrupts =
+ 0xe0 0 0 0
+ 0xe1 0 0 0
+ 0xe2 0 0 0
+ 0xe3 0 0 0
+ 0xe4 0 0 0
+ 0xe5 0 0 0
+ 0xe6 0 0 0
+ 0xe7 0 0 0
+ 0x100 0 0 0
+ 0x101 0 0 0
+ 0x102 0 0 0
+ 0x103 0 0 0
+ 0x104 0 0 0
+ 0x105 0 0 0
+ 0x106 0 0 0
+ 0x107 0 0 0;
+};
+
+msi1: msi@41800 {
+ compatible = fsl,mpic-msi, fsl,mpic-msi-v4.3;
+ reg = 0x41800 0x200 0x45148 4;
+ msi-available-ranges = 0 0x200;
+ interrupts =
+ 0xe8 0 0 0
+ 0xe9 0 0 0
+ 0xea 0 0 0
+ 0xeb 0 0 0
+ 0xec 0 0 0
+ 0xed 0 0 0
+ 0xee 0 0 0
+ 0xef 0 0 0
+ 0x108 0 0 0
+ 0x109 0 0 0
+ 0x10a 0 0 0
+ 0x10b 0 0 0
+ 0x10c 0 0 0
+ 0x10d 0 0 0
+ 0x10e 0 0 0
+ 0x10f 0 0 0;
+};
+
+msi2: msi@41a00 {
+ compatible = fsl,mpic-msi,
[PATCH 2/5] powerpc/fsl_msi: add MSIIR1 support for MPIC v4.3
MPIC controller v4.3 provides MSIIR1 to index 16 MSI registers.
MSIIR can only index 8 MSI registers. MSIIR1 uses different bits
definition than MSIIR. This patch adds ibs_shift and srs_shift to
indicate the bits definition of the MSIIR and MSIIR1, so the same
code can handle the MSIIR and MSIIR1 simultaneously.
Signed-off-by: Minghuan Lian minghuan.l...@freescale.com
---
arch/powerpc/sysdev/fsl_msi.c | 62 ++-
arch/powerpc/sysdev/fsl_msi.h | 4 ++-
2 files changed, 53 insertions(+), 13 deletions(-)
diff --git a/arch/powerpc/sysdev/fsl_msi.c b/arch/powerpc/sysdev/fsl_msi.c
index ab02db3..34510b7 100644
--- a/arch/powerpc/sysdev/fsl_msi.c
+++ b/arch/powerpc/sysdev/fsl_msi.c
@@ -28,6 +28,18 @@
#include fsl_msi.h
#include fsl_pci.h
+#define MSIIR_OFFSET_MASK 0xf
+#define MSIIR_IBS_SHIFT0
+#define MSIIR_SRS_SHIFT5
+#define MSIIR1_IBS_SHIFT 4
+#define MSIIR1_SRS_SHIFT 0
+#define MSI_SRS_MASK 0xf
+#define MSI_IBS_MASK 0x1f
+
+#define msi_hwirq(msi, msir_index, intr_index) \
+ ((msir_index) (msi)-srs_shift | \
+((intr_index) (msi)-ibs_shift))
+
static LIST_HEAD(msi_head);
struct fsl_msi_feature {
@@ -80,18 +92,19 @@ static const struct irq_domain_ops fsl_msi_host_ops = {
static int fsl_msi_init_allocator(struct fsl_msi *msi_data)
{
- int rc;
+ int rc, hwirq;
rc = msi_bitmap_alloc(msi_data-bitmap, NR_MSI_IRQS,
msi_data-irqhost-of_node);
if (rc)
return rc;
- rc = msi_bitmap_reserve_dt_hwirqs(msi_data-bitmap);
- if (rc 0) {
- msi_bitmap_free(msi_data-bitmap);
- return rc;
- }
+ /*
+* Reserve all the hwirqs
+* The available hwirqs will be released in fsl_msi_setup_hwirq()
+*/
+ for (hwirq = 0; hwirq NR_MSI_IRQS; hwirq++)
+ msi_bitmap_reserve_hwirq(msi_data-bitmap, hwirq);
return 0;
}
@@ -144,8 +157,9 @@ static void fsl_compose_msi_msg(struct pci_dev *pdev, int
hwirq,
msg-data = hwirq;
- pr_debug(%s: allocated srs: %d, ibs: %d\n,
- __func__, hwirq / IRQS_PER_MSI_REG, hwirq % IRQS_PER_MSI_REG);
+ pr_debug(%s: allocated srs: %d, ibs: %d\n, __func__,
+(hwirq msi_data-srs_shift) MSI_SRS_MASK,
+(hwirq msi_data-ibs_shift) MSI_IBS_MASK);
}
static int fsl_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
@@ -285,8 +299,8 @@ static void fsl_msi_cascade(unsigned int irq, struct
irq_desc *desc)
intr_index = ffs(msir_value) - 1;
cascade_irq = irq_linear_revmap(msi_data-irqhost,
- msir_index * IRQS_PER_MSI_REG +
- intr_index + have_shift);
+ msi_hwirq(msi_data, msir_index,
+ intr_index + have_shift));
if (cascade_irq != NO_IRQ)
generic_handle_irq(cascade_irq);
have_shift += intr_index + 1;
@@ -339,7 +353,7 @@ static int fsl_msi_setup_hwirq(struct fsl_msi *msi, struct
platform_device *dev,
int offset, int irq_index)
{
struct fsl_msi_cascade_data *cascade_data = NULL;
- int virt_msir;
+ int virt_msir, i;
virt_msir = irq_of_parse_and_map(dev-dev.of_node, irq_index);
if (virt_msir == NO_IRQ) {
@@ -360,6 +374,11 @@ static int fsl_msi_setup_hwirq(struct fsl_msi *msi, struct
platform_device *dev,
irq_set_handler_data(virt_msir, cascade_data);
irq_set_chained_handler(virt_msir, fsl_msi_cascade);
+ /* Release the hwirqs corresponding to this MSI register */
+ for (i = 0; i IRQS_PER_MSI_REG; i++)
+ msi_bitmap_free_hwirqs(msi-bitmap,
+ msi_hwirq(msi, offset, i), 1);
+
return 0;
}
@@ -368,7 +387,7 @@ static int fsl_of_msi_probe(struct platform_device *dev)
{
const struct of_device_id *match;
struct fsl_msi *msi;
- struct resource res;
+ struct resource res, msiir;
int err, i, j, irq_index, count;
int rc;
const u32 *p;
@@ -421,10 +440,29 @@ static int fsl_of_msi_probe(struct platform_device *dev)
}
msi-msiir_offset =
features-msiir_offset + (res.start 0xf);
+
+ /*
+* First read the MSIIR/MSIIR1 offset from dts
+* If failure use the hardcode MSIIR offset
+*/
+ if (of_address_to_resource(dev-dev.of_node, 1, msiir))
+ msi-msiir_offset = features-msiir_offset +
+ (res.start MSIIR_OFFSET_MASK);
+ else
+ msi-msiir_offset = msiir.start
[PATCH 3/5] powerpc/dts: update MSI bindings doc for MPIC v4.3
Add compatible fsl,mpic-msi-v4.3 for MPIC v4.3. MPIC v4.3 contains
MSIIR and MSIIR1. MSIIR supports 8 MSI registers and MSIIR1 supports
16 MSI registers, but uses different IBS and SRS shift. When using
MSIR1, the interrupt number is not consecutive. It is hard to use
'msi-available-ranges' to describe the ranges of the available
interrupt and the ranges are related to the application, rather than
the description of the hardware. this patch also removes
'msi-available-ranges' property.
Signed-off-by: Minghuan Lian minghuan.l...@freescale.com
---
.../devicetree/bindings/powerpc/fsl/msi-pic.txt| 49 ++
1 file changed, 22 insertions(+), 27 deletions(-)
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt
b/Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt
index 5693877..e851e93 100644
--- a/Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt
+++ b/Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt
@@ -1,26 +1,23 @@
* Freescale MSI interrupt controller
Required properties:
-- compatible : compatible list, contains 2 entries,
+- compatible : compatible list, may contains one or two entries,
first is fsl,CHIP-msi, where CHIP is the processor(mpc8610, mpc8572,
- etc.) and the second is fsl,mpic-msi or fsl,ipic-msi depending on
- the parent type.
+ etc.) and the second is fsl,mpic-msi or fsl,ipic-msi or
+ fsl,mpic-msi-v4.3 depending on the parent type and version. If mpic
+ version is 4.3, the number of MSI registers is increased to 16, MSIIR1 is
+ provided to access these 16 registers, compatible fsl,mpic-msi-v4.3
+ should be used.
- reg : It may contain one or two regions. The first region should contain
the address and the length of the shared message interrupt register set.
- The second region should contain the address of aliased MSIIR register for
- platforms that have such an alias.
-
-- msi-available-ranges: use start count style section to define which
- msi interrupt can be used in the 256 msi interrupts. This property is
- optional, without this, all the 256 MSI interrupts can be used.
- Each available range must begin and end on a multiple of 32 (i.e.
- no splitting an individual MSI register or the associated PIC interrupt).
+ The second region should contain the address of aliased MSIIR or MSIIR1
+ register for platforms that have such an alias, if using MSIIR1, the second
+ region must be added because different MSI group has different MSIRR1 offset.
- interrupts : each one of the interrupts here is one entry per 32 MSIs,
and routed to the host interrupt controller. the interrupts should
- be set as edge sensitive. If msi-available-ranges is present, only
- the interrupts that correspond to available ranges shall be present.
+ be set as edge sensitive.
- interrupt-parent: the phandle for the interrupt controller
that services interrupts for this device. for 83xx cpu, the interrupts
@@ -39,20 +36,18 @@ Optional properties:
Example:
msi@41600 {
- compatible = fsl,mpc8610-msi, fsl,mpic-msi;
- reg = 0x41600 0x80;
- msi-available-ranges = 0 0x100;
- interrupts =
- 0xe0 0
- 0xe1 0
- 0xe2 0
- 0xe3 0
- 0xe4 0
- 0xe5 0
- 0xe6 0
- 0xe7 0;
- interrupt-parent = mpic;
- };
+ compatible = fsl,mpic-msi;
+ reg = 0x41600 0x200 0x44140 4;
+ interrupts =
+ 0xe0 0 0 0
+ 0xe1 0 0 0
+ 0xe2 0 0 0
+ 0xe3 0 0 0
+ 0xe4 0 0 0
+ 0xe5 0 0 0
+ 0xe6 0 0 0
+ 0xe7 0 0 0;
+};
The Freescale hypervisor and msi-address-64
---
--
1.8.1.2
___
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Linuxppc-dev@lists.ozlabs.org
https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH 5/5] powerpc/fsl_msi: add 'msiregs' kernel parameter
1. Only MSIIR1 can index 16 MSI registers, but when using MSIIR1
the IRQs of a register are not continuous. for example, the first
register irq values are 0x0, 0x10, 0x20, 0x30 ... 0x1f0. So it
is hard to use 'msi-available-ranges' property to indicate the
available ranges and 'msi-available-ranges' property has been
removed from dts node, so this patch removes the related code.
2. Add 'msiregs' kernel parameter instead of 'msi-available-ranges'
functionality. 'msiregs' is used to indicate the available MSI
registers ranges and uses a colon ':' to separate the multiple
banks. The range representation format is 'start-end', 'start'
and 'end' are integers describe the start and end register index,
the available registers lies between start and end and not include
end. For example, the available register x satisfying
start = x end.
Signed-off-by: Minghuan Lian minghuan.l...@freescale.com
---
arch/powerpc/sysdev/fsl_msi.c | 118 --
arch/powerpc/sysdev/fsl_msi.h | 1 +
2 files changed, 80 insertions(+), 39 deletions(-)
diff --git a/arch/powerpc/sysdev/fsl_msi.c b/arch/powerpc/sysdev/fsl_msi.c
index 34510b7..db382ef9b 100644
--- a/arch/powerpc/sysdev/fsl_msi.c
+++ b/arch/powerpc/sysdev/fsl_msi.c
@@ -52,6 +52,60 @@ struct fsl_msi_cascade_data {
int index;
};
+struct msi_reg_range {
+ u32 start;
+ u32 end;
+};
+
+static struct msi_reg_range msiregs[NR_MSI_BANK] = {
+ {.start = 0, .end = NR_MSI_REG },
+ {.start = 0, .end = NR_MSI_REG },
+ {.start = 0, .end = NR_MSI_REG },
+ {.start = 0, .end = NR_MSI_REG },
+};
+
+/*
+ * Handle 'msiregs' parameter.
+ * msiregs is used to indicate the available MSI registers range and
+ * uses colon ':' to separate the multiple banks ranges.
+ * For each bank, the registers range format is 'start-end'
+ * start and end are integers, used to the indicate the start and end
+ * register index. The range is a set of real numbers that lies between
+ * start and end but not include end. For example, the set of all numbers
+ * x satisfying start = x end.
+ * if no range specified, driver will use the default range including all
+ * the registers.
+ * if you do no want to use this bank, you can set range as '0-0'
+ * For example msiregs=0-16:0-0::0-2
+ */
+static int msi_regs_setup(char *s)
+{
+ int bank = 0;
+ char *p;
+ struct msi_reg_range *range;
+
+ while ((p = strsep(s, :)) != NULL) {
+ int start = 0, end = NR_MSI_REG;
+
+ if (bank = NR_MSI_BANK)
+ break;
+ range = msiregs[bank];
+
+ if ((*p != '\0') (sscanf(p, %d-%d, start, end) 1))
+ pr_err(msiregs correct format is: start-end\n);
+
+ /* Ok, gets the specified value */
+ range-start = start;
+ range-end = end;
+ pr_info(MSI bank%d available regs range is %d-%d\n,
+bank, range-start, range-end);
+ bank++;
+ }
+ return 1;
+}
+
+__setup(msiregs=, msi_regs_setup);
+
static inline u32 fsl_msi_read(u32 __iomem *base, unsigned int reg)
{
return in_be32(base + (reg 2));
@@ -350,7 +404,7 @@ static int fsl_of_msi_remove(struct platform_device *ofdev)
static struct lock_class_key fsl_msi_irq_class;
static int fsl_msi_setup_hwirq(struct fsl_msi *msi, struct platform_device
*dev,
- int offset, int irq_index)
+ int irq_index)
{
struct fsl_msi_cascade_data *cascade_data = NULL;
int virt_msir, i;
@@ -369,7 +423,7 @@ static int fsl_msi_setup_hwirq(struct fsl_msi *msi, struct
platform_device *dev,
}
irq_set_lockdep_class(virt_msir, fsl_msi_irq_class);
msi-msi_virqs[irq_index] = virt_msir;
- cascade_data-index = offset;
+ cascade_data-index = irq_index;
cascade_data-msi_data = msi;
irq_set_handler_data(virt_msir, cascade_data);
irq_set_chained_handler(virt_msir, fsl_msi_cascade);
@@ -377,7 +431,7 @@ static int fsl_msi_setup_hwirq(struct fsl_msi *msi, struct
platform_device *dev,
/* Release the hwirqs corresponding to this MSI register */
for (i = 0; i IRQS_PER_MSI_REG; i++)
msi_bitmap_free_hwirqs(msi-bitmap,
- msi_hwirq(msi, offset, i), 1);
+ msi_hwirq(msi, irq_index, i), 1);
return 0;
}
@@ -387,21 +441,29 @@ static int fsl_of_msi_probe(struct platform_device *dev)
{
const struct of_device_id *match;
struct fsl_msi *msi;
+ static int bank;
+ struct msi_reg_range *range;
struct resource res, msiir;
- int err, i, j, irq_index, count;
+ int err, irq_index, count;
int rc;
- const u32 *p;
const struct fsl_msi_feature *features;
- int len;
- u32 offset;
- static const u32
[PATCH 4/5] powerpc/dts: remove msi-available-ranges property
For MPIC v4.3 MSIIR supports 8 MSI registers and MSIIR1 supports
16 MSI registers, but uses different IBS and SRS shift. For the
first register, when using MSIIR we will get the irqs 0x0 0x1 0x2
...0x1f, but when using MSIIR1, the irqs are 0x0 0x10 0x20 ... 0x1f0
It is hard to describe the available irqs using property
'msi-available-ranges'. The patch removes this property.
Signed-off-by: Minghuan Lian minghuan.l...@freescale.com
---
arch/powerpc/boot/dts/fsl/pq3-mpic.dtsi | 1 -
arch/powerpc/boot/dts/fsl/qoriq-mpic.dtsi| 3 ---
arch/powerpc/boot/dts/fsl/qoriq-mpic4.3.dtsi | 4
3 files changed, 8 deletions(-)
diff --git a/arch/powerpc/boot/dts/fsl/pq3-mpic.dtsi
b/arch/powerpc/boot/dts/fsl/pq3-mpic.dtsi
index 71c30eb..1ac4f23 100644
--- a/arch/powerpc/boot/dts/fsl/pq3-mpic.dtsi
+++ b/arch/powerpc/boot/dts/fsl/pq3-mpic.dtsi
@@ -66,7 +66,6 @@ message@41400 {
msi@41600 {
compatible = fsl,mpic-msi;
reg = 0x41600 0x80;
- msi-available-ranges = 0 0x100;
interrupts =
0xe0 0 0 0
0xe1 0 0 0
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-mpic.dtsi
b/arch/powerpc/boot/dts/fsl/qoriq-mpic.dtsi
index 08f4227..cf7355c 100644
--- a/arch/powerpc/boot/dts/fsl/qoriq-mpic.dtsi
+++ b/arch/powerpc/boot/dts/fsl/qoriq-mpic.dtsi
@@ -54,7 +54,6 @@ timer@41100 {
msi0: msi@41600 {
compatible = fsl,mpic-msi;
reg = 0x41600 0x200 0x44140 4;
- msi-available-ranges = 0 0x100;
interrupts =
0xe0 0 0 0
0xe1 0 0 0
@@ -69,7 +68,6 @@ msi0: msi@41600 {
msi1: msi@41800 {
compatible = fsl,mpic-msi;
reg = 0x41800 0x200 0x45140 4;
- msi-available-ranges = 0 0x100;
interrupts =
0xe8 0 0 0
0xe9 0 0 0
@@ -84,7 +82,6 @@ msi1: msi@41800 {
msi2: msi@41a00 {
compatible = fsl,mpic-msi;
reg = 0x41a00 0x200 0x46140 4;
- msi-available-ranges = 0 0x100;
interrupts =
0xf0 0 0 0
0xf1 0 0 0
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-mpic4.3.dtsi
b/arch/powerpc/boot/dts/fsl/qoriq-mpic4.3.dtsi
index e2665b8..8a997ea 100644
--- a/arch/powerpc/boot/dts/fsl/qoriq-mpic4.3.dtsi
+++ b/arch/powerpc/boot/dts/fsl/qoriq-mpic4.3.dtsi
@@ -54,7 +54,6 @@ timer@41100 {
msi0: msi@41600 {
compatible = fsl,mpic-msi, fsl,mpic-msi-v4.3;
reg = 0x41600 0x200 0x44148 4;
- msi-available-ranges = 0 0x200;
interrupts =
0xe0 0 0 0
0xe1 0 0 0
@@ -77,7 +76,6 @@ msi0: msi@41600 {
msi1: msi@41800 {
compatible = fsl,mpic-msi, fsl,mpic-msi-v4.3;
reg = 0x41800 0x200 0x45148 4;
- msi-available-ranges = 0 0x200;
interrupts =
0xe8 0 0 0
0xe9 0 0 0
@@ -100,7 +98,6 @@ msi1: msi@41800 {
msi2: msi@41a00 {
compatible = fsl,mpic-msi, fsl,mpic-msi-v4.3;
reg = 0x41a00 0x200 0x46148 4;
- msi-available-ranges = 0 0x200;
interrupts =
0xf0 0 0 0
0xf1 0 0 0
@@ -123,7 +120,6 @@ msi2: msi@41a00 {
msi3: msi@41c00 {
compatible = fsl,mpic-msi, fsl,mpic-msi-v4.3;
reg = 0x41c00 0x200 0x47148 4;
- msi-available-ranges = 0 0x200;
interrupts =
0xf8 0 0 0
0xf9 0 0 0
--
1.8.1.2
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Re: [BUG] PCI related panic on powerpc based board with 3.10-rcX
On Thursday 13 June 2013 11:49:17 Scott Wood wrote: On 06/13/2013 02:21:24 AM, Rojhalat Ibrahim wrote: On Wednesday 12 June 2013 16:50:26 Scott Wood wrote: On 06/12/2013 03:19:30 AM, Rojhalat Ibrahim wrote: On Tuesday 11 June 2013 12:28:59 Scott Wood wrote: Yes, I figured it was non-PCIe because the code change that you said helped was on the non-PCIe branch of the if/else. Generally it's good to explicitly mention the chip you're using, though. fsl_setup_indirect_pci should be renamed to fsl_setup_indirect_pcie. Your patch above should be applied, and fsl_setup_indirect_pcie should be moved into the booke/86xx ifdef to avoid an unused function warning. -Scott How about this patch? It uses setup_indirect_pci for the PCI case in mpc83xx_add_bridge. Additionally it adds a check in fsl_setup_indirect_pci to only use the modified read function in case of PCIe. If we're adding the check to fsl_setup_indirect_pci, there's no need to change the 83xx call back to setup_indirect_pci. I see that 85xx is also callirng fsl_setup_indirect_pci for both; it'd be good to be consistent. In any case, can you send a proper patch with a signoff and commit message? -Scott Where is it called for 85xx? As far as I can tell fsl_setup_indirect_pci is called exactly once in fsl_add_bridge and nowhere else (after applying the proposed patch). fsl_add_bridge() is where it's called for 85xx. For 83xx the decision between PCI and PCIe has already been made at the point where the setup function is called. So IMO it doesn't make sense to call fsl_setup_indirect_pci and do the check again. Moreover PCIe on 83xx uses a completely different set of functions. My concern is consistency. E.g. if 85xx is using fsl_setup_indirect_pci for both, but 83xx isn't, then a developer using 83xx could end up breaking 85xx by introducing another PCIe dependency in fsl_setup_indirect_pci. Or an 85xx developer could put something non-PCIe-related in fsl_setup_indirect_pci that 83xx would benefit from. Alternatively, you could call it fsl_setup_indirect_pcie, and move the PCIe check into fsl_add_bridge(). -Scott Ok. I'll post a v2 of the patch. Rojhalat ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH] powerpc/85xx: Add P1023RDB board support
P1023RDB Specification:
---
Memory subsystem:
512MB DDR3 (Fixed DDR on board)
64MB NOR flash
128MB NAND flash
Ethernet:
eTSEC1: Connected to Atheros AR8035 GETH PHY
eTSEC2: Connected to Atheros AR8035 GETH PHY
PCIe:
Three mini-PCIe slots
USB:
Two USB2.0 Type A ports
I2C:
AT24C08 8K Board EEPROM (8 bit address)
Signed-off-by: Chunhe Lan chunhe@freescale.com
Cc: Kumar Gala ga...@kernel.crashing.org
---
arch/powerpc/boot/dts/p1023rdb.dts | 191 ++
arch/powerpc/configs/85xx/p1023rds_defconfig |4 +
arch/powerpc/platforms/85xx/Kconfig |6 +
arch/powerpc/platforms/85xx/p1023_rds.c | 24 +++-
4 files changed, 224 insertions(+), 1 deletions(-)
create mode 100644 arch/powerpc/boot/dts/p1023rdb.dts
diff --git a/arch/powerpc/boot/dts/p1023rdb.dts
b/arch/powerpc/boot/dts/p1023rdb.dts
new file mode 100644
index 000..4ce1cc9
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1023rdb.dts
@@ -0,0 +1,191 @@
+/*
+ * P1023 RDB Device Tree Source
+ *
+ *Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * Author: Roy Zang tie-fei.z...@freescale.com
+ *Chunhe Lan chunhe@freescale.com
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License (GPL) as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/include/ fsl/p1023si-pre.dtsi
+
+/ {
+ model = fsl,P1023;
+ compatible = fsl,P1023RDB;
+ #address-cells = 2;
+ #size-cells = 2;
+ interrupt-parent = mpic;
+
+ memory {
+ device_type = memory;
+ };
+
+ soc: soc@ff60 {
+ ranges = 0x0 0x0 0xff60 0x20;
+
+ i2c@3000 {
+ eeprom@53 {
+ compatible = at24,24c04;
+ reg = 0x53;
+ };
+
+ rtc@6f {
+ compatible = microchip,mcp7941x;
+ reg = 0x6f;
+ };
+ };
+
+ usb@22000 {
+ dr_mode = host;
+ phy_type = ulpi;
+ };
+ };
+
+ lbc: localbus@ff605000 {
+ reg = 0 0xff605000 0 0x1000;
+
+ /* NOR Flash */
+ ranges = 0x0 0x0 0x0 0xec00 0x0400;
+
+ nor@0,0 {
+ #address-cells = 1;
+ #size-cells = 1;
+ compatible = cfi-flash;
+ reg = 0x0 0x0 0x0400;
+ bank-width = 2;
+ device-width = 1;
+
+ partition@0 {
+ label = ramdisk;
+ reg = 0x 0x0300;
+ };
+ partition@300 {
+ label = kernel;
+ reg = 0x0300 0x00ee;
+ };
+ partiton@3ee {
+ label = dtb;
+ reg = 0x03ee 0x0002;
+ };
+ partition@3f0 {
+ label = firmware;
+ reg = 0x03f0
[PATCH v2] powerpc/pci: Fix setup of Freescale PCI / PCIe controllers
Commit 50d8f87d2b3 (powerpc/fsl-pci Make PCIe hotplug work with Freescale
PCIe controllers) does not handle non-PCIe controllers properly, which causes
a panic during boot for certain configurations.
This patch fixes the issue by calling setup_indirect_pci for all device types.
fsl_indirect_read_config is now only used for booke/86xx PCIe controllers.
Reported-by: Michael Guntsche m...@it-loops.com
Cc: Scott Wood scottw...@freescale.com
Signed-off-by: Rojhalat Ibrahim i...@rtschenk.de
---
v2: Make it more consistent.
arch/powerpc/sysdev/fsl_pci.c | 20 +++-
1 file changed, 7 insertions(+), 13 deletions(-)
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index 028ac1f..5682c8a 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -97,20 +97,12 @@ static int fsl_indirect_read_config(struct pci_bus *bus,
unsigned int devfn,
return indirect_read_config(bus, devfn, offset, len, val);
}
-static struct pci_ops fsl_indirect_pci_ops =
+static struct pci_ops fsl_indirect_pcie_ops =
{
.read = fsl_indirect_read_config,
.write = indirect_write_config,
};
-static void __init fsl_setup_indirect_pci(struct pci_controller* hose,
- resource_size_t cfg_addr,
- resource_size_t cfg_data, u32 flags)
-{
- setup_indirect_pci(hose, cfg_addr, cfg_data, flags);
- hose-ops = fsl_indirect_pci_ops;
-}
-
#if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
#define MAX_PHYS_ADDR_BITS 40
@@ -504,13 +496,15 @@ int __init fsl_add_bridge(struct platform_device *pdev,
int is_primary)
if (!hose-private_data)
goto no_bridge;
- fsl_setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4,
- PPC_INDIRECT_TYPE_BIG_ENDIAN);
+ setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4,
+ PPC_INDIRECT_TYPE_BIG_ENDIAN);
if (in_be32(pci-block_rev1) PCIE_IP_REV_3_0)
hose-indirect_type |= PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK;
if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
+ /* use fsl_indirect_read_config for PCIe */
+ hose-ops = fsl_indirect_pcie_ops;
/* For PCIE read HEADER_TYPE to identify controler mode */
early_read_config_byte(hose, 0, 0, PCI_HEADER_TYPE, hdr_type);
if ((hdr_type 0x7f) != PCI_HEADER_TYPE_BRIDGE)
@@ -814,8 +808,8 @@ int __init mpc83xx_add_bridge(struct device_node *dev)
if (ret)
goto err0;
} else {
- fsl_setup_indirect_pci(hose, rsrc_cfg.start,
- rsrc_cfg.start + 4, 0);
+ setup_indirect_pci(hose, rsrc_cfg.start,
+ rsrc_cfg.start + 4, 0);
}
printk(KERN_INFO Found FSL PCI host bridge at 0x%016llx.
--
1.8.1.5
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[PATCH] powerpc: Fix emulation of illegal instructions on PowerNV platform
Normally, the kernel emulates a few instructions that are unimplemented
on some processors (e.g. the old dcba instruction), or privileged (e.g.
mfpvr). The emulation of unimplemented instructions is currently not
working on the PowerNV platform. The reason is that on these machines,
unimplemented and illegal instructions cause a hypervisor emulation
assist interrupt, rather than a program interrupt as on older CPUs.
Our vector for the emulation assist interrupt just calls
program_check_exception() directly, without setting the bit in SRR1
that indicates an illegal instruction interrupt. This fixes it by
making the emulation assist interrupt set that bit before calling
program_check_interrupt(). With this, old programs that use no-longer
implemented instructions such as dcba now work again.
Signed-off-by: Paul Mackerras pau...@samba.org
---
arch/powerpc/kernel/exceptions-64s.S |2 +-
arch/powerpc/kernel/traps.c | 10 ++
2 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/kernel/exceptions-64s.S
b/arch/powerpc/kernel/exceptions-64s.S
index e783453..40e4a17 100644
--- a/arch/powerpc/kernel/exceptions-64s.S
+++ b/arch/powerpc/kernel/exceptions-64s.S
@@ -683,7 +683,7 @@ machine_check_common:
STD_EXCEPTION_COMMON(0xb00, trap_0b, .unknown_exception)
STD_EXCEPTION_COMMON(0xd00, single_step, .single_step_exception)
STD_EXCEPTION_COMMON(0xe00, trap_0e, .unknown_exception)
- STD_EXCEPTION_COMMON(0xe40, emulation_assist, .program_check_exception)
+ STD_EXCEPTION_COMMON(0xe40, emulation_assist,
.emulation_assist_interrupt)
STD_EXCEPTION_COMMON(0xe60, hmi_exception, .unknown_exception)
#ifdef CONFIG_PPC_DOORBELL
STD_EXCEPTION_COMMON_ASYNC(0xe80, h_doorbell, .doorbell_exception)
diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/traps.c
index f18c79c..c0e5caf 100644
--- a/arch/powerpc/kernel/traps.c
+++ b/arch/powerpc/kernel/traps.c
@@ -1165,6 +1165,16 @@ bail:
exception_exit(prev_state);
}
+/*
+ * This occurs when running in hypervisor mode on POWER6 or later
+ * and an illegal instruction is encountered.
+ */
+void __kprobes emulation_assist_interrupt(struct pt_regs *regs)
+{
+ regs-msr |= REASON_ILLEGAL;
+ program_check_exception(regs);
+}
+
void alignment_exception(struct pt_regs *regs)
{
enum ctx_state prev_state = exception_enter();
--
1.7.10.4
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Re: [PATCH v2] powerpc/pci: Fix setup of Freescale PCI / PCIe controllers
On 06/14/2013 04:05:34 AM, Rojhalat Ibrahim wrote:
Commit 50d8f87d2b3 (powerpc/fsl-pci Make PCIe hotplug work with
Freescale
PCIe controllers) does not handle non-PCIe controllers properly,
which causes
a panic during boot for certain configurations.
This patch fixes the issue by calling setup_indirect_pci for all
device types.
fsl_indirect_read_config is now only used for booke/86xx PCIe
controllers.
Reported-by: Michael Guntsche m...@it-loops.com
Cc: Scott Wood scottw...@freescale.com
Signed-off-by: Rojhalat Ibrahim i...@rtschenk.de
---
v2: Make it more consistent.
arch/powerpc/sysdev/fsl_pci.c | 20 +++-
1 file changed, 7 insertions(+), 13 deletions(-)
diff --git a/arch/powerpc/sysdev/fsl_pci.c
b/arch/powerpc/sysdev/fsl_pci.c
index 028ac1f..5682c8a 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -97,20 +97,12 @@ static int fsl_indirect_read_config(struct
pci_bus *bus,
unsigned int devfn,
return indirect_read_config(bus, devfn, offset, len, val);
}
-static struct pci_ops fsl_indirect_pci_ops =
+static struct pci_ops fsl_indirect_pcie_ops =
{
.read = fsl_indirect_read_config,
.write = indirect_write_config,
};
On 83xx:
cc1: warnings being treated as errors
/home/scott/fsl/git/linux/upstream/arch/powerpc/sysdev/fsl_pci.c:100:23:
error: 'fsl_indirect_pcie_ops' defined but not used
make[2]: *** [arch/powerpc/sysdev/fsl_pci.o] Error 1
make[2]: *** Waiting for unfinished jobs
I can fix this when applying, but this makes me wonder how you tested
it, given that the whole point is to fix 83xx... Did you fix this and
then accidentally sent a stale version?
Also, please be careful that the patch doesn't get line wrapped -- I
had to manually unwrap a couple places. Use git send-email if you
can't get KMail to cooperate.
-Scott
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Re: [PATCH 1/5] powerpc/dts: add MPIC v4.3 dts node
On 06/14/2013 02:15:55 AM, Minghuan Lian wrote:
+msi0: msi@41600 {
+ compatible = fsl,mpic-msi, fsl,mpic-msi-v4.3;
More specific compatibles come first -- and I don't think this is 100%
backwards compatible with fsl,mpic-msi anyway.
-Scott
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Re: Regression in RCU subsystem in latest mainline kernel
On Fri, 2013-06-14 at 14:46 +0200, Rojhalat Ibrahim wrote: On Friday 14 June 2013 05:28:00 Paul E. McKenney wrote: On Fri, Jun 14, 2013 at 01:47:00PM +0200, Rojhalat Ibrahim wrote: Hi, the current mainline kernel from git reproducibly hangs on my Freescale PowerPC P5020DS development system. Most of the time the hang occurs during boot (kernel just stops booting, system hangs), sometimes shortly after booting (system hangs, no message). Very often booting stops at the initialization of the Intel PRO 1000 PCIe network device (e1000e). I was pretty much able to reproduce this on my PA Semi PPC box. Funny thing is, when I type on the console, it makes progress. Anyway, it seems that powerpc has an issue with irq_work(). I'll try to get some time either tonight or next week to figure it out. Thanks! -- Steve I used git bisect and arrived at this commit: 016a8d5be6ddcc72ef0432d82d9f6fa34f61b907 rcu: Don't call wakeup() with rcu_node structure -lock held With versions before that commit the system runs normally. Odd, given that this fix was intended to prevent hangs. Could you please send your .config? Thanx, Paul ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH 1/5] powerpc/dts: add MPIC v4.3 dts node
On 06/14/2013 03:39:26 PM, Scott Wood wrote:
On 06/14/2013 02:15:55 AM, Minghuan Lian wrote:
+msi0: msi@41600 {
+ compatible = fsl,mpic-msi, fsl,mpic-msi-v4.3;
More specific compatibles come first -- and I don't think this is
100% backwards compatible with fsl,mpic-msi anyway.
Also please update the binding.
-Scott
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[PATCH] trivial: powerpc: fix typo in ioei_interrupt() description
Signed-off-by: Sebastien Bessiere sebastien.bessi...@gmail.com --- arch/powerpc/platforms/pseries/io_event_irq.c |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/powerpc/platforms/pseries/io_event_irq.c b/arch/powerpc/platforms/pseries/io_event_irq.c index ef9d9d8..5ea88d1 100644 --- a/arch/powerpc/platforms/pseries/io_event_irq.c +++ b/arch/powerpc/platforms/pseries/io_event_irq.c @@ -115,7 +115,7 @@ static struct pseries_io_event * ioei_find_event(struct rtas_error_log *elog) * by scope or event type alone. For example, Torrent ISR route change * event is reported with scope 0x00 (Not Applicatable) rather than * 0x3B (Torrent-hub). It is better to let the clients to identify - * who owns the the event. + * who owns the event. */ static irqreturn_t ioei_interrupt(int irq, void *dev_id) -- 1.7.9.5 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH] dtc: ensure #line directives don't consume data from the next line
On Wed, 05 Jun 2013 10:50:02 -0600, Stephen Warren swar...@wwwdotorg.org
wrote:
On 06/03/2013 09:36 AM, Stephen Warren wrote:
From: Stephen Warren swar...@nvidia.com
Previously, the #line parsing regex ended with ({WS}+[0-9]+)?. The {WS}
could match line-break characters. If the #line directive did not contain
the optional flags field at the end, this could cause any integer data on
the next line to be consumed as part of the #line directive parsing. This
could cause syntax errors (i.e. #line parsing consuming the leading 0
from a hex literal 0x1234, leaving x1234 to be parsed as cell data,
which is a syntax error), or invalid compilation results (i.e. simply
consuming literal 1234 as part of the #line processing, thus removing it
from the cell data).
Fix this by replacing {WS} with [ \t] so that it can't match line-breaks.
Convert all instances of {WS}, even though the other instances should be
irrelevant for any well-formed #line directive. This is done for
consistency and ultimate safety.
This is a port of upstream dtc commit a1ee6f0 (with same subject) to the
kernel's copy of dtc.
Rob, Grant, does this look OK to apply for v3.10-rc*?
The fix is in mainline now. Please check to make sure it is working for you.
g.
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Re: [PATCH 3/5] powerpc/dts: update MSI bindings doc for MPIC v4.3
On 06/14/2013 02:15:57 AM, Minghuan Lian wrote:
Add compatible fsl,mpic-msi-v4.3 for MPIC v4.3. MPIC v4.3 contains
MSIIR and MSIIR1. MSIIR supports 8 MSI registers and MSIIR1 supports
16 MSI registers, but uses different IBS and SRS shift. When using
MSIR1, the interrupt number is not consecutive. It is hard to use
'msi-available-ranges' to describe the ranges of the available
interrupt and the ranges are related to the application, rather than
the description of the hardware. this patch also removes
'msi-available-ranges' property.
Signed-off-by: Minghuan Lian minghuan.l...@freescale.com
---
.../devicetree/bindings/powerpc/fsl/msi-pic.txt| 49
++
1 file changed, 22 insertions(+), 27 deletions(-)
diff --git
a/Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt
b/Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt
index 5693877..e851e93 100644
--- a/Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt
+++ b/Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt
@@ -1,26 +1,23 @@
* Freescale MSI interrupt controller
Required properties:
-- compatible : compatible list, contains 2 entries,
+- compatible : compatible list, may contains one or two entries,
first is fsl,CHIP-msi, where CHIP is the processor(mpc8610,
mpc8572,
- etc.) and the second is fsl,mpic-msi or fsl,ipic-msi depending
on
- the parent type.
+ etc.) and the second is fsl,mpic-msi or fsl,ipic-msi or
+ fsl,mpic-msi-v4.3 depending on the parent type and version. If
mpic
+ version is 4.3, the number of MSI registers is increased to 16,
MSIIR1 is
+ provided to access these 16 registers, compatible
fsl,mpic-msi-v4.3
+ should be used.
Why one or two? What does it look like in the case where there's
just one?
- reg : It may contain one or two regions. The first region should
contain
the address and the length of the shared message interrupt
register set.
- The second region should contain the address of aliased MSIIR
register for
- platforms that have such an alias.
-
-- msi-available-ranges: use start count style section to define
which
- msi interrupt can be used in the 256 msi interrupts. This property
is
- optional, without this, all the 256 MSI interrupts can be used.
- Each available range must begin and end on a multiple of 32 (i.e.
- no splitting an individual MSI register or the associated PIC
interrupt).
+ The second region should contain the address of aliased MSIIR or
MSIIR1
+ register for platforms that have such an alias, if using MSIIR1,
the second
+ region must be added because different MSI group has different
MSIRR1 offset.
Why are you removing msi-available-ranges? It's not valid for MPIC
v4.3, but it's still valid for older MPICs. It should move to the
optional section, though.
- interrupts : each one of the interrupts here is one entry per 32
MSIs,
and routed to the host interrupt controller. the interrupts should
- be set as edge sensitive. If msi-available-ranges is present, only
- the interrupts that correspond to available ranges shall be
present.
+ be set as edge sensitive.
- interrupt-parent: the phandle for the interrupt controller
that services interrupts for this device. for 83xx cpu, the
interrupts
@@ -39,20 +36,18 @@ Optional properties:
Example:
msi@41600 {
- compatible = fsl,mpc8610-msi, fsl,mpic-msi;
- reg = 0x41600 0x80;
- msi-available-ranges = 0 0x100;
- interrupts =
- 0xe0 0
- 0xe1 0
- 0xe2 0
- 0xe3 0
- 0xe4 0
- 0xe5 0
- 0xe6 0
- 0xe7 0;
- interrupt-parent = mpic;
- };
+ compatible = fsl,mpic-msi;
+ reg = 0x41600 0x200 0x44140 4;
Why 0x200?
-Scott
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Re: [PATCH 2/5] powerpc/fsl_msi: add MSIIR1 support for MPIC v4.3
On 06/14/2013 02:15:56 AM, Minghuan Lian wrote:
@@ -421,10 +440,29 @@ static int fsl_of_msi_probe(struct
platform_device *dev)
}
msi-msiir_offset =
features-msiir_offset + (res.start 0xf);
+
+ /*
+* First read the MSIIR/MSIIR1 offset from dts
+* If failure use the hardcode MSIIR offset
On failure
+*/
+ if (of_address_to_resource(dev-dev.of_node, 1, msiir))
+ msi-msiir_offset = features-msiir_offset +
+ (res.start
MSIIR_OFFSET_MASK);
+ else
+ msi-msiir_offset = msiir.start
MSIIR_OFFSET_MASK;
}
msi-feature = features-fsl_pic_ip;
+ if (of_device_is_compatible(dev-dev.of_node,
fsl,mpic-msi-v4.3)) {
+ msi-srs_shift = MSIIR1_SRS_SHIFT;
+ msi-ibs_shift = MSIIR1_IBS_SHIFT;
+
+ } else {
+ msi-srs_shift = MSIIR_SRS_SHIFT;
+ msi-ibs_shift = MSIIR_IBS_SHIFT;
+ }
Remove the blank line just before the } else {.
diff --git a/arch/powerpc/sysdev/fsl_msi.h
b/arch/powerpc/sysdev/fsl_msi.h
index 8225f86..43a9d99 100644
--- a/arch/powerpc/sysdev/fsl_msi.h
+++ b/arch/powerpc/sysdev/fsl_msi.h
@@ -16,7 +16,7 @@
#include linux/of.h
#include asm/msi_bitmap.h
-#define NR_MSI_REG 8
+#define NR_MSI_REG 16
#define IRQS_PER_MSI_REG 32
#define NR_MSI_IRQS(NR_MSI_REG * IRQS_PER_MSI_REG)
I don't see where you update all_avail in fsl_of_msi_probe.
We should also be bounds-checking the contents of msi-available-ranges.
Currently it looks like we just silently overrun the bitmap if we get
bad
input from the device tree.
-Scott
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Re: [PATCH 5/5] powerpc/fsl_msi: add 'msiregs' kernel parameter
On 06/14/2013 02:15:59 AM, Minghuan Lian wrote: 1. Only MSIIR1 can index 16 MSI registers, but when using MSIIR1 the IRQs of a register are not continuous. for example, the first register irq values are 0x0, 0x10, 0x20, 0x30 ... 0x1f0. So it is hard to use 'msi-available-ranges' property to indicate the available ranges and 'msi-available-ranges' property has been removed from dts node, so this patch removes the related code. 2. Add 'msiregs' kernel parameter instead of 'msi-available-ranges' functionality. The reason we used a device tree property was because this is for virtualization and AMP scenarios where this instance of Linux does not own all of the MSI registers. I don't see any reasonable way to partition an MPIC v4.3 MSI group -- but there are more groups, so it's not that bad. What's the use case for this patch? -Scott ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH 4/5] powerpc/dts: remove msi-available-ranges property
On 06/14/2013 02:15:58 AM, Minghuan Lian wrote: For MPIC v4.3 MSIIR supports 8 MSI registers and MSIIR1 supports 16 MSI registers, but uses different IBS and SRS shift. For the first register, when using MSIIR we will get the irqs 0x0 0x1 0x2 ...0x1f, but when using MSIIR1, the irqs are 0x0 0x10 0x20 ... 0x1f0 It is hard to describe the available irqs using property 'msi-available-ranges'. The patch removes this property. Only remove it from mpic 4.3. And since you introduced qoriq-mpic4.3.dtsi earlier in the patchset, why didn't you just avoid adding it then? -Scott ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH] powerpc/sysfs: disable hotplug for the boot cpu
On Thu, 2013-06-13 at 19:25 +0800, Zhao Chenhui wrote: Some multicore SoCs firstly boot up the cpu0 after warm reset. In some suspend/resume cases, SoC will do a warm reset when resuming. In order to ensure that the suspending and resuming is running on a same cpu, cpu0 should be the last cpu to suspend. Here, cpu0 is the boot_cpuid. Well, so: - In any case, your patch will break pseries, so it's not acceptable. - Why does it have to absolutely resume from the same CPU it suspended from ? Can't you have a little bit of code on the resuming CPU that checks if it's not online, poke an online one and goes back to sleep ? Cheers, Ben. ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: Regression in RCU subsystem in latest mainline kernel
On Fri, 2013-06-14 at 17:06 -0400, Steven Rostedt wrote: I was pretty much able to reproduce this on my PA Semi PPC box. Funny thing is, when I type on the console, it makes progress. Anyway, it seems that powerpc has an issue with irq_work(). I'll try to get some time either tonight or next week to figure it out. Does this help ? diff --git a/arch/powerpc/kernel/irq.c b/arch/powerpc/kernel/irq.c index 5cbcf4d..ea185e0 100644 --- a/arch/powerpc/kernel/irq.c +++ b/arch/powerpc/kernel/irq.c @@ -162,7 +162,7 @@ notrace unsigned int __check_irq_replay(void) * in case we also had a rollover while hard disabled */ local_paca-irq_happened = ~PACA_IRQ_DEC; - if (decrementer_check_overflow()) + if ((happened PACA_IRQ_DEC) || decrementer_check_overflow()) return 0x900; /* Finally check if an external interrupt happened */ Cheers, Ben. ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH] powerpc: Fix missing/delayed calls to irq_work
When replaying interrupts (as a result of the interrupt occurring while soft-disabled), in the case of the decrementer, we are exclusively testing for a pending timer target. However we also use decrementer interrupts to trigger the new irq_work, which in this case would be missed. This change the logic to force a replay in both cases of a timer boundary reached and a decrementer interrupt having actually occurred while disabled. The former test is still useful to catch cases where a CPU having been hard-disabled for a long time completely misses the interrupt due to a decrementer rollover. Signed-off-by: Benjamin Herrenschmidt b...@kernel.crashing.org --- diff --git a/arch/powerpc/kernel/irq.c b/arch/powerpc/kernel/irq.c index 5cbcf4d..ea185e0 100644 --- a/arch/powerpc/kernel/irq.c +++ b/arch/powerpc/kernel/irq.c @@ -162,7 +162,7 @@ notrace unsigned int __check_irq_replay(void) * in case we also had a rollover while hard disabled */ local_paca-irq_happened = ~PACA_IRQ_DEC; - if (decrementer_check_overflow()) + if ((happened PACA_IRQ_DEC) || decrementer_check_overflow()) return 0x900; /* Finally check if an external interrupt happened */ ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: Regression in RCU subsystem in latest mainline kernel
On Sat, 2013-06-15 at 12:02 +1000, Benjamin Herrenschmidt wrote: On Fri, 2013-06-14 at 17:06 -0400, Steven Rostedt wrote: I was pretty much able to reproduce this on my PA Semi PPC box. Funny thing is, when I type on the console, it makes progress. Anyway, it seems that powerpc has an issue with irq_work(). I'll try to get some time either tonight or next week to figure it out. Does this help ? It did for me. Rojhalat, did this fix your issue too? -- Steve diff --git a/arch/powerpc/kernel/irq.c b/arch/powerpc/kernel/irq.c index 5cbcf4d..ea185e0 100644 --- a/arch/powerpc/kernel/irq.c +++ b/arch/powerpc/kernel/irq.c @@ -162,7 +162,7 @@ notrace unsigned int __check_irq_replay(void) * in case we also had a rollover while hard disabled */ local_paca-irq_happened = ~PACA_IRQ_DEC; - if (decrementer_check_overflow()) + if ((happened PACA_IRQ_DEC) || decrementer_check_overflow()) return 0x900; /* Finally check if an external interrupt happened */ Cheers, Ben. ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: Regression in RCU subsystem in latest mainline kernel
On Fri, 2013-06-14 at 22:17 -0400, Steven Rostedt wrote: On Sat, 2013-06-15 at 12:02 +1000, Benjamin Herrenschmidt wrote: On Fri, 2013-06-14 at 17:06 -0400, Steven Rostedt wrote: I was pretty much able to reproduce this on my PA Semi PPC box. Funny thing is, when I type on the console, it makes progress. Anyway, it seems that powerpc has an issue with irq_work(). I'll try to get some time either tonight or next week to figure it out. Does this help ? It did for me. Rojhalat, did this fix your issue too? Ok, adding that to what I'm about to send to Linus. Cheers, Ben. ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: Regression in RCU subsystem in latest mainline kernel
On Sat, 2013-06-15 at 12:21 +1000, Benjamin Herrenschmidt wrote: On Fri, 2013-06-14 at 22:17 -0400, Steven Rostedt wrote: On Sat, 2013-06-15 at 12:02 +1000, Benjamin Herrenschmidt wrote: On Fri, 2013-06-14 at 17:06 -0400, Steven Rostedt wrote: I was pretty much able to reproduce this on my PA Semi PPC box. Funny thing is, when I type on the console, it makes progress. Anyway, it seems that powerpc has an issue with irq_work(). I'll try to get some time either tonight or next week to figure it out. Does this help ? It did for me. Rojhalat, did this fix your issue too? Ok, adding that to what I'm about to send to Linus. Feel free to add: Tested-by: Steven Rostedt rost...@goodmis.org -- Steve ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: Regression in RCU subsystem in latest mainline kernel
On Fri, Jun 14, 2013 at 10:31:12PM -0400, Steven Rostedt wrote: On Sat, 2013-06-15 at 12:21 +1000, Benjamin Herrenschmidt wrote: On Fri, 2013-06-14 at 22:17 -0400, Steven Rostedt wrote: On Sat, 2013-06-15 at 12:02 +1000, Benjamin Herrenschmidt wrote: On Fri, 2013-06-14 at 17:06 -0400, Steven Rostedt wrote: I was pretty much able to reproduce this on my PA Semi PPC box. Funny thing is, when I type on the console, it makes progress. Anyway, it seems that powerpc has an issue with irq_work(). I'll try to get some time either tonight or next week to figure it out. Does this help ? It did for me. Rojhalat, did this fix your issue too? Ok, adding that to what I'm about to send to Linus. Feel free to add: Tested-by: Steven Rostedt rost...@goodmis.org Thank you both!!! Thanx, Paul ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[git pull] Please pull powerpc.git merge branch
Hi Linus ! Hopefully this one smells better ... So here are 3 fixes still for 3.10. Fixes are simple, bugs are nasty (though not recent regressions, nasty enough) and all targeted at stable. Please apply. Thanks ! Cheers, Ben. The following changes since commit 34376a50fb1fa095b9d0636fa41ed2e73125f214: Fix lockup related to stop_machine being stuck in __do_softirq. (2013-06-10 17:46:57 -0700) are available in the git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc.git merge for you to fetch changes up to 230b3034793247f61e6a0b08c44cf415f6d92981: powerpc: Fix missing/delayed calls to irq_work (2013-06-15 12:33:30 +1000) Benjamin Herrenschmidt (1): powerpc: Fix missing/delayed calls to irq_work Michael Ellerman (1): powerpc: Fix stack overflow crash in resume_kernel when ftracing Paul Mackerras (1): powerpc: Fix emulation of illegal instructions on PowerNV platform arch/powerpc/include/asm/exception-64s.h |2 +- arch/powerpc/kernel/exceptions-64s.S |2 +- arch/powerpc/kernel/irq.c|2 +- arch/powerpc/kernel/process.c|4 ++-- arch/powerpc/kernel/traps.c | 10 ++ 5 files changed, 15 insertions(+), 5 deletions(-) ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
