On Thu, 2013-07-04 at 06:47 +, Caraman Mihai Claudiu-B02008 wrote:
> This is a solid reason. Ben it's ok for you to apply the combined
> patch? If so I will respin it.
Sure, but nowadays, all that stuff goes via Scott and Alex.
Cheers,
Ben.
___
Li
> -Original Message-
> From: kvm-ppc-ow...@vger.kernel.org [mailto:kvm-ppc-
> ow...@vger.kernel.org] On Behalf Of Alexander Graf
> Sent: Wednesday, July 03, 2013 9:40 PM
> To: Wood Scott-B07421
> Cc: Caraman Mihai Claudiu-B02008; kvm-...@vger.kernel.org;
> k...@vger.kernel.org; linuxppc-d
> -Original Message-
> From: Wood Scott-B07421
> Sent: Wednesday, July 03, 2013 11:17 PM
> To: Caraman Mihai Claudiu-B02008
> Cc: linuxppc-dev@lists.ozlabs.org; kvm-...@vger.kernel.org;
> k...@vger.kernel.org; Caraman Mihai Claudiu-B02008
> Subject: Re: [PATCH 2/2] KVM: PPC: Book3E: Add LRA
> -Original Message-
> From: Wood Scott-B07421
> Sent: Wednesday, July 03, 2013 11:18 PM
> To: Caraman Mihai Claudiu-B02008
> Cc: linuxppc-dev@lists.ozlabs.org; kvm-...@vger.kernel.org;
> k...@vger.kernel.org; Caraman Mihai Claudiu-B02008
> Subject: Re: [PATCH 1/2] powerpc/booke64: Add LRAT
This way we can use same data type struct with KVM and
also help in using other debug related function.
Signed-off-by: Bharat Bhushan
---
arch/powerpc/include/asm/processor.h | 38 +
arch/powerpc/include/asm/reg_booke.h |8 +-
arch/powerpc/kernel/asm-offsets.c|2 +-
arch/po
Signed-off-by: Bharat Bhushan
---
arch/powerpc/kernel/process.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c
index c517dbe..19b8733 100644
--- a/arch/powerpc/kernel/process.c
+++ b/arch/powerpc/kernel/proce
From: Bharat Bhushan
This patchset moves the debug registers in a structure, which allows
kvm to use same structure for debug emulation.
Note: Earilier a patchset
"https://lists.ozlabs.org/pipermail/linuxppc-dev/2013-June/108132.html";
was sent which is a bunch of six patches. That patchset is
From: "Aneesh Kumar K.V"
The sllp value is stored in mmu_psize_defs in such a way that we can easily OR
the value to get the operand for slbmte instruction. ie, the L and LP bits are
not contiguous. Decode the bits and use them correctly in tlbie.
regression is introduced by 1f6aaaccb1b3af8613fe4
Hello, i'm developing an embedded linux system on a custom mpc5200b board, at
University.
We have a problem with a custom version of kernel: 2.6.23 and 2.6.33. We can't
use newer version at the moment.
We are able to compile and load the kernel on Freescale Lite5200b and on Custom
Board.
So,
Some systems have an ibm,chip-id property in the cpu nodes in the
device tree. On these systems, we now use that to compute the
cpu_core_mask (i.e. the set of core siblings) rather than looking
at cache properties.
Signed-off-by: Paul Mackerras
---
diff --git a/arch/powerpc/kernel/smp.c b/arch/p
Regards & Thanks
Haijun.
发件人: Wood Scott-B07421
发送时间: 2013年7月3日 19:09
收件人: Zhang Haijun-B42677
Cc: ga...@kernel.crashing.org; linuxppc-dev@lists.ozlabs.org; Zhang
Haijun-B42677; Huang Changming-R66093
主题: Re: [PATCH 2/2] powerpc/85xx: add the P1020RDB-P
On Wed, Jul 03, 2013 at 03:38:27PM -0500, Scott Wood wrote:
> On 07/02/2013 10:00:44 PM, Kevin Hao wrote:
> >On Tue, Jul 02, 2013 at 05:39:18PM -0500, Scott Wood wrote:
> >> How much overhead (space and time) is this really?
> >
> >The following is the additional sections when relocatable is
> >ena
Because of the changes made in dcache.h header file, files that
use the d_lock field of the dentry structure need to be changed
accordingly. All the d_lock's spin_lock() and spin_unlock() calls
are replaced by the corresponding d_lock() and d_unlock() calls.
There is no change in logic and everythi
Hi Linus !
This is the powerpc changes for the 3.11 merge window. In addition to
the usual bug fixes and small updates, the main highlights are:
- Support for transparent huge pages by Aneesh Kumar for 64-bit server
processors. This allows the use of 16M pages as transparent huge pages
on kernel
On 07/03/2013 04:42:40 PM, Alexander Graf wrote:
On 03.07.2013, at 22:16, Scott Wood wrote:
> On 07/03/2013 11:56:06 AM, Mihai Caraman wrote:
>> With LRAT (Logical to Real Address Translation) error exception
handler in kernel
>> KVM needs to add the counterpart otherwise will break the buil
On 03.07.2013, at 22:16, Scott Wood wrote:
> On 07/03/2013 11:56:06 AM, Mihai Caraman wrote:
>> With LRAT (Logical to Real Address Translation) error exception handler in
>> kernel
>> KVM needs to add the counterpart otherwise will break the build.
>> Signed-off-by: Mihai Caraman
>> ---
>> arch
From: James Yang
Reserved fields of the sync instruction have been used for other
instructions (e.g. lwsync). On processors that do not support variants
of the sync instruction, emulate it by executing a sync to subsume the
effect of the intended instruction.
Signed-off-by: James Yang
---
arc
On 07/02/2013 10:00:44 PM, Kevin Hao wrote:
On Tue, Jul 02, 2013 at 05:39:18PM -0500, Scott Wood wrote:
> How much overhead (space and time) is this really?
The following is the additional sections when relocatable is enabled
for
a p2020rdb board.
sectionsize
.dynsym 07
On 07/03/2013 11:56:05 AM, Mihai Caraman wrote:
@@ -1410,6 +1423,7 @@ _GLOBAL(setup_doorbell_ivors)
_GLOBAL(setup_ehv_ivors)
SET_IVOR(40, 0x300) /* Embedded Hypervisor System Call */
SET_IVOR(41, 0x320) /* Embedded Hypervisor Privilege */
+ SET_IVOR(42, 0x340) /* LRAT Error
Change endpoint device name format to use a component tag value instead of
device destination ID.
RapidIO specification defines a component tag to be a unique identifier
for devices in a network. RapidIO switches already use component tag as
part of their device name and also use it for device ide
On 07/03/2013 11:56:06 AM, Mihai Caraman wrote:
With LRAT (Logical to Real Address Translation) error exception
handler in kernel
KVM needs to add the counterpart otherwise will break the build.
Signed-off-by: Mihai Caraman
---
arch/powerpc/kvm/bookehv_interrupts.S |2 ++
1 files changed
On 06/30/2013 11:12:23 PM, Haijun Zhang wrote:
From: "Haijun.Zhang"
Overview of P1020RDB-PD device:
- DDR3 2GB
- NOR flash 64MB
- NAND flash 128MB
- SPI flash 16MB
- I2C EEPROM 256Kb
- eTSEC1 (RGMII PHY) connected to VSC7385 L2 switch
- eTSEC2 (SGMII PHY)
- eTSEC3 (RGMII PHY)
- SDHC
- 2 USB por
On 07/03/2013 02:48:59 AM, Hongbo Zhang wrote:
On 07/03/2013 11:53 AM, Hongbo Zhang wrote:
hmm...add the devicetree-disc...@lists.ozlabs.org into list.
Note that we are discussing a better naming for this new compatible
property in the corresponding [PATCH 2/2], so I will resend a v2 of
thi
On 03.07.2013, at 20:36, Scott Wood wrote:
> On 07/03/2013 12:07:30 PM, Alexander Graf wrote:
>> On 03.07.2013, at 18:49, Caraman Mihai Claudiu-B02008 wrote:
>> Do we need to do this even when the guest doesn't use Altivec? Can't
>> >> we
>> just load it on demand then once we fault? Th
On 07/03/2013 01:42:12 PM, Alexander Graf wrote:
On 03.07.2013, at 20:28, Scott Wood wrote:
> On 07/03/2013 10:13:57 AM, Alexander Graf wrote:
>> There is no chip that supports SPE and HV at the same time. So
we'll never hit this anyway, since kvmppc_supports_spe() always
returns false on H
On 03.07.2013, at 20:28, Scott Wood wrote:
> On 07/03/2013 10:13:57 AM, Alexander Graf wrote:
>> On 03.07.2013, at 15:53, Caraman Mihai Claudiu-B02008 wrote:
>> >>> -#ifdef CONFIG_SPE
>> >>> case BOOKE_INTERRUPT_SPE_ALTIVEC_UNAVAIL: {
>> >>> -if (vcpu->arch.shared->msr & MSR_SPE)
On 03.07.2013, at 20:37, Scott Wood wrote:
> On 07/03/2013 07:42:36 AM, Mihai Caraman wrote:
>> Increase FPU laziness by calling kvmppc_load_guest_fp() just before
>> returning to guest instead of each sched in. Without this improvement
>> an interrupt may also claim floting point corrupting gues
On 03.07.2013, at 19:44, Scott Wood wrote:
> On 07/03/2013 12:23:16 PM, Alexander Graf wrote:
>> On 03.07.2013, at 19:18, Scott Wood wrote:
>> > On 07/03/2013 07:42:36 AM, Mihai Caraman wrote:
>> >> Increase FPU laziness by calling kvmppc_load_guest_fp() just before
>> >> returning to guest inste
On 07/03/2013 07:42:37 AM, Mihai Caraman wrote:
Add KVM Book3E AltiVec support. KVM Book3E FPU support gracefully
reuse host
infrastructure so follow the same approach for AltiVec.
Signed-off-by: Mihai Caraman
---
arch/powerpc/kvm/booke.c | 72
On 07/03/2013 07:42:36 AM, Mihai Caraman wrote:
Increase FPU laziness by calling kvmppc_load_guest_fp() just before
returning to guest instead of each sched in. Without this improvement
an interrupt may also claim floting point corrupting guest state.
Signed-off-by: Mihai Caraman
---
arch/powe
On 07/03/2013 12:07:30 PM, Alexander Graf wrote:
On 03.07.2013, at 18:49, Caraman Mihai Claudiu-B02008 wrote:
Do we need to do this even when the guest doesn't use Altivec?
Can't
>> we
just load it on demand then once we fault? This code path really
>> should
only be a prefetc
On 07/03/2013 07:11:52 AM, Caraman Mihai Claudiu-B02008 wrote:
> -Original Message-
> From: Wood Scott-B07421
> Sent: Wednesday, June 05, 2013 1:40 AM
> To: Caraman Mihai Claudiu-B02008
> Cc: kvm-...@vger.kernel.org; k...@vger.kernel.org; linuxppc-
> d...@lists.ozlabs.org; Caraman Mihai C
On 07/03/2013 10:13:57 AM, Alexander Graf wrote:
On 03.07.2013, at 15:53, Caraman Mihai Claudiu-B02008 wrote:
>>> -#ifdef CONFIG_SPE
>>>case BOOKE_INTERRUPT_SPE_ALTIVEC_UNAVAIL: {
>>> - if (vcpu->arch.shared->msr & MSR_SPE)
>>> - kvmppc_vcpu_enable_spe(vcpu);
>>>
On 07/03/2013 12:23:16 PM, Alexander Graf wrote:
On 03.07.2013, at 19:18, Scott Wood wrote:
> On 07/03/2013 07:42:36 AM, Mihai Caraman wrote:
>> Increase FPU laziness by calling kvmppc_load_guest_fp() just before
>> returning to guest instead of each sched in. Without this
improvement
>> an
On 03.07.2013, at 19:18, Scott Wood wrote:
> On 07/03/2013 07:42:36 AM, Mihai Caraman wrote:
>> Increase FPU laziness by calling kvmppc_load_guest_fp() just before
>> returning to guest instead of each sched in. Without this improvement
>> an interrupt may also claim floting point corrupting gues
On 03.07.2013, at 19:17, Scott Wood wrote:
> On 07/03/2013 11:59:45 AM, Alexander Graf wrote:
>> On 03.07.2013, at 17:41, Caraman Mihai Claudiu-B02008 wrote:
>> > Increase FPU laziness by calling kvmppc_load_guest_fp() just before
>> > returning to guest instead of each sched in. Without
On 07/03/2013 07:42:36 AM, Mihai Caraman wrote:
Increase FPU laziness by calling kvmppc_load_guest_fp() just before
returning to guest instead of each sched in. Without this improvement
an interrupt may also claim floting point corrupting guest state.
Signed-off-by: Mihai Caraman
---
arch/powe
On 07/03/2013 11:59:45 AM, Alexander Graf wrote:
On 03.07.2013, at 17:41, Caraman Mihai Claudiu-B02008 wrote:
> Increase FPU laziness by calling kvmppc_load_guest_fp() just
before
> returning to guest instead of each sched in. Without this
improvement
> an interrupt may also cla
On 03.07.2013, at 19:07, Scott Wood wrote:
> On 07/03/2013 10:11:50 AM, Alexander Graf wrote:
>> On 03.07.2013, at 15:55, Caraman Mihai Claudiu-B02008 wrote:
>> >> -Original Message-
>> >> From: Alexander Graf [mailto:ag...@suse.de]
>> >> Sent: Wednesday, July 03, 2013 4:45 PM
>> >> To: C
On 03.07.2013, at 18:49, Caraman Mihai Claudiu-B02008 wrote:
> +
> if (!vcpu->arch.sane) {
> kvm_run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
> return -EINVAL;
> @@ -716,6 +750,22 @@ int kvmppc_vcpu_run(struct kvm_run *kvm_run,
struct kvm_vcpu *vcpu)
On 07/03/2013 10:11:50 AM, Alexander Graf wrote:
On 03.07.2013, at 15:55, Caraman Mihai Claudiu-B02008 wrote:
>> -Original Message-
>> From: Alexander Graf [mailto:ag...@suse.de]
>> Sent: Wednesday, July 03, 2013 4:45 PM
>> To: Caraman Mihai Claudiu-B02008
>> Cc: kvm-...@vger.kernel.org
On 07/02/2013 10:47:44 PM, Hongbo Zhang wrote:
On 07/03/2013 07:13 AM, Scott Wood wrote:
Wait a second -- how are we even getting into this code on these new
DMA controllers? All 85xx-family DMA controllers use
fsldma_chan_irq directly.
Right, we are using fsldma_chan_irq, this code never
On 03.07.2013, at 17:41, Caraman Mihai Claudiu-B02008 wrote:
> Increase FPU laziness by calling kvmppc_load_guest_fp() just before
> returning to guest instead of each sched in. Without this improvement
> an interrupt may also claim floting point corrupting guest state.
Not
Add LRAT (Logical to Real Address Translation) error exception handler to
Booke3E 64-bit kernel. LRAT support in KVM will follow afterwards.
Signed-off-by: Mihai Caraman
---
arch/powerpc/include/asm/kvm_asm.h |1 +
arch/powerpc/include/asm/reg_booke.h |1 +
arch/powerpc/kernel/exceptio
With LRAT (Logical to Real Address Translation) error exception handler in
kernel
KVM needs to add the counterpart otherwise will break the build.
Signed-off-by: Mihai Caraman
---
arch/powerpc/kvm/bookehv_interrupts.S |2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/arc
> >>> +
> >>> if (!vcpu->arch.sane) {
> >>> kvm_run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
> >>> return -EINVAL;
> >>> @@ -716,6 +750,22 @@ int kvmppc_vcpu_run(struct kvm_run *kvm_run,
> >> struct kvm_vcpu *vcpu)
> >>> kvmppc_load_guest_fp(vcpu);
> >>> #endif
> >>>
> >>> +#
On 03.07.2013, at 18:09, Caraman Mihai Claudiu-B02008 wrote:
>>> + * Simulate AltiVec unavailable fault to load guest state
>>> + * from thread to AltiVec unit.
>>> + * It requires to be called with preemption disabled.
>>> + */
>>> +static inline void kvmppc_load_guest_altivec(struct kvm_vcpu *v
> > + * Simulate AltiVec unavailable fault to load guest state
> > + * from thread to AltiVec unit.
> > + * It requires to be called with preemption disabled.
> > + */
> > +static inline void kvmppc_load_guest_altivec(struct kvm_vcpu *vcpu)
> > +{
> > + if (kvmppc_supports_altivec()) {
> > +
> >>> Increase FPU laziness by calling kvmppc_load_guest_fp() just before
> >>> returning to guest instead of each sched in. Without this improvement
> >>> an interrupt may also claim floting point corrupting guest state.
> >>
> >> Not sure I follow. Could you please describe exactly what's happeni
On 03.07.2013, at 14:42, Mihai Caraman wrote:
> Add KVM Book3E AltiVec support. KVM Book3E FPU support gracefully reuse host
> infrastructure so follow the same approach for AltiVec.
>
> Signed-off-by: Mihai Caraman
> ---
> arch/powerpc/kvm/booke.c | 72 +++
On 03.07.2013, at 15:53, Caraman Mihai Claudiu-B02008 wrote:
>>> -#ifdef CONFIG_SPE
>>> case BOOKE_INTERRUPT_SPE_ALTIVEC_UNAVAIL: {
>>> - if (vcpu->arch.shared->msr & MSR_SPE)
>>> - kvmppc_vcpu_enable_spe(vcpu);
>>> - else
>>> - kvmppc_b
On 07/03/2013 05:52 PM, Scott Wood wrote:
On 07/03/2013 07:29:43 AM, Tudor Laurentiu wrote:
On 07/02/2013 08:55 PM, Scott Wood wrote:
On 07/02/2013 07:46:29 AM, Laurentiu Tudor wrote:
- insts = of_get_property(hyper_node, "hcall-instructions", &len);
- if (!insts)
- return -ENODEV;
+#if !defin
On 03.07.2013, at 15:55, Caraman Mihai Claudiu-B02008 wrote:
>> -Original Message-
>> From: Alexander Graf [mailto:ag...@suse.de]
>> Sent: Wednesday, July 03, 2013 4:45 PM
>> To: Caraman Mihai Claudiu-B02008
>> Cc: kvm-...@vger.kernel.org; k...@vger.kernel.org; linuxppc-
>> d...@lists.ozl
On 07/03/2013 07:29:43 AM, Tudor Laurentiu wrote:
On 07/02/2013 08:55 PM, Scott Wood wrote:
On 07/02/2013 07:46:29 AM, Laurentiu Tudor wrote:
- insts = of_get_property(hyper_node, "hcall-instructions", &len);
- if (!insts)
- return -ENODEV;
+#if !defined(CONFIG_64BIT) || defined(CONFIG_PPC_BOOK
On Wed, Jul 3, 2013 at 3:10 PM, Rob Herring wrote:
> On 07/03/2013 01:01 AM, Benjamin Herrenschmidt wrote:
>> Commit:
>>
>> e38c0a1fbc5803cbacdaac0557c70ac8ca5152e7
>> of/address: Handle #address-cells > 2 specially
>>
>> broke real time clock access on Bimini, js2x, and similar powerpc
>> ma
At console init, when the kernel tries to flush the log buffer
the ePAPR byte-channel based console write fails silently,
losing the buffered messages.
This happens because The ePAPR para-virtualization init isn't
done early enough so that the hcall instruction to be set,
causing the byte-channel w
On 07/03/2013 01:01 AM, Benjamin Herrenschmidt wrote:
> Commit:
>
> e38c0a1fbc5803cbacdaac0557c70ac8ca5152e7
> of/address: Handle #address-cells > 2 specially
>
> broke real time clock access on Bimini, js2x, and similar powerpc
> machines using the "maple" platform. That code was in
> -Original Message-
> From: Alexander Graf [mailto:ag...@suse.de]
> Sent: Wednesday, July 03, 2013 4:45 PM
> To: Caraman Mihai Claudiu-B02008
> Cc: kvm-...@vger.kernel.org; k...@vger.kernel.org; linuxppc-
> d...@lists.ozlabs.org
> Subject: Re: [PATCH 3/6] KVM: PPC: Book3E: Increase FPU laz
> > -#ifdef CONFIG_SPE
> > case BOOKE_INTERRUPT_SPE_ALTIVEC_UNAVAIL: {
> > - if (vcpu->arch.shared->msr & MSR_SPE)
> > - kvmppc_vcpu_enable_spe(vcpu);
> > - else
> > - kvmppc_booke_queue_irqprio(vcpu,
> > -
> BOOKE_IRQPRIO_SPE_ALTIVEC_UNAV
On 03.07.2013, at 14:42, Mihai Caraman wrote:
> Increase FPU laziness by calling kvmppc_load_guest_fp() just before
> returning to guest instead of each sched in. Without this improvement
> an interrupt may also claim floting point corrupting guest state.
Not sure I follow. Could you please desc
Some exit ids where left out from kvm_exit_names array.
Signed-off-by: Mihai Caraman
---
arch/powerpc/kvm/timing.c |4 +++-
1 files changed, 3 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/kvm/timing.c b/arch/powerpc/kvm/timing.c
index 07b6110..c392d26 100644
--- a/arch/powerpc/kv
Some guests are making use of return from machine check instruction
to do crazy things even though the 64-bit kernel doesn't handle yet
this interrupt. Emulate MCSRR0/1 SPR and rfmci instruction accordingly.
Signed-off-by: Mihai Caraman
---
arch/powerpc/include/asm/kvm_host.h |1 +
arch/powe
On 03.07.2013, at 14:42, Mihai Caraman wrote:
> SPE/FP/AltiVec interrupts share the same numbers. Refactor SPE/FP exit
> handling
> to accommodate AltiVec later. Detect the targeted unit at run time since it
> can
> be configured in the kernel but not featured on hardware.
>
> Signed-off-by: M
Increase FPU laziness by calling kvmppc_load_guest_fp() just before
returning to guest instead of each sched in. Without this improvement
an interrupt may also claim floting point corrupting guest state.
Signed-off-by: Mihai Caraman
---
arch/powerpc/kvm/booke.c |1 +
arch/powerpc/kvm/e500mc
Now that AltiVec support is in place enable e6500 core.
Signed-off-by: Mihai Caraman
---
arch/powerpc/kvm/e500mc.c | 10 ++
1 files changed, 10 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/kvm/e500mc.c b/arch/powerpc/kvm/e500mc.c
index 09da1ac..bec897c 100644
--- a/arch/pow
Add KVM Book3E AltiVec support and enable e6500 core.
Mihai Caraman (6):
KVM: PPC: Book3E: Use common defines for SPE/FP/AltiVec int numbers
KVM: PPC: Book3E: Refactor SPE/FP exit handling
KVM: PPC: Book3E: Increase FPU laziness
KVM: PPC: Book3E: Add AltiVec support
KVM: PPC: Book3E: Add
SPE/FP/AltiVec interrupts share the same numbers. Refactor SPE/FP exit handling
to accommodate AltiVec later. Detect the targeted unit at run time since it can
be configured in the kernel but not featured on hardware.
Signed-off-by: Mihai Caraman
---
arch/powerpc/kvm/booke.c | 102 +
Add KVM Book3E AltiVec support. KVM Book3E FPU support gracefully reuse host
infrastructure so follow the same approach for AltiVec.
Signed-off-by: Mihai Caraman
---
arch/powerpc/kvm/booke.c | 72 -
1 files changed, 70 insertions(+), 2 deletions(-)
Add ONE_REG support for AltiVec on Book3E.
Signed-off-by: Mihai Caraman
---
arch/powerpc/kvm/booke.c | 32
1 files changed, 32 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/kvm/booke.c b/arch/powerpc/kvm/booke.c
index c3c3af6..6ac1f68 100644
--- a/ar
Use common BOOKE_IRQPRIO and BOOKE_INTERRUPT defines for SPE/FP/AltiVec
which share the same interrupts numbers.
Signed-off-by: Mihai Caraman
---
arch/powerpc/kvm/booke.c | 16
arch/powerpc/kvm/booke.h |4 ++--
arch/powerpc/kvm/bookehv_interrupts.
On 07/02/2013 08:55 PM, Scott Wood wrote:
On 07/02/2013 07:46:29 AM, Laurentiu Tudor wrote:
diff --git a/arch/powerpc/kernel/epapr_paravirt.c
b/arch/powerpc/kernel/epapr_paravirt.c
index d44a571..d05f9da 100644
--- a/arch/powerpc/kernel/epapr_paravirt.c
+++ b/arch/powerpc/kernel/epapr_paravirt.c
> So we can remove this hack in kvm_asm.h:
Not yet, this comment was added in the context of AltiVec RFC patches
which intended to remove a similar dependency.
>
> /*
> * TODO: Unify 32-bit and 64-bit kernel exception handlers to use same
> defines
> */
> #define BOOKE_INTERRUPT_SPE_UNAVAIL
> -Original Message-
> From: Wood Scott-B07421
> Sent: Wednesday, June 05, 2013 1:40 AM
> To: Caraman Mihai Claudiu-B02008
> Cc: kvm-...@vger.kernel.org; k...@vger.kernel.org; linuxppc-
> d...@lists.ozlabs.org; Caraman Mihai Claudiu-B02008
> Subject: Re: [RFC PATCH 5/6] KVM: PPC: Book3E: Ad
> -Original Message-
> From: Linuxppc-dev [mailto:linuxppc-dev-
> bounces+varun.sethi=freescale@lists.ozlabs.org] On Behalf Of Tiejun
> Chen
> Sent: Thursday, June 20, 2013 1:23 PM
> To: b...@kernel.crashing.org
> Cc: linuxppc-dev@lists.ozlabs.org; linux-ker...@vger.kernel.org
> Subje
From: "Aneesh Kumar K.V"
The sllp value is stored in mmu_psize_defs in such a way that we can easily OR
the value to get the operand for slbmte instruction. ie, the L and LP bits are
not contiguous. Decode the bits and use them correctly in tlbie.
regression is introduced by 1f6aaaccb1b3af8613fe4
From: "Aneesh Kumar K.V"
We should not fallthrough different case statements in hpte_decode. Add
break statement to break out of the switch. The regression is introduced by
dcda287a9b26309ae43a091d0ecde16f8f61b4c0 "powerpc/mm: Simplify hpte_decode"
Reported-by: Paul Mackerras
Signed-off-by: Ane
On 07/03/2013 11:53 AM, Hongbo Zhang wrote:
hmm...add the devicetree-disc...@lists.ozlabs.org into list.
Note that we are discussing a better naming for this new compatible
property in the corresponding [PATCH 2/2], so I will resend a v2 of
this patch.
On 07/01/2013 11:46 AM, hongbo.zh...@f
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