On Fri, 2013-09-27 at 16:44 -0700, Yinghai Lu wrote:
> > Thus the port driver bails out before calling pci_set_master(). The fix
> > is to call pci_set_master() unconditionally. However that lead me to
> > find to a few interesting oddities in that port driver code:
>
> can we revert that partial
[+ Rafael]
On Fri, Sep 27, 2013 at 4:19 PM, Benjamin Herrenschmidt
wrote:
> On Fri, 2013-09-27 at 15:56 -0700, Yinghai Lu wrote:
>
>> ok, please if you are ok attached one instead. It will print some warning
>> about
>> driver skipping pci_set_master, so we can catch more problem with drivers.
>
On Fri, 2013-09-27 at 15:56 -0700, Yinghai Lu wrote:
> ok, please if you are ok attached one instead. It will print some warning
> about
> driver skipping pci_set_master, so we can catch more problem with drivers.
Except that the message is pretty cryptic :-) Especially since the
driver causing
On Fri, Sep 27, 2013 at 3:38 PM, Benjamin Herrenschmidt
wrote:
> On Fri, 2013-09-27 at 14:54 -0700, Yinghai Lu wrote:
>> On Fri, Sep 27, 2013 at 2:46 PM, Benjamin Herrenschmidt
>> wrote:
>>
>> > Wouldn't it be better to simply have pci_enable_device() always set bus
>> > master on a bridge? I don
On Fri, 2013-09-27 at 14:54 -0700, Yinghai Lu wrote:
> On Fri, Sep 27, 2013 at 2:46 PM, Benjamin Herrenschmidt
> wrote:
>
> > Wouldn't it be better to simply have pci_enable_device() always set bus
> > master on a bridge? I don't see any case where it makes sense to have
> > an enabled bridge wit
On Fri, 2013-09-27 at 10:44 -0700, Yinghai Lu wrote:
> |/* Get and check PCI Express port services */
> |capabilities = get_port_device_capability(dev);
> |if (!capabilities)
> |return 0;
> |
> |pci_set_master(dev);
>
> so how come that pci_set_maste
On Fri, 2013-09-27 at 14:54 -0700, Yinghai Lu wrote:
> On Fri, Sep 27, 2013 at 2:46 PM, Benjamin Herrenschmidt
> wrote:
>
> > Wouldn't it be better to simply have pci_enable_device() always set bus
> > master on a bridge? I don't see any case where it makes sense to have
> > an enabled bridge wit
On Fri, Sep 27, 2013 at 2:46 PM, Benjamin Herrenschmidt
wrote:
> Wouldn't it be better to simply have pci_enable_device() always set bus
> master on a bridge? I don't see any case where it makes sense to have
> an enabled bridge without the master bit set on it...
Do you mean attached?
pci_set
On Fri, 2013-09-27 at 10:10 -0700, Linus Torvalds wrote:
> > So i would like to use the first way that you suggest : call pci_set_master
> > PCIe port driver.
>
> So I have to say, that if we can fix this with just adding a single
> new pci_set_master() call, we should do that before we decide to
On Tue, 2013-09-24 at 10:18 +0200, Christophe Leroy wrote:
> Activating CONFIG_PIN_TLB is supposed to pin the IMMR and the first three
> 8Mbytes pages. But the setting of MD_CTR to a pinnable entry was missing
> before
> the pinning of the third 8Mb page. As the index is decremented module 28
> (M
On Sun, 2013-09-22 at 10:28 +0800, Zhao Qiang wrote:
> P1010rdb-pa and p1010rdb-pb have different phy interrupts.
> So update dts to adapt to both p1010rdb-pa and p1010rdb-pb.
>
> Signed-off-by: Shengzhou Liu
> Signed-off-by: Zhao Qiang
> ---
> arch/powerpc/boot/dts/p1010rdb-pa.dts | 33 +++
On Thu, 2013-09-26 at 22:34 -0500, Wang Dongsheng-B40534 wrote:
>
> > -Original Message-
> > From: Wood Scott-B07421
> > Sent: Friday, September 27, 2013 5:37 AM
> > To: Wang Dongsheng-B40534
> > Cc: Bhushan Bharat-R65777; Wood Scott-B07421; linuxppc-
> > d...@lists.ozlabs.org
> > Subject:
On Fri, Sep 27, 2013 at 9:01 AM, Yinghai Lu wrote:
> On Fri, Sep 27, 2013 at 1:28 AM, Benjamin Herrenschmidt
> wrote:
>> Hi Linus, Yinghai !
>>
>> Please consider reverting:
>>
>> 928bea964827d7824b548c1f8e06eccbbc4d0d7d
>> PCI: Delay enabling bridges until they're needed
>>
>> (I'd suggest to re
On Fri, 2013-09-27 at 12:09 -0500, Kumar Gala wrote:
> On Sep 27, 2013, at 11:15 AM, Scott Wood wrote:
>
> > On Fri, 2013-09-27 at 10:52 -0500, Kumar Gala wrote:
> >> On Sep 26, 2013, at 7:18 PM, Scott Wood wrote:
> >>
> >>> Otherwise, we get a debug traceback due to the use of
> >>> smp_processo
On Wed, 2013-09-25 at 15:40 +0530, Prabhakar Kushwaha wrote:
> The QorIQ T1040/T1042 processor support four integrated 64-bit e5500 PA
> processor cores with high-performance data path acceleration architecture
> and network peripheral interfaces required for networking &
> telecommunications.
>
On Fri, Sep 27, 2013 at 9:01 AM, Yinghai Lu wrote:
>
> So i would like to use the first way that you suggest : call pci_set_master
> PCIe port driver.
So I have to say, that if we can fix this with just adding a single
new pci_set_master() call, we should do that before we decide to
revert.
If o
On Sep 27, 2013, at 11:15 AM, Scott Wood wrote:
> On Fri, 2013-09-27 at 10:52 -0500, Kumar Gala wrote:
>> On Sep 26, 2013, at 7:18 PM, Scott Wood wrote:
>>
>>> Otherwise, we get a debug traceback due to the use of
>>> smp_processor_id() (or get_paca()) inside hard_smp_processor_id().
>>> mpic_ho
On Wed, 2013-09-25 at 04:50 -0500, Xie Xiaobo-R63061 wrote:
> > > +#if defined(CONFIG_SERIAL_QE)
> > > + /* On P1025TWR board, the UCC7 acted as UART port.
> > > + * However, The UCC7's CTS pin is low level in default,
> > > + * it will impact the t
On Thu, 2013-09-26 at 17:37 +0800, Xie Xiaobo wrote:
> +#ifdef CONFIG_QUICC_ENGINE
> +void __init mpc85xx_qe_init(void)
> +{
> + struct device_node *np;
> +
> + np = of_find_compatible_node(NULL, NULL, "fsl,qe");
> + if (!np) {
> + np = of_find_node_by_name(NULL, "qe");
> +
On Wed, 2013-09-18 at 19:02 +0800, Minghuan Lian wrote:
> @@ -592,6 +719,7 @@ int fsl_pci_mcheck_exception(struct pt_regs *regs)
> #if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
>
> struct device_node *fsl_pci_primary;
> +extern const struct of_device_id fsl_pci_ids[];
Externs g
On Fri, 2013-09-27 at 19:29 +0800, Lian Minghuan-b31939 wrote:
> Hi All,
>
> Can anyone comment on my code or help to pick up?
Please break it up into multiple patches, each with one logical change
that is individually explained. It will be much easier to review that
way.
-Scott
On Fri, 2013-09-27 at 10:52 -0500, Kumar Gala wrote:
> On Sep 26, 2013, at 7:18 PM, Scott Wood wrote:
>
> > Otherwise, we get a debug traceback due to the use of
> > smp_processor_id() (or get_paca()) inside hard_smp_processor_id().
> > mpic_host_map() is just looking for a default CPU, so it does
On Fri, Sep 27, 2013 at 1:28 AM, Benjamin Herrenschmidt
wrote:
> Hi Linus, Yinghai !
>
> Please consider reverting:
>
> 928bea964827d7824b548c1f8e06eccbbc4d0d7d
> PCI: Delay enabling bridges until they're needed
>
> (I'd suggest to revert now and maybe merge a better patch later)
>
> This breaks P
On Mon, 2013-08-05 at 20:53 +1000, Benjamin Herrenschmidt wrote:
> On Mon, 2013-08-05 at 12:32 +0200, Michel Dänzer wrote:
> >
> > I did that, sorry should have mentioned that.
> >
> >
> > > > @@ -468,5 +478,3 @@ static struct platform_driver
> > i2c_powermac_driver
> > > > =
> > > > {
> > > >
On Sep 26, 2013, at 7:18 PM, Scott Wood wrote:
> Otherwise, we get a debug traceback due to the use of
> smp_processor_id() (or get_paca()) inside hard_smp_processor_id().
> mpic_host_map() is just looking for a default CPU, so it doesn't matter
> if we migrate after getting the CPU ID.
>
> Sign
On Wed 25 Sep at 19:44:36 +0200 mi...@kernel.org said:
>
> * Timothy Pepper wrote:
>
> > On Wed 25 Sep at 09:30:49 +0200 mi...@kernel.org said:
> > > > info.flags = VM_UNMAPPED_AREA_TOPDOWN;
> > > > info.length = len;
> > > > - info.low_limit = PAGE_SIZE;
> > > > + in
a disabled Kconfig option results in a reference to a not implemented
routine when the IS_ENABLED() macro is used for both conditional
implementation of the routine as well as a C language source code test
at the call site -- the "if (0) func();" construct only gets eliminated
later by the optimize
On Sep 27, 2013, at 8:40 AM, Aida Mynzhasova wrote:
> Currently IEEE 1588 timer reference clock source is determined through
> hard-coded value in gianfar_ptp driver. This patch allows to select ptp
> clock source by means of device tree file node.
>
> For instance:
>
> fsl,cksel = <0>;
>
Previous commit 46723bfa540... introduced a new config option
HAVE_BOOTMEM_INFO_NODE that ended up breaking memory hot-remove for ppc
when sparse vmemmap is not defined.
This patch defines HAVE_BOOTMEM_INFO_NODE for ppc and adds the call to
register_page_bootmem_info_node. Without this we get a BU
Il 27/09/2013 15:13, Aneesh Kumar K.V ha scritto:
> Alexander Graf writes:
>
>> On 27.09.2013, at 12:03, Aneesh Kumar K.V wrote:
>>
>>> From: "Aneesh Kumar K.V"
>>
>> Missing patch description.
>>
>>> Signed-off-by: Aneesh Kumar K.V
>>
>> I fail to see how this really simplifies things, but at
On Fri, 27 Sep 2013 15:59:30 +0200
Laurent Dufour wrote:
> Follow-up to Anton's H_SET_MODE patch, the host should be taken aware
> of guest endianess change.
>
> The hcall H_SET_MODE/H_SET_MODE_RESOURCE_LE is processed in kvm and
> then propagated to the host.
>
Even if it seems a bit odd to g
On 09/26/2013 12:01 PM, Michael Ellerman wrote:
> +int powernv_hwrng_present(void)
> +{
> + return __raw_get_cpu_var(powernv_rng) != NULL;
> +}
> +
> static unsigned long rng_whiten(struct powernv_rng *rng, unsigned long val)
> {
> unsigned long parity;
> @@ -42,6 +48,17 @@ static unsig
Follow-up to Anton's H_SET_MODE patch, the host should be taken aware of
guest endianess change.
The hcall H_SET_MODE/H_SET_MODE_RESOURCE_LE is processed in kvm and then
propagated to the host.
v2: taking in account the Paul Mackerras's comment, using H_TOO_HARD to
propagate only H_SET_MODE_RESOU
Currently IEEE 1588 timer reference clock source is determined through
hard-coded value in gianfar_ptp driver. This patch allows to select ptp
clock source by means of device tree file node.
For instance:
fsl,cksel = <0>;
for using external (TSEC_TMR_CLK input) high precision timer
refer
Alexander Graf writes:
> On 27.09.2013, at 12:03, Aneesh Kumar K.V wrote:
>
>> From: "Aneesh Kumar K.V"
>
> Missing patch description.
>
>> Signed-off-by: Aneesh Kumar K.V
>
> I fail to see how this really simplifies things, but at the end of the
> day it's Gleb's and Paolo's call.
will do. It
Alexander Graf writes:
> On 27.09.2013, at 12:03, Aneesh Kumar K.V wrote:
>
>> diff --git a/arch/powerpc/kvm/book3s_64_mmu_host.c
>> b/arch/powerpc/kvm/book3s_64_mmu_host.c
>> index fd5b393..775d368 100644
>> --- a/arch/powerpc/kvm/book3s_64_mmu_host.c
>> +++ b/arch/powerpc/kvm/book3s_64_mmu_hos
Alexander Graf writes:
> On 27.09.2013, at 12:03, Aneesh Kumar K.V wrote:
>
>> From: "Aneesh Kumar K.V"
>>
>> This patch moves PR related tracepoints to a separate header. This
>> enables in converting PR to a kernel module which will be done in
>> later patches
>>
>> Signed-off-by: Aneesh Kum
Alexander Graf writes:
> On 27.09.2013, at 12:03, Aneesh Kumar K.V wrote:
>
>> From: "Aneesh Kumar K.V"
>>
>> This help us to identify whether we are running with hypervisor mode KVM
>> enabled. The change is needed so that we can have both HV and PR kvm
>> enabled in the same kernel.
>>
>> If
Alexander Graf writes:
> On 27.09.2013, at 12:03, Aneesh Kumar K.V wrote:
>
>> From: "Aneesh Kumar K.V"
>>
>> This moves HV and PR specific functions to kvmppc_ops callback.
>> This is needed so that we can enable HV and PR together in the
>> same kernel. Actual changes to enable both come in t
Alexander Graf writes:
> On 27.09.2013, at 12:03, Aneesh Kumar K.V wrote:
>
>> From: "Aneesh Kumar K.V"
>>
>> This help ups to select the relevant code in the kernel code
>> when we later move HV and PR bits as seperate modules.
>
> I don't think I grasp what semantically the difference between
On 27.09.2013, at 12:03, Aneesh Kumar K.V wrote:
> From: "Aneesh Kumar K.V"
Missing patch description.
> Signed-off-by: Aneesh Kumar K.V
I fail to see how this really simplifies things, but at the end of the day it's
Gleb's and Paolo's call.
Which brings me to the next issue: You forgot to
On 27.09.2013, at 12:03, Aneesh Kumar K.V wrote:
> From: "Aneesh Kumar K.V"
>
> Signed-off-by: Aneesh Kumar K.V
> ---
> arch/powerpc/kvm/Kconfig | 6 +++---
> arch/powerpc/kvm/Makefile | 12
> arch/powerpc/kvm/book3s.c | 19 ++-
>
On 27.09.2013, at 12:03, Aneesh Kumar K.V wrote:
> From: "Aneesh Kumar K.V"
>
> This patch moves PR related tracepoints to a separate header. This
> enables in converting PR to a kernel module which will be done in
> later patches
>
> Signed-off-by: Aneesh Kumar K.V
> ---
> arch/powerpc/kvm/b
On 27.09.2013, at 12:03, Aneesh Kumar K.V wrote:
> From: "Aneesh Kumar K.V"
>
> This help us to identify whether we are running with hypervisor mode KVM
> enabled. The change is needed so that we can have both HV and PR kvm
> enabled in the same kernel.
>
> If both HV and PR KVM are included,
On 27.09.2013, at 12:03, Aneesh Kumar K.V wrote:
> From: "Aneesh Kumar K.V"
>
> This moves HV and PR specific functions to kvmppc_ops callback.
> This is needed so that we can enable HV and PR together in the
> same kernel. Actual changes to enable both come in the later
> patch.This also renam
On 27.09.2013, at 12:03, Aneesh Kumar K.V wrote:
> From: "Aneesh Kumar K.V"
>
> This help ups to select the relevant code in the kernel code
> when we later move HV and PR bits as seperate modules.
I don't think I grasp what semantically the difference between
CONFIG_KVM_BOOK3S_HV and CONFIG_
On 27.09.2013, at 12:03, Aneesh Kumar K.V wrote:
> From: Paul Mackerras
>
> add kvmppc_free_vcores() to free the kvmppc_vcore structures
> that we allocate for a guest, which are currently being leaked.
>
> Signed-off-by: Paul Mackerras
> Signed-off-by: Aneesh Kumar K.V
This one doesn't loo
powerpc/kernel/sysfs.c exports purr with write permission.
This is only valid for kernel in hypervisor mode.
But writing to the file in PowerVM lpar causes crash.
# echo 0 > purr
cpu 0x0: Vector: 700 (Program Check) at [c0d072b0]
pc: c001770c: .write_purr+0x1c/0x40
lr: c000
Hi All,
Can anyone comment on my code or help to pick up?
Thanks,
Minghuan
On 09/18/2013 07:02 PM, Minghuan Lian wrote:
The Freescale's Layerscape series processors will use the same PCI
controller but change cores from PowerPC to ARM. This patch is to
rework FSL PCI driver to support PowerPC
"Aneesh Kumar K.V" writes:
> Hi All,
>
> This patch series support enabling HV and PR KVM together in the same kernel.
> We
> extend machine property with new property "kvm_type". A value of 1 will force
> HV
> KVM and 2 PR KVM. The default value is 0 which will select the fastest KVM
> mode.
From: "Aneesh Kumar K.V"
only hash 64 config we always set memory coherence, If
a platform cannot have memory coherence always set they
can infer that from _PAGE_NO_CACHE and _PAGE_WRITETHRU
like in lpar. So we dont' really need a separate bit
for tracking _PAGE_COHERENCE.
Signed-off-by: Aneesh
From: "Aneesh Kumar K.V"
Even though we have same value for linux PTE bits and hash PTE pits
use the hash pte bits wen updating hash pte
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/platforms/cell/beat_htab.c | 4 ++--
arch/powerpc/platforms/pseries/lpar.c | 2 +-
2 files changed, 3 inse
From: Paul Mackerras
Since the code in book3s_64_vio_hv.c is called from real mode with HV
KVM, and therefore has to be built into the main kernel binary, this
makes it always built-in rather than part of the KVM module. It gets
called from the KVM module by PR KVM, so this adds an EXPORT_SYMBOL
From: "Aneesh Kumar K.V"
This moves HV and PR specific functions to kvmppc_ops callback.
This is needed so that we can enable HV and PR together in the
same kernel. Actual changes to enable both come in the later
patch.This also renames almost all of the symbols that exist in both PR and HV
KVM f
From: "Aneesh Kumar K.V"
This patch moves PR related tracepoints to a separate header. This
enables in converting PR to a kernel module which will be done in
later patches
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/kvm/book3s_64_mmu_host.c | 2 +-
arch/powerpc/kvm/book3s_mmu_hpte.c
From: "Aneesh Kumar K.V"
This moves the kvmppc_ops callbacks to be a per VM entity. This
enables us to select HV and PR mode when creating a VM
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/kvm_host.h | 3 ++
arch/powerpc/include/asm/kvm_ppc.h | 11 --
arch/powerpc/kvm/boo
From: "Aneesh Kumar K.V"
Signed-off-by: Aneesh Kumar K.V
---
arch/arm/kvm/arm.c | 4 ++--
arch/ia64/kvm/kvm-ia64.c | 4 ++--
arch/mips/kvm/kvm_mips.c | 6 ++
arch/powerpc/include/asm/kvm_ppc.h | 2 +-
arch/powerpc/kvm/44x.c | 2 +-
arch/p
From: "Aneesh Kumar K.V"
This help us to identify whether we are running with hypervisor mode KVM
enabled. The change is needed so that we can have both HV and PR kvm
enabled in the same kernel.
If both HV and PR KVM are included, interrupts come in to the HV version
of the kvmppc_interrupt code
From: "Aneesh Kumar K.V"
This help ups to select the relevant code in the kernel code
when we later move HV and PR bits as seperate modules.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/kvm_book3s_64.h | 6 +++---
arch/powerpc/include/asm/kvm_book3s_asm.h | 2 +-
arch/powerp
From: "Aneesh Kumar K.V"
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/kvm/Kconfig | 6 +++---
arch/powerpc/kvm/Makefile | 12
arch/powerpc/kvm/book3s.c | 19 ++-
arch/powerpc/kvm/book3s_64_mmu_host.c | 1 +
arch/powerpc/kvm
Hi All,
This patch series support enabling HV and PR KVM together in the same kernel. We
extend machine property with new property "kvm_type". A value of 1 will force HV
KVM and 2 PR KVM. The default value is 0 which will select the fastest KVM mode.
ie, HV if that is supported otherwise PR.
With
From: Paul Mackerras
This label is not used now.
Signed-off-by: Paul Mackerras
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/kvm/book3s_hv_interrupts.S | 3 ---
arch/powerpc/kvm/book3s_interrupts.S| 3 ---
2 files changed, 6 deletions(-)
diff --git a/arch/powerpc/kvm/book3s_hv_interru
From: "Aneesh Kumar K.V"
This moves /dev/kvm ownership to kvm.ko module. Depending on
which KVM mode we select during VM creation we take a reference
count on respective module
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/kvm_ppc.h | 1 +
arch/powerpc/kvm/book3s.c | 2
From: Paul Mackerras
add kvmppc_free_vcores() to free the kvmppc_vcore structures
that we allocate for a guest, which are currently being leaked.
Signed-off-by: Paul Mackerras
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/kvm/book3s_hv.c | 10 ++
1 file changed, 10 insertions(+)
d
On Thu, Sep 26, 2013 at 10:23:08PM +0200, Rafał Miłecki wrote:
> 2013/9/19 Russell King - ARM Linux :
> > This email is only being sent to the mailing lists in question, not to
> > anyone personally. The list of individuals is far to great to do that.
> > I'm hoping no mailing lists reject the pat
Hi Linus, Yinghai !
Please consider reverting:
928bea964827d7824b548c1f8e06eccbbc4d0d7d
PCI: Delay enabling bridges until they're needed
(I'd suggest to revert now and maybe merge a better patch later)
This breaks PCI on the PowerPC "powernv" platform (which is booted via
kexec) and probably x8
On 26/09/2013 00:31, Paul Mackerras wrote:
> On Wed, Sep 25, 2013 at 02:10:27PM +0200, Laurent Dufour wrote:
>> Follow-up to Anton's H_SET_MODE patch, the host should be taken aware of
>> guest endianess change.
>>
>> The hcall H_SET_MODE is processed in kvm then in the host.
>>
>> Signed-off-by: L
On Fri, 2013-09-27 at 13:32 +0530, Madhavan Srinivasan wrote:
> powerpc/kernel/sysfs.c exports purr with write permission.
> This may be valid for powernv kernel since purr is Hyp resource.
> But writing to the file in PowerVM lpar causes crash.
Testing powernv isn't right, you should test for hyp
powerpc/kernel/sysfs.c exports purr with write permission.
This may be valid for powernv kernel since purr is Hyp resource.
But writing to the file in PowerVM lpar causes crash.
# echo 0 > purr
cpu 0x0: Vector: 700 (Program Check) at [c0d072b0]
pc: c001770c: .write_purr+0x1c/0x
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