[RFC PATCH powerpc] Fix a dma_mask issue of vio
I encountered following issue: [0.283035] ibmvscsi 3015: couldn't initialize event pool [5.688822] ibmvscsi: probe of 3015 failed with error -1 which prevents the storage from being recognized, and the machine from booting. After some digging, it seems that it is caused by commit 4886c399da as dma_mask pointer in viodev-dev is not set, so in dma_set_mask_and_coherent(), dma_set_coherent_mask() is not called because dma_set_mask(), which is dma_set_mask_pSeriesLP() returned EIO. While before the commit, dma_set_coherent_mask() is always called. I tried to replace dma_set_mask_and_coherent() with dma_coerce_mask_and_coherent(), and the machine could boot again. But I'm not sure whether this is the correct fix... --- arch/powerpc/kernel/vio.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/powerpc/kernel/vio.c b/arch/powerpc/kernel/vio.c index e7d0c88..76a6482 100644 --- a/arch/powerpc/kernel/vio.c +++ b/arch/powerpc/kernel/vio.c @@ -1419,7 +1419,7 @@ struct vio_dev *vio_register_device_node(struct device_node *of_node) /* needed to ensure proper operation of coherent allocations * later, in case driver doesn't set it explicitly */ - dma_set_mask_and_coherent(viodev-dev, DMA_BIT_MASK(64)); + dma_coerce_mask_and_coherent(viodev-dev, DMA_BIT_MASK(64)); } /* register with generic device framework */ ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [RFC PATCH powerpc] Fix compiling error in powernv/rng.c
On Tue, 2013-11-19 at 15:04 +1100, Michael Ellerman wrote: On Fri, Nov 15, 2013 at 03:36:04PM +0800, Li Zhong wrote: This is seen when CONFIG_SMP is not enabled: arch/powerpc/platforms/powernv/rng.c: In function 'rng_init_per_cpu': arch/powerpc/platforms/powernv/rng.c:74: error: implicit declaration of function 'cpu_to_chip_id' Hi Li, We try whenever possible to avoid adding #ifdefs in C code. Also on a multi chip system where there are multiple RNGs, your code for UP will not necessarily choose the RNG on the same core as the cpu. OK, thank you for the review, Michael. Just try to make sure I understand it: So even in UP, we could have multiple rng sources, and we should try to use the source which has the same chip_id as the logical cpu? Thanks, Zhong I have a different fix that I will send. cheers ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH] powerpc/gpio: Fix the wrong GPIO input data on MPC8572/MPC8536
On Fri, Nov 15, 2013 at 8:16 AM, Liu Gang gang@freescale.com wrote: For MPC8572/MPC8536, the status of GPIOs defined as output cannot be determined by reading GPDAT register, so the code use shadow data register instead. But if the input pins are asserted high, they will always read high due to the shadow data, even if the pins are set to low. So the input pins should be read directly from GPDAT, not the shadow data. Signed-off-by: Liu Gang gang@freescale.com --- drivers/gpio/gpio-mpc8xxx.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpio/gpio-mpc8xxx.c b/drivers/gpio/gpio-mpc8xxx.c index 9ae29cc..1d4ac75 100644 --- a/drivers/gpio/gpio-mpc8xxx.c +++ b/drivers/gpio/gpio-mpc8xxx.c @@ -71,6 +71,7 @@ static int mpc8572_gpio_get(struct gpio_chip *gc, unsigned int gpio) struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm); val = in_be32(mm-regs + GPIO_DAT) ~in_be32(mm-regs + GPIO_DIR); + mpc8xxx_gc-data = in_be32(mm-regs + GPIO_DIR); return (val | mpc8xxx_gc-data) mpc8xxx_gpio2mask(gpio); } Anatolij, Ben: can either of you take a look at this patch and ACK it if OK? Yours, Linus Walleij ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH RESEND v4] powerpc: kvm: fix rare but potential deadlock scene
On 19.11.2013, at 07:12, Liu Ping Fan kernelf...@gmail.com wrote: Since kvmppc_hv_find_lock_hpte() is called from both virtmode and realmode, so it can trigger the deadlock. Suppose the following scene: Two physical cpuM, cpuN, two VM instances A, B, each VM has a group of vcpus. If on cpuM, vcpu_A_1 holds bitlock X (HPTE_V_HVLOCK), then is switched out, and on cpuN, vcpu_A_2 try to lock X in realmode, then cpuN will be caught in realmode for a long time. What makes things even worse if the following happens, On cpuM, bitlockX is hold, on cpuN, Y is hold. vcpu_B_2 try to lock Y on cpuM in realmode vcpu_A_2 try to lock X on cpuN in realmode Oops! deadlock happens Signed-off-by: Liu Ping Fan pingf...@linux.vnet.ibm.com Any particular reason for the resend? The patch is already applied, no? Alex ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH v3] powerpc: kvm: optimize sc 1 as fast return
On 19.11.2013, at 07:12, Liu Ping Fan kernelf...@gmail.com wrote:
In some scene, e.g openstack CI, PR guest can trigger sc 1 frequently,
this patch optimizes the path by directly delivering BOOK3S_INTERRUPT_SYSCALL
to HV guest, so powernv can return to HV guest without heavy exit, i.e,
no need to swap TLB, HTAB,.. etc
Signed-off-by: Liu Ping Fan pingf...@linux.vnet.ibm.com
---
v3: add some document
This is v4 I think
---
arch/powerpc/kvm/book3s_hv.c| 10 --
arch/powerpc/kvm/book3s_hv_rmhandlers.S | 19 ++-
2 files changed, 22 insertions(+), 7 deletions(-)
diff --git a/arch/powerpc/kvm/book3s_hv.c b/arch/powerpc/kvm/book3s_hv.c
index 62a2b5a..1addb1a 100644
--- a/arch/powerpc/kvm/book3s_hv.c
+++ b/arch/powerpc/kvm/book3s_hv.c
@@ -628,12 +628,10 @@ static int kvmppc_handle_exit(struct kvm_run *run,
struct kvm_vcpu *vcpu,
/* hcall - punt to userspace */
int i;
- if (vcpu-arch.shregs.msr MSR_PR) {
- /* sc 1 from userspace - reflect to guest syscall */
- kvmppc_book3s_queue_irqprio(vcpu,
BOOK3S_INTERRUPT_SYSCALL);
- r = RESUME_GUEST;
- break;
- }
+ /* hypercall with MSR_PR has already been handled in rmode,
+ * and never reaches here.
+ */
It would've been nice to also mention the real mode hypercall handling, but I
can just post a follow-up patch for that one.
Thanks, applied to kvm-ppc-queue.
Alex
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Re: Problem reading and programming memory location...
Hello Anatolij, this is our code, used at University, but again it doesn’t work…
How i told, the only information we have about that reg are:
Chip select 4 specification:
Lp_cs4
bus size: 8 bit
bus control: 2 wait state R/W ACK disabled
size allocated: 4 KByte
Our Register 8 bit LP_cs4 (we want to write)
cs4 offset: 0x001
The code we have used:
——
#define MBAR_BASE 0xF000
#define MALab_MM_START 0x1002U
#define MALab_MM_END 0x1003U
#define MALab_MM_SIZE0x0001U
#define MALab_DEVICE_NAME MALab
int init_module(void) { ...
u16 cs4_start_value;
u16 cs4_stop_value;
u32 cs4_enable_value;
u32 cs0_reg_value;
u32 cs3_reg_value;
u32 ipbi_cr_value;
u32 cs_ctrl_reg_value;
u8 rvoice_ioaddr_value;
// reserve a page of memory for our hardware /proc/iomem
if ( check_region(MALab_MM_START,MALab_MM_SIZE) ) {
printk (KERN_ALERT LED init_module: memory already in use\n);
return -EBUSY;
}
request_region(MALab_MM_START,MALab_MM_SIZE,MALab_DEVICE_NAME);
void __iomem *reg_base = ioremap(MBAR_BASE, 0x400);
void __iomem *cs0_reg = reg_base + 0x0300;
void __iomem *cs1_reg = reg_base + 0x0304;
void __iomem *cs2_reg = reg_base + 0x0308;
void __iomem *cs3_reg = reg_base + 0x030C;
void __iomem *ipbi_cr = reg_base + 0x0054;
void __iomem *cs4_start = reg_base + 0x0024;
void __iomem *cs4_stop = reg_base + 0x0028;
void __iomem *cs4_enable = reg_base + 0x0310;
void __iomem *cs_ctrl_reg = reg_base + 0x0318;
void __iomem *rvoice_ioaddr = ioremap ((volatile unsigned
long)(MALab_MM_START), MALab_MM_SIZE);
printk(KERN_ALERT “r_ioaddr: 0x%08x\n, (u32)rvoice_ioaddr);
//Chip Select 0/Boot Configuration Register: CE=0
cs0_reg_value =in_be32(cs0_reg);
out_be32(cs0_reg, (cs0_reg_value = ~0x0001));
//Chip Select 3 Configuration Register: CE=0
cs3_reg_value =in_be32(cs3_reg);
out_be32(cs3_reg, (cs3_reg_value = ~0x0001));
//enable LocalBus chip select CS4 to hit on our address range
ipbi_cr_value=in_be32(ipbi_cr);
out_be32(ipbi_cr, (ipbi_cr_value = 0x0011));
out_be32(ipbi_cr, (ipbi_cr_value |= 0x0011));
out_be16(cs4_start+2, MALab_MM_START 16);
out_be16(cs4_stop+2, MALab_MM_END 16);
// LocalBus Chip Select 4 Configuration Register
out_be32(cs4_enable, 0x0002DC00);
//Enable Chip Select Control Register
cs_ctrl_reg_value=in_be32(cs_ctrl_reg);
out_be32(cs_ctrl_reg, (cs_ctrl_reg_value |= 0x0100));
//start solution A
rvoice_ioaddr_value=in_8(rvoice_ioaddr);
rvoice_ioaddr_value=0xAA;
printk(A r_ioaddr_value---before : %x \n,in_8(rvoice_ioaddr));
out_8(rvoice_ioaddr, rvoice_ioaddr_value);
printk(A r_ioaddr_value---after : %x \n,in_8(rvoice_ioaddr));
//end solution A
//start solution B
*(volatile u8 *)rvoice_ioaddr = 0xAA;
printk(\n B r_ioaddr_value %x\n,*(volatile u8 *)rvoice_ioaddr);
//end solution B
... }
——
the result is:
rvoice_ioaddr: 0xc908
A rvoice_ioaddr_value---before : 10
A rvoice_ioaddr_value---after : 10
B rvoice_ioaddr_value 10
——
we found some information on this post:
http://linuxppc.10917.n7.nabble.com/MPC5200b-kernel-module-memory-mapping-td59862.html
Thanks again…
Lorenzo
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[PATCH] lib/crc32: slice by 4 is more efficient than the default slice by 8 on Powerpc 8xx.
On PPC_8xx, CRC32_SLICEBY4 is more efficient (almost twice) than CRC32_SLICEBY8, as shown below: With CRC32_SLICEBY8: [1.109204] crc32: CRC_LE_BITS = 64, CRC_BE BITS = 64 [1.114401] crc32: self tests passed, processed 225944 bytes in 15118910 nsec [1.130655] crc32c: CRC_LE_BITS = 64 [1.134235] crc32c: self tests passed, processed 225944 bytes in 4479879 nsec With CRC32_SLICEBY4: [1.097129] crc32: CRC_LE_BITS = 32, CRC_BE BITS = 32 [1.101878] crc32: self tests passed, processed 225944 bytes in 8616242 nsec [1.116298] crc32c: CRC_LE_BITS = 32 [1.119607] crc32c: self tests passed, processed 225944 bytes in 3289576 nsec Signed-off-by: Christophe Leroy christophe.le...@c-s.fr Index: a/lib/Kconfig === --- a/lib/Kconfig (révision 5325) +++ b/lib/Kconfig (copie de travail) @@ -102,6 +102,7 @@ choice prompt CRC32 implementation depends on CRC32 + default CRC32_SLICEBY4 if PPC_8xx default CRC32_SLICEBY8 help This option allows a kernel builder to override the default choice ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH] lib/crc32: slice by 4 is more efficient than the default slice by 8 on Powerpc 8xx.
I found the same on MPC8321 long time ago(when 64 bits change went in), the 32 bits were much faster. I guess the smaller CPUs cannot handle the cache trashing these big tables impose, I didn't look into the details though. So I think this is a good change for 8xx. Acked-by: Joakim Tjernlund joakim.tjernl...@transmode.se Christophe Leroy christophe.le...@c-s.fr wrote on 2013/11/18 08:04:23: From: Christophe Leroy christophe.le...@c-s.fr To: Vitaly Bordug v...@kernel.crashing.org, Marcelo Tosatti marc...@kvack.org, Joakim Tjernlund joakim.tjernl...@transmode.se, Bob Pearson rpear...@systemfabricworks.com, Cc: linux-ker...@vger.kernel.org, linuxppc-dev@lists.ozlabs.org Date: 2013/11/19 13:05 Subject: [PATCH] lib/crc32: slice by 4 is more efficient than the default slice by 8 on Powerpc 8xx. On PPC_8xx, CRC32_SLICEBY4 is more efficient (almost twice) than CRC32_SLICEBY8, as shown below: With CRC32_SLICEBY8: [1.109204] crc32: CRC_LE_BITS = 64, CRC_BE BITS = 64 [1.114401] crc32: self tests passed, processed 225944 bytes in 15118910 nsec [1.130655] crc32c: CRC_LE_BITS = 64 [1.134235] crc32c: self tests passed, processed 225944 bytes in 4479879 nsec With CRC32_SLICEBY4: [1.097129] crc32: CRC_LE_BITS = 32, CRC_BE BITS = 32 [1.101878] crc32: self tests passed, processed 225944 bytes in 8616242 nsec [1.116298] crc32c: CRC_LE_BITS = 32 [1.119607] crc32c: self tests passed, processed 225944 bytes in 3289576 nsec Signed-off-by: Christophe Leroy christophe.le...@c-s.fr Index: a/lib/Kconfig === --- a/lib/Kconfig (révision 5325) +++ b/lib/Kconfig (copie de travail) @@ -102,6 +102,7 @@ choice prompt CRC32 implementation depends on CRC32 + default CRC32_SLICEBY4 if PPC_8xx default CRC32_SLICEBY8 help This option allows a kernel builder to override the default choice ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH] powerpc/gpio: Fix the wrong GPIO input data on MPC8572/MPC8536
On Fri, 15 Nov 2013 15:16:29 +0800 Liu Gang gang@freescale.com wrote: For MPC8572/MPC8536, the status of GPIOs defined as output cannot be determined by reading GPDAT register, so the code use shadow data register instead. But if the input pins are asserted high, they will always read high due to the shadow data, even if the pins are set to low. Could you please add a better description of the problem? I'm having some difficulties to understand the last sentence above. Does the issue appear if some pins were configured as inputs and were asserted high before booting the kernel, and therefore the shadow data has been initialized with these pin values? Or does the issue appear if some pin has been configured as output first and has been set to the high value, then reconfigured as input? Now reading the pin state will always return high even if the actual pin state is low? It seems the issue will appear in both cases. If so, please add this information to the commit message. So the input pins should be read directly from GPDAT, not the shadow data. Signed-off-by: Liu Gang gang@freescale.com --- drivers/gpio/gpio-mpc8xxx.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpio/gpio-mpc8xxx.c b/drivers/gpio/gpio-mpc8xxx.c index 9ae29cc..1d4ac75 100644 --- a/drivers/gpio/gpio-mpc8xxx.c +++ b/drivers/gpio/gpio-mpc8xxx.c @@ -71,6 +71,7 @@ static int mpc8572_gpio_get(struct gpio_chip *gc, unsigned int gpio) struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm); val = in_be32(mm-regs + GPIO_DAT) ~in_be32(mm-regs + GPIO_DIR); + mpc8xxx_gc-data = in_be32(mm-regs + GPIO_DIR); we can reduce one in_be32() call here, i.e. u32 out_mask; ... out_mask = in_be32(mm-regs + GPIO_DIR); val = in_be32(mm-regs + GPIO_DAT) ~out_mask; mpc8xxx_gc-data = out_mask; return (val | mpc8xxx_gc-data) mpc8xxx_gpio2mask(gpio); } Thanks, Anatolij -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: off...@denx.de ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH] lib/crc32: slice by 4 is more efficient than the default slice by 8 on Powerpc 8xx.
I don't think we should go littering the Kconfig with defaults for various bits of hardware -- especially since you've already pointed out non-8xx hardware that would also want this. Put it in defconfig instead, unless you can identify very broad classes of machines for which SLICEBY4 is faster. -Scott On Tue, 2013-11-19 at 15:11 +0100, Joakim Tjernlund wrote: I found the same on MPC8321 long time ago(when 64 bits change went in), the 32 bits were much faster. I guess the smaller CPUs cannot handle the cache trashing these big tables impose, I didn't look into the details though. So I think this is a good change for 8xx. Acked-by: Joakim Tjernlund joakim.tjernl...@transmode.se Christophe Leroy christophe.le...@c-s.fr wrote on 2013/11/18 08:04:23: From: Christophe Leroy christophe.le...@c-s.fr To: Vitaly Bordug v...@kernel.crashing.org, Marcelo Tosatti marc...@kvack.org, Joakim Tjernlund joakim.tjernl...@transmode.se, Bob Pearson rpear...@systemfabricworks.com, Cc: linux-ker...@vger.kernel.org, linuxppc-dev@lists.ozlabs.org Date: 2013/11/19 13:05 Subject: [PATCH] lib/crc32: slice by 4 is more efficient than the default slice by 8 on Powerpc 8xx. On PPC_8xx, CRC32_SLICEBY4 is more efficient (almost twice) than CRC32_SLICEBY8, as shown below: With CRC32_SLICEBY8: [1.109204] crc32: CRC_LE_BITS = 64, CRC_BE BITS = 64 [1.114401] crc32: self tests passed, processed 225944 bytes in 15118910 nsec [1.130655] crc32c: CRC_LE_BITS = 64 [1.134235] crc32c: self tests passed, processed 225944 bytes in 4479879 nsec With CRC32_SLICEBY4: [1.097129] crc32: CRC_LE_BITS = 32, CRC_BE BITS = 32 [1.101878] crc32: self tests passed, processed 225944 bytes in 8616242 nsec [1.116298] crc32c: CRC_LE_BITS = 32 [1.119607] crc32c: self tests passed, processed 225944 bytes in 3289576 nsec Signed-off-by: Christophe Leroy christophe.le...@c-s.fr Index: a/lib/Kconfig === --- a/lib/Kconfig (révision 5325) +++ b/lib/Kconfig (copie de travail) @@ -102,6 +102,7 @@ choice prompt CRC32 implementation depends on CRC32 + default CRC32_SLICEBY4 if PPC_8xx default CRC32_SLICEBY8 help This option allows a kernel builder to override the default choice ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: Problem reading and programming memory location...
Hi Lorenzo, On Tue, 19 Nov 2013 11:20:24 +0100 neorf3k neor...@gmail.com wrote: Hello Anatolij, this is our code, used at University, but again it doesn’t work… How i told, the only information we have about that reg are: Chip select 4 specification: Lp_cs4 bus size: 8 bit bus control: 2 wait state R/W ACK disabled size allocated: 4 KByte Our Register 8 bit LP_cs4 (we want to write) cs4 offset: 0x001 is the byte in FPGA at offset 0x0 writable? In your code you currently test read/write access to the byte at offset 0x0. If the read/write access works under U-Boot, then maybe the chip select parameters for CS4 are configured differently in U-Boot. You can dump the Chip Select 4 configuration registers under U-Boot and compare. Is address- and data-bus to the FPGA multipexed? Another possible reason for non-working access could be that the configured CS4 range 0x1002 - 0x1003 overlaps with configured range for CS0, CS1, CS2 or CS3. Can you verify that no such overlapping exists. Thanks, Anatolij ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH v5 01/17] powerpc/fsl-pci: improve clock API use
On Mon, 2013-11-18 at 00:06 +0100, Gerhard Sittig wrote:
make the Freescale PCI driver get, prepare and enable the PCI clock
during probe(); the clock gets put upon device shutdown by the devm
approach
clock lookup is non-fatal as not all platforms may provide clock specs
in their device tree or implement a device tree based clock provider,
but failure to enable clocks after successful lookup is fatal
the driver appears to not have a remove() routine, so no reference to
the clock is kept during use, and the clock isn't released (the devm
approach will put the clock, but it won't get disabled or unprepared)
the 85xx/86xx platforms go through the probe() routine, where clock
lookup occurs and the clock gets acquired if one was specified; the
512x/83xx platforms don't pass through probe() but instead directly call
the add_bridge() routine at a point in time where the clock provider has
not been setup yet even if the platform implements one -- add comments
to the code paths as a reminder for the potential need of a workaround
in the platform's clock driver, and to keep awareness if code should get
re-arranged or moved
Cc: Benjamin Herrenschmidt b...@kernel.crashing.org
Cc: Paul Mackerras pau...@samba.org
Cc: Kumar Gala ga...@kernel.crashing.org
Cc: linuxppc-dev@lists.ozlabs.org
Signed-off-by: Gerhard Sittig g...@denx.de
---
arch/powerpc/sysdev/fsl_pci.c | 52
+
1 file changed, 52 insertions(+)
Please coordinate this change with Minghuan Lian's patchset (posted Oct
23) to move the bulk of this driver outside of arch/powerpc.
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index ccfb50ddfe38..efa0916f61b6 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -17,6 +17,8 @@
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
+
+#include linux/clk.h
#include linux/kernel.h
#include linux/pci.h
#include linux/delay.h
@@ -755,6 +757,32 @@ int __init mpc83xx_add_bridge(struct device_node *dev)
const int *bus_range;
int primary;
+ /*
+ * 85xx/86xx platforms take the path through the probe() routine
+ * as one would expect, PCI related clocks get acquired there if
+ * specified
+ *
+ * 83xx/512x _don't_ pass through probe(), this add_bridge()
+ * routine instead is called from within .setup_arch() at a
+ * point in time where clock providers haven't been setup yet;
+ * so clocks cannot get acquired here -- lookup would always
+ * fail even on those platforms which implement the provider
+ *
+ * there is no counterpart for add_bridge() just like there is
+ * no remove() counterpart for probe(), so in either case the
+ * PCI related clock won't get released, and all of the
+ * 512x/83xx/85xx/86xx platforms behave in identical ways
How is it identical if 85xx/86xx will acquire a clock in probe(), but
83xx/512x can't acquire it in add_bridge()?
Could you explain the relevance of releasing clocks here?
+ *
+ * this comment is here to keep the balance against the
+ * probe() routine, and as a reminder to acquire clocks if the
+ * add_bridge() call should move to some later point in time
+ *
+ * until then clock providers are expected to work around the
+ * peripheral driver's not acquiring the PCI clock on those
+ * platforms where clock providers exist, while nothing needs to
+ * be done for those platforms without a clock provider
+ */
What would be involved in moving 83xx/512x to use .probe() as well?
is_mpc83xx_pci = 1;
if (!of_device_is_available(dev)) {
@@ -1086,9 +1114,33 @@ void fsl_pci_assign_primary(void)
static int fsl_pci_probe(struct platform_device *pdev)
{
+ struct clk *clk;
int ret;
struct device_node *node;
+ /*
+ * clock lookup is non-fatal since the driver is shared among
+ * platforms and not all of them provide clocks specs in their
+ * device tree, but failure to enable a specified clock is
+ * considered fatal
+ *
+ * note that only the 85xx and 86xx platforms pass through this
+ * probe() routine, while 83xx and 512x directly invoke the
+ * mpc83xx_add_bridge() routine from within .setup_arch() code
+ */
+ clk = devm_clk_get(pdev-dev, ipg);
+ if (!IS_ERR(clk)) {
+ ret = clk_prepare_enable(clk);
+ if (ret) {
+ dev_err(pdev-dev, Could not enable PCI clock\n);
+ return ret;
+ }
+ /*
+ * TODO where to store the 'clk' reference? there appears
+ * to be no remove() routine which undoes what probe() does
+ */
+ }
There is a .remove(); this driver just doesn't support it.
As
Re: [PATCH] powerpc/gpio: Fix the wrong GPIO input data on MPC8572/MPC8536
On Fri, 2013-11-15 at 15:16 +0800, Liu Gang wrote: For MPC8572/MPC8536, the status of GPIOs defined as output cannot be determined by reading GPDAT register, so the code use shadow data register instead. But if the input pins are asserted high, they will always read high due to the shadow data, even if the pins are set to low. So the input pins should be read directly from GPDAT, not the shadow data. Signed-off-by: Liu Gang gang@freescale.com --- drivers/gpio/gpio-mpc8xxx.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpio/gpio-mpc8xxx.c b/drivers/gpio/gpio-mpc8xxx.c index 9ae29cc..1d4ac75 100644 --- a/drivers/gpio/gpio-mpc8xxx.c +++ b/drivers/gpio/gpio-mpc8xxx.c @@ -71,6 +71,7 @@ static int mpc8572_gpio_get(struct gpio_chip *gc, unsigned int gpio) struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm); val = in_be32(mm-regs + GPIO_DAT) ~in_be32(mm-regs + GPIO_DIR); + mpc8xxx_gc-data = in_be32(mm-regs + GPIO_DIR); return (val | mpc8xxx_gc-data) mpc8xxx_gpio2mask(gpio); } It seems odd to update -data in a function that's supposed to be reading things... Perhaps it would be better to keep -data in a good state from the beginning. -Scott ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH v2] panic: Make panic_timeout configurable
On 11/19/2013 02:09 AM, Ingo Molnar wrote: * Jason Baron jba...@akamai.com wrote: On 11/18/2013 05:30 PM, Andrew Morton wrote: On Mon, 18 Nov 2013 21:04:36 + (GMT) Jason Baron jba...@akamai.com wrote: The panic_timeout value can be set via the command line option 'panic=x', or via /proc/sys/kernel/panic, however that is not sufficient when the panic occurs before we are able to set up these values. Thus, add a CONFIG_PANIC_TIMEOUT so that we can set the desired value from the .config. The default panic_timeout value continues to be 0 - wait forever, except for powerpc and mips, which have been defaulted to 180 and 5 respectively. This is in keeping with the fact that these arches already set panic_timeout in their arch init code. However, I found three exceptions- two in mips and one in powerpc where the settings didn't match these default values. In those cases, I left the arch code so it continues to override, in case the user has not changed from the default. It would nice if these arches had one default value, or if we could determine the correct setting at compile-time. Felipe is proposing a simpler patch (panic: setup panic_timeout early) which switches to early_param(). Is that sufficient for the (undescribed!) failure which you are presumably observing? No - that patch doesn't change the 'panic_timeout' value until the call to 'parse_early_param()' is made. If there is a panic before that point, the param doesn't do anything. The idea of this patch is to allow it to be configured at build-time. I've tested the patch by simply inserting a panic() call at the beginning of 'start_kernel()'. So, no I do not have a specific panic in mind for this. Would you be interested in picking up Felipe's patch/fix on top of yours? I was unable to communicate with him efficiently, but I'd take the patch if it's signed off by you. Thanks, Ingo Sure, I can round up all the related patches in this area that make sense and re-submit as a series. Felipe, would the CONFIG_PANIC_TIMEOUT=xx .config parameter work for your needs, or would you still like to see the command-line processing moved up? I'd also like to hear from the PowerPC folks about the arch defaults there. Now, that mips is ok with CONFIG_PANIC_TIMEOUT, PowerPC is the only arch doing specific initialization of 'panic_timeout'. Thanks, -Jason ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH] lib/crc32: slice by 4 is more efficient than the default slice by 8 on Powerpc 8xx.
Scott Wood scottw...@freescale.com wrote on 2013/11/19 19:29:26: I don't think we should go littering the Kconfig with defaults for various bits of hardware -- especially since you've already pointed out non-8xx hardware that would also want this. Put it in defconfig instead, unless you can identify very broad classes of machines for which SLICEBY4 is faster. hmm, when 64bits went in there was not much proof that it was faster for a wide range of CPU, just 2 or 3 if I recall correctly. I suspect there are quite a few CPUs where 32 bits a equal or faster. Jocke -Scott On Tue, 2013-11-19 at 15:11 +0100, Joakim Tjernlund wrote: I found the same on MPC8321 long time ago(when 64 bits change went in), the 32 bits were much faster. I guess the smaller CPUs cannot handle the cache trashing these big tables impose, I didn't look into the details though. So I think this is a good change for 8xx. Acked-by: Joakim Tjernlund joakim.tjernl...@transmode.se Christophe Leroy christophe.le...@c-s.fr wrote on 2013/11/18 08:04:23: From: Christophe Leroy christophe.le...@c-s.fr To: Vitaly Bordug v...@kernel.crashing.org, Marcelo Tosatti marc...@kvack.org, Joakim Tjernlund joakim.tjernl...@transmode.se, Bob Pearson rpear...@systemfabricworks.com, Cc: linux-ker...@vger.kernel.org, linuxppc-dev@lists.ozlabs.org Date: 2013/11/19 13:05 Subject: [PATCH] lib/crc32: slice by 4 is more efficient than the default slice by 8 on Powerpc 8xx. On PPC_8xx, CRC32_SLICEBY4 is more efficient (almost twice) than CRC32_SLICEBY8, as shown below: With CRC32_SLICEBY8: [1.109204] crc32: CRC_LE_BITS = 64, CRC_BE BITS = 64 [1.114401] crc32: self tests passed, processed 225944 bytes in 15118910 nsec [1.130655] crc32c: CRC_LE_BITS = 64 [1.134235] crc32c: self tests passed, processed 225944 bytes in 4479879 nsec With CRC32_SLICEBY4: [1.097129] crc32: CRC_LE_BITS = 32, CRC_BE BITS = 32 [1.101878] crc32: self tests passed, processed 225944 bytes in 8616242 nsec [1.116298] crc32c: CRC_LE_BITS = 32 [1.119607] crc32c: self tests passed, processed 225944 bytes in 3289576 nsec Signed-off-by: Christophe Leroy christophe.le...@c-s.fr Index: a/lib/Kconfig === --- a/lib/Kconfig (révision 5325) +++ b/lib/Kconfig (copie de travail) @@ -102,6 +102,7 @@ choice prompt CRC32 implementation depends on CRC32 + default CRC32_SLICEBY4 if PPC_8xx default CRC32_SLICEBY8 help This option allows a kernel builder to override the default choice ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH] lib/crc32: slice by 4 is more efficient than the default slice by 8 on Powerpc 8xx.
On Wed, 2013-11-20 at 00:39 +0100, Joakim Tjernlund wrote: Scott Wood scottw...@freescale.com wrote on 2013/11/19 19:29:26: I don't think we should go littering the Kconfig with defaults for various bits of hardware -- especially since you've already pointed out non-8xx hardware that would also want this. Put it in defconfig instead, unless you can identify very broad classes of machines for which SLICEBY4 is faster. hmm, when 64bits went in there was not much proof that it was faster for a wide range of CPU, just 2 or 3 if I recall correctly. I suspect there are quite a few CPUs where 32 bits a equal or faster. That may be the case, but I don't think we want a big list of them in lib/Kconfig. Whether the default should change (for all targets that don't override it in defconfig, or at least for some broader category such as all 32-bit chips) is a different discussion. -Scott ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH 2/2] powerpc/pseries: Fix SMP=n build of rng.c
In commit a489043 Implement arch_get_random_long() based on H_RANDOM I broke the SMP=n build. We were getting plpar_wrappers.h via spinlock.h which breaks when SMP=n. Signed-off-by: Michael Ellerman m...@ellerman.id.au --- arch/powerpc/platforms/pseries/rng.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/powerpc/platforms/pseries/rng.c b/arch/powerpc/platforms/pseries/rng.c index a702f1c..72a1027 100644 --- a/arch/powerpc/platforms/pseries/rng.c +++ b/arch/powerpc/platforms/pseries/rng.c @@ -13,6 +13,7 @@ #include linux/of.h #include asm/archrandom.h #include asm/machdep.h +#include asm/plpar_wrappers.h static int pseries_get_random_long(unsigned long *v) -- 1.8.3.2 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH 1/2] powerpc: Make cpu_to_chip_id() available when SMP=n
Up until now we have only used cpu_to_chip_id() in the topology code,
which is only used on SMP builds. However my recent commit a4da0d5
Implement arch_get_random_long/int() for powernv added a usage when
SMP=n, breaking the build.
Move cpu_to_chip_id() into prom.c so it is available for SMP=n builds.
We would move the extern to prom.h, but that breaks the include in
topology.h. Instead we leave it in smp.h, but move it out of the
CONFIG_SMP #ifdef. We also need to include asm/smp.h in rng.c, because
the linux version skips asm/smp.h on UP. What a mess.
Signed-off-by: Michael Ellerman m...@ellerman.id.au
---
arch/powerpc/include/asm/smp.h | 2 +-
arch/powerpc/kernel/prom.c | 20
arch/powerpc/kernel/smp.c| 16
arch/powerpc/platforms/powernv/rng.c | 1 +
4 files changed, 22 insertions(+), 17 deletions(-)
diff --git a/arch/powerpc/include/asm/smp.h b/arch/powerpc/include/asm/smp.h
index 98da78e..084e080 100644
--- a/arch/powerpc/include/asm/smp.h
+++ b/arch/powerpc/include/asm/smp.h
@@ -33,6 +33,7 @@ extern int boot_cpuid;
extern int spinning_secondaries;
extern void cpu_die(void);
+extern int cpu_to_chip_id(int cpu);
#ifdef CONFIG_SMP
@@ -112,7 +113,6 @@ static inline struct cpumask *cpu_core_mask(int cpu)
}
extern int cpu_to_core_id(int cpu);
-extern int cpu_to_chip_id(int cpu);
/* Since OpenPIC has only 4 IPIs, we use slightly different message numbers.
*
diff --git a/arch/powerpc/kernel/prom.c b/arch/powerpc/kernel/prom.c
index 4432fd8..67a7b3b 100644
--- a/arch/powerpc/kernel/prom.c
+++ b/arch/powerpc/kernel/prom.c
@@ -786,6 +786,26 @@ int of_get_ibm_chip_id(struct device_node *np)
return -1;
}
+/**
+ * cpu_to_chip_id - Return the cpus chip-id
+ * @cpu: The logical cpu number.
+ *
+ * Return the value of the ibm,chip-id property corresponding to the given
+ * logical cpu number. If the chip-id can not be found, returns -1.
+ */
+int cpu_to_chip_id(int cpu)
+{
+ struct device_node *np;
+
+ np = of_get_cpu_node(cpu, NULL);
+ if (!np)
+ return -1;
+
+ of_node_put(np);
+ return of_get_ibm_chip_id(np);
+}
+EXPORT_SYMBOL(cpu_to_chip_id);
+
#ifdef CONFIG_PPC_PSERIES
/*
* Fix up the uninitialized fields in a new device node:
diff --git a/arch/powerpc/kernel/smp.c b/arch/powerpc/kernel/smp.c
index 8e59abc..e5174d3 100644
--- a/arch/powerpc/kernel/smp.c
+++ b/arch/powerpc/kernel/smp.c
@@ -597,22 +597,6 @@ out:
return id;
}
-/* Return the value of the chip-id property corresponding
- * to the given logical cpu.
- */
-int cpu_to_chip_id(int cpu)
-{
- struct device_node *np;
-
- np = of_get_cpu_node(cpu, NULL);
- if (!np)
- return -1;
-
- of_node_put(np);
- return of_get_ibm_chip_id(np);
-}
-EXPORT_SYMBOL(cpu_to_chip_id);
-
/* Helper routines for cpu to core mapping */
int cpu_core_index_of_thread(int cpu)
{
diff --git a/arch/powerpc/platforms/powernv/rng.c
b/arch/powerpc/platforms/powernv/rng.c
index 8844628..1cb160d 100644
--- a/arch/powerpc/platforms/powernv/rng.c
+++ b/arch/powerpc/platforms/powernv/rng.c
@@ -19,6 +19,7 @@
#include asm/io.h
#include asm/prom.h
#include asm/machdep.h
+#include asm/smp.h
struct powernv_rng {
--
1.8.3.2
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Re: [RFC PATCH powerpc] Fix a dma_mask issue of vio
On Tue, 2013-11-19 at 16:11 +0800, Li Zhong wrote: I encountered following issue: [0.283035] ibmvscsi 3015: couldn't initialize event pool [5.688822] ibmvscsi: probe of 3015 failed with error -1 which prevents the storage from being recognized, and the machine from booting. After some digging, it seems that it is caused by commit 4886c399da as dma_mask pointer in viodev-dev is not set, so in dma_set_mask_and_coherent(), dma_set_coherent_mask() is not called because dma_set_mask(), which is dma_set_mask_pSeriesLP() returned EIO. While before the commit, dma_set_coherent_mask() is always called. I tried to replace dma_set_mask_and_coherent() with dma_coerce_mask_and_coherent(), and the machine could boot again. But I'm not sure whether this is the correct fix... Russell, care to chime in ? I can't make sense of the semantics... The original commit was fairly clear: Replace the following sequence: dma_set_mask(dev, mask); dma_set_coherent_mask(dev, mask); with a call to the new helper dma_set_mask_and_coherent(). It all makes sense so far ... but doesn't work for some odd reason, and the fix uses a function whose name doesn't make much sense to me ... what is the difference between setting and coercing the mask ? And why doe replacing two set with a set both doesn't work and require a coerce ? I'm asking because I'm worried about breakage elsewhere... Cheers, Ben. --- arch/powerpc/kernel/vio.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/powerpc/kernel/vio.c b/arch/powerpc/kernel/vio.c index e7d0c88..76a6482 100644 --- a/arch/powerpc/kernel/vio.c +++ b/arch/powerpc/kernel/vio.c @@ -1419,7 +1419,7 @@ struct vio_dev *vio_register_device_node(struct device_node *of_node) /* needed to ensure proper operation of coherent allocations * later, in case driver doesn't set it explicitly */ - dma_set_mask_and_coherent(viodev-dev, DMA_BIT_MASK(64)); + dma_coerce_mask_and_coherent(viodev-dev, DMA_BIT_MASK(64)); } /* register with generic device framework */ ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [RFC PATCH powerpc] Fix a dma_mask issue of vio
On Wed, 2013-11-20 at 12:28 +1100, Benjamin Herrenschmidt wrote:
On Tue, 2013-11-19 at 16:11 +0800, Li Zhong wrote:
I encountered following issue:
[0.283035] ibmvscsi 3015: couldn't initialize event pool
[5.688822] ibmvscsi: probe of 3015 failed with error -1
which prevents the storage from being recognized, and the machine from
booting.
After some digging, it seems that it is caused by commit 4886c399da
as dma_mask pointer in viodev-dev is not set, so in
dma_set_mask_and_coherent(), dma_set_coherent_mask() is not called
because dma_set_mask(), which is dma_set_mask_pSeriesLP() returned EIO.
While before the commit, dma_set_coherent_mask() is always called.
I tried to replace dma_set_mask_and_coherent() with
dma_coerce_mask_and_coherent(), and the machine could boot again.
But I'm not sure whether this is the correct fix...
Russell, care to chime in ? I can't make sense of the semantics...
The original commit was fairly clear:
Replace the following sequence:
dma_set_mask(dev, mask);
dma_set_coherent_mask(dev, mask);
with a call to the new helper dma_set_mask_and_coherent().
It all makes sense so far ... but doesn't work for some odd reason,
and the fix uses a function whose name doesn't make much sense to
me ... what is the difference between setting and coercing
the mask ? And why doe replacing two set with a set both doesn't
work and require a coerce ?
I think the difference is because the check of return value from
dma_set_mask in dma_coerce_mask_and_coherent():
--
int rc = dma_set_mask(dev, mask);
if (rc == 0)
dma_set_coherent_mask(dev, mask);
--
and in struct device {, dma_mask is a pointer, while coherent_dma_mask
is value (don't know why we have this difference).
And here for pseries, dma_set_mask() failed because the dma_mask pointer
still remains null.
And in dma_coerce_mask_and_coherent(), the dma_mask is set with the
address of coherent_dma_mask
--
dev-dma_mask = dev-coherent_dma_mask;
--
Thanks, Zhong
I'm asking because I'm worried about breakage elsewhere...
Cheers,
Ben.
---
arch/powerpc/kernel/vio.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/kernel/vio.c b/arch/powerpc/kernel/vio.c
index e7d0c88..76a6482 100644
--- a/arch/powerpc/kernel/vio.c
+++ b/arch/powerpc/kernel/vio.c
@@ -1419,7 +1419,7 @@ struct vio_dev *vio_register_device_node(struct
device_node *of_node)
/* needed to ensure proper operation of coherent allocations
* later, in case driver doesn't set it explicitly */
- dma_set_mask_and_coherent(viodev-dev, DMA_BIT_MASK(64));
+ dma_coerce_mask_and_coherent(viodev-dev, DMA_BIT_MASK(64));
}
/* register with generic device framework */
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Re: [PATCH] powerpc/gpio: Fix the wrong GPIO input data on MPC8572/MPC8536
On Tue, 2013-11-19 at 16:32 +0100, Anatolij Gustschin wrote: On Fri, 15 Nov 2013 15:16:29 +0800 Liu Gang gang@freescale.com wrote: For MPC8572/MPC8536, the status of GPIOs defined as output cannot be determined by reading GPDAT register, so the code use shadow data register instead. But if the input pins are asserted high, they will always read high due to the shadow data, even if the pins are set to low. Could you please add a better description of the problem? I'm having some difficulties to understand the last sentence above. Does the issue appear if some pins were configured as inputs and were asserted high before booting the kernel, and therefore the shadow data has been initialized with these pin values? Or does the issue appear if some pin has been configured as output first and has been set to the high value, then reconfigured as input? Now reading the pin state will always return high even if the actual pin state is low? It seems the issue will appear in both cases. If so, please add this information to the commit message. Yes, you are right. I'll updated the description more clear. val = in_be32(mm-regs + GPIO_DAT) ~in_be32(mm-regs + GPIO_DIR); + mpc8xxx_gc-data = in_be32(mm-regs + GPIO_DIR); we can reduce one in_be32() call here, i.e. u32 out_mask; ... out_mask = in_be32(mm-regs + GPIO_DIR); val = in_be32(mm-regs + GPIO_DAT) ~out_mask; mpc8xxx_gc-data = out_mask; return (val | mpc8xxx_gc-data) mpc8xxx_gpio2mask(gpio); } Thanks, Anatolij Granted, it will be better to reduce one in_be32() call. I'll improve the method based on your and Scott's comments. Thanks Liu Gang ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH RESEND v4] powerpc: kvm: fix rare but potential deadlock scene
On Tue, Nov 19, 2013 at 6:39 PM, Alexander Graf ag...@suse.de wrote: On 19.11.2013, at 07:12, Liu Ping Fan kernelf...@gmail.com wrote: Since kvmppc_hv_find_lock_hpte() is called from both virtmode and realmode, so it can trigger the deadlock. Suppose the following scene: Two physical cpuM, cpuN, two VM instances A, B, each VM has a group of vcpus. If on cpuM, vcpu_A_1 holds bitlock X (HPTE_V_HVLOCK), then is switched out, and on cpuN, vcpu_A_2 try to lock X in realmode, then cpuN will be caught in realmode for a long time. What makes things even worse if the following happens, On cpuM, bitlockX is hold, on cpuN, Y is hold. vcpu_B_2 try to lock Y on cpuM in realmode vcpu_A_2 try to lock X on cpuN in realmode Oops! deadlock happens Signed-off-by: Liu Ping Fan pingf...@linux.vnet.ibm.com Any particular reason for the resend? The patch is already applied, no? Oh, seems that I misunderstood your meaning. You said Actually, I've changed my mind and moved the patch to the for-3.13 branch instead. Please make sure to CC kvm@vger on all patches you submit though. So I think it is necessary to resend with cc kvm@vger Regards, Pingfan ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH] powerpc/gpio: Fix the wrong GPIO input data on MPC8572/MPC8536
On Tue, 2013-11-19 at 16:51 -0600, Scott Wood wrote: @@ -71,6 +71,7 @@ static int mpc8572_gpio_get(struct gpio_chip *gc, unsigned int gpio) struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm); val = in_be32(mm-regs + GPIO_DAT) ~in_be32(mm-regs + GPIO_DIR); + mpc8xxx_gc-data = in_be32(mm-regs + GPIO_DIR); return (val | mpc8xxx_gc-data) mpc8xxx_gpio2mask(gpio); } It seems odd to update -data in a function that's supposed to be reading things... Perhaps it would be better to keep -data in a good state from the beginning. -Scott Yes, keeping the -data in a good state from the beginning will be better. But this will need more code in different functions to cover all the scenarios. First, we should check the direct of the pin in the function mpc8xxx_gpio_set, and clean the input bit in -data after setting operation. In addition, we may change a output pin to input and then read the input status. So we also should update the -data in mpc8xxx_gpio_dir_in function. So maybe it's better to eliminate the effects of the -data to the input pins when reading the status, regardless of the possible changes of the pins and the data. Do you think so? Best Regards, Liu Gang ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
RE: [PATCHv2 1/8] ALSA: Add SAI SoC Digital Audio Interface driver.
The udelay just doesn't make sense to what you are talking about.
Does SAI really need 10us delay between two register-updating?
No, this is not must be.
We basically use udelay only if the IP hardware actually needs it: some
IP needs time to boot itself up after doing software reset for example.
But it doesn't look reasonable to me by using udelay to make sure the
last enabled.
And from the 'Synchronous mode' you just provided, there're another issue:
+ case SNDRV_PCM_TRIGGER_START:
+ case SNDRV_PCM_TRIGGER_RESUME:
+ case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
+ tcsr |= FSL_SAI_CSR_TERE;
+ rcsr |= FSL_SAI_CSR_TERE;
+ writel(rcsr, sai-base + FSL_SAI_RCSR);
+ udelay(10);
+ writel(tcsr, sai-base + FSL_SAI_TCSR);
+ break;
+
+ case SNDRV_PCM_TRIGGER_STOP:
+ case SNDRV_PCM_TRIGGER_SUSPEND:
+ case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
+ if (!(dai-playback_active || dai-capture_active)) {
+ tcsr = ~FSL_SAI_CSR_TERE;
+ rcsr = ~FSL_SAI_CSR_TERE;
+ }
+ writel(rcsr, sai-base + FSL_SAI_RCSR);
+ udelay(10);
+ writel(tcsr, sai-base + FSL_SAI_TCSR);
+ break;
ISSUE 1: You might make sure transmitter is the last enabled.
However, it's not the first disabled. Is this okay?
Yes, this is just programming mistake. I'll revise it.
In this case the transmitter should be the last enabled and the first disabled.
ISSUE 2: There are two cases listed in 'Synchronous mode'.
However, your driver doesn't take care of them.
The SAI's synchronous mode looks like more flexible
than SSI's. The driver needs to be more sophisticated
so that it can handle multiple cases when TX/RX clocks
are controlled by either TX or RX, and surely, the
asynchronous mode as well.
Because in Vybrid the transmitter bit clock and frame sync are to be used by
both the transmitter and receiver, and only this case can be used here, so now
I only handle this case.
And there's another personal tip: I think you can first try to focus on
this SAI driver and pend the others. There might be two many things you
need to refine if you are doing them at the same time.
I'll implement them later if needed.
--
Best Regards,
Xiubo
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Re: [PATCHv2 1/8] ALSA: Add SAI SoC Digital Audio Interface driver.
On Wed, Nov 20, 2013 at 11:37:45AM +0800, Xiubo Li-B47053 wrote:
The udelay just doesn't make sense to what you are talking about.
Does SAI really need 10us delay between two register-updating?
No, this is not must be.
Then you should explain in your comments why you really put it here or just
drop it if it's just a mistake.
We basically use udelay only if the IP hardware actually needs it: some
IP needs time to boot itself up after doing software reset for example.
But it doesn't look reasonable to me by using udelay to make sure the
last enabled.
And from the 'Synchronous mode' you just provided, there're another issue:
+ case SNDRV_PCM_TRIGGER_START:
+ case SNDRV_PCM_TRIGGER_RESUME:
+ case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
+ tcsr |= FSL_SAI_CSR_TERE;
+ rcsr |= FSL_SAI_CSR_TERE;
+ writel(rcsr, sai-base + FSL_SAI_RCSR);
+ udelay(10);
+ writel(tcsr, sai-base + FSL_SAI_TCSR);
+ break;
+
+ case SNDRV_PCM_TRIGGER_STOP:
+ case SNDRV_PCM_TRIGGER_SUSPEND:
+ case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
+ if (!(dai-playback_active || dai-capture_active)) {
+ tcsr = ~FSL_SAI_CSR_TERE;
+ rcsr = ~FSL_SAI_CSR_TERE;
+ }
+ writel(rcsr, sai-base + FSL_SAI_RCSR);
+ udelay(10);
+ writel(tcsr, sai-base + FSL_SAI_TCSR);
+ break;
ISSUE 1: You might make sure transmitter is the last enabled.
However, it's not the first disabled. Is this okay?
Yes, this is just programming mistake. I'll revise it.
In this case the transmitter should be the last enabled and the first
disabled.
ISSUE 2: There are two cases listed in 'Synchronous mode'.
However, your driver doesn't take care of them.
The SAI's synchronous mode looks like more flexible
than SSI's. The driver needs to be more sophisticated
so that it can handle multiple cases when TX/RX clocks
are controlled by either TX or RX, and surely, the
asynchronous mode as well.
Because in Vybrid the transmitter bit clock and frame sync are to be used by
both the transmitter and receiver, and only this case can be used here, so
now I only handle this case.
It's fairly okay if adding explicit comments to indicate that currently the
driver only supports its Synchronous mode with clocks controlled by TX only.
Best,
Nicolin Chen
And there's another personal tip: I think you can first try to focus on
this SAI driver and pend the others. There might be two many things you
need to refine if you are doing them at the same time.
I'll implement them later if needed.
--
Best Regards,
Xiubo
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[PATCH 24/34] PCI: use weak functions for MSI arch-specific functions
From: Thomas Petazzoni thomas.petazz...@free-electrons.com
Until now, the MSI architecture-specific functions could be overloaded
using a fairly complex set of #define and compile-time
conditionals. In order to prepare for the introduction of the msi_chip
infrastructure, it is desirable to switch all those functions to use
the 'weak' mechanism. This commit converts all the architectures that
were overidding those MSI functions to use the new strategy.
Note that we keep two separate, non-weak, functions
default_teardown_msi_irqs() and default_restore_msi_irqs() for the
default behavior of the arch_teardown_msi_irqs() and
arch_restore_msi_irqs(), as the default behavior is needed by x86 PCI
code.
Signed-off-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
Acked-by: Bjorn Helgaas bhelg...@google.com
Acked-by: Benjamin Herrenschmidt b...@kernel.crashing.org
Tested-by: Daniel Price daniel.pr...@gmail.com
Tested-by: Thierry Reding thierry.red...@gmail.com
Cc: Benjamin Herrenschmidt b...@kernel.crashing.org
Cc: Paul Mackerras pau...@samba.org
Cc: linuxppc-dev@lists.ozlabs.org
Cc: Martin Schwidefsky schwidef...@de.ibm.com
Cc: Heiko Carstens heiko.carst...@de.ibm.com
Cc: linux...@de.ibm.com
Cc: linux-s...@vger.kernel.org
Cc: Thomas Gleixner t...@linutronix.de
Cc: Ingo Molnar mi...@redhat.com
Cc: H. Peter Anvin h...@zytor.com
Cc: x...@kernel.org
Cc: Russell King li...@arm.linux.org.uk
Cc: Tony Luck tony.l...@intel.com
Cc: Fenghua Yu fenghua...@intel.com
Cc: linux-i...@vger.kernel.org
Cc: Ralf Baechle r...@linux-mips.org
Cc: linux-m...@linux-mips.org
Cc: David S. Miller da...@davemloft.net
Cc: sparcli...@vger.kernel.org
Cc: Chris Metcalf cmetc...@tilera.com
Signed-off-by: Jason Cooper ja...@lakedaemon.net
---
arch/mips/include/asm/pci.h|5
arch/powerpc/include/asm/pci.h |5
arch/s390/include/asm/pci.h|4 ---
arch/x86/include/asm/pci.h | 30 -
arch/x86/kernel/x86_init.c | 24
drivers/pci/msi.c | 48
include/linux/msi.h|8 +-
7 files changed, 55 insertions(+), 69 deletions(-)
diff --git a/arch/mips/include/asm/pci.h b/arch/mips/include/asm/pci.h
index b8e24fd..031f4c1 100644
--- a/arch/mips/include/asm/pci.h
+++ b/arch/mips/include/asm/pci.h
@@ -137,11 +137,6 @@ static inline int pci_get_legacy_ide_irq(struct pci_dev
*dev, int channel)
return channel ? 15 : 14;
}
-#ifdef CONFIG_CPU_CAVIUM_OCTEON
-/* MSI arch hook for OCTEON */
-#define arch_setup_msi_irqs arch_setup_msi_irqs
-#endif
-
extern char * (*pcibios_plat_setup)(char *str);
#ifdef CONFIG_OF
diff --git a/arch/powerpc/include/asm/pci.h b/arch/powerpc/include/asm/pci.h
index 6653f27..95145a1 100644
--- a/arch/powerpc/include/asm/pci.h
+++ b/arch/powerpc/include/asm/pci.h
@@ -113,11 +113,6 @@ extern int pci_domain_nr(struct pci_bus *bus);
/* Decide whether to display the domain number in /proc */
extern int pci_proc_domain(struct pci_bus *bus);
-/* MSI arch hooks */
-#define arch_setup_msi_irqs arch_setup_msi_irqs
-#define arch_teardown_msi_irqs arch_teardown_msi_irqs
-#define arch_msi_check_device arch_msi_check_device
-
struct vm_area_struct;
/* Map a range of PCI memory or I/O space for a device into user space */
int pci_mmap_page_range(struct pci_dev *pdev, struct vm_area_struct *vma,
diff --git a/arch/s390/include/asm/pci.h b/arch/s390/include/asm/pci.h
index 6c18012..8641e8d 100644
--- a/arch/s390/include/asm/pci.h
+++ b/arch/s390/include/asm/pci.h
@@ -21,10 +21,6 @@ void pci_iounmap(struct pci_dev *, void __iomem *);
int pci_domain_nr(struct pci_bus *);
int pci_proc_domain(struct pci_bus *);
-/* MSI arch hooks */
-#define arch_setup_msi_irqsarch_setup_msi_irqs
-#define arch_teardown_msi_irqs arch_teardown_msi_irqs
-
#define ZPCI_BUS_NR0 /* default bus number */
#define ZPCI_DEVFN 0 /* default device number */
diff --git a/arch/x86/include/asm/pci.h b/arch/x86/include/asm/pci.h
index d9e9e6c..7d74432 100644
--- a/arch/x86/include/asm/pci.h
+++ b/arch/x86/include/asm/pci.h
@@ -100,29 +100,6 @@ static inline void early_quirks(void) { }
extern void pci_iommu_alloc(void);
#ifdef CONFIG_PCI_MSI
-/* MSI arch specific hooks */
-static inline int x86_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
-{
- return x86_msi.setup_msi_irqs(dev, nvec, type);
-}
-
-static inline void x86_teardown_msi_irqs(struct pci_dev *dev)
-{
- x86_msi.teardown_msi_irqs(dev);
-}
-
-static inline void x86_teardown_msi_irq(unsigned int irq)
-{
- x86_msi.teardown_msi_irq(irq);
-}
-static inline void x86_restore_msi_irqs(struct pci_dev *dev, int irq)
-{
- x86_msi.restore_msi_irqs(dev, irq);
-}
-#define arch_setup_msi_irqs x86_setup_msi_irqs
-#define arch_teardown_msi_irqs x86_teardown_msi_irqs
-#define arch_teardown_msi_irq x86_teardown_msi_irq
-#define arch_restore_msi_irqs x86_restore_msi_irqs
/*
Recall: [PATCH 24/34] PCI: use weak functions for MSI arch-specific functions
Zhu Richard-R65037 would like to recall the message, [PATCH 24/34] PCI: use weak functions for MSI arch-specific functions. ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
RE: [PATCHv2 1/8] ALSA: Add SAI SoC Digital Audio Interface driver.
The udelay just doesn't make sense to what you are talking about. Does SAI really need 10us delay between two register-updating? No, this is not must be. Then you should explain in your comments why you really put it here or just drop it if it's just a mistake. The udelay will be removed then. ISSUE 2: There are two cases listed in 'Synchronous mode'. However, your driver doesn't take care of them. The SAI's synchronous mode looks like more flexible than SSI's. The driver needs to be more sophisticated so that it can handle multiple cases when TX/RX clocks are controlled by either TX or RX, and surely, the asynchronous mode as well. Because in Vybrid the transmitter bit clock and frame sync are to be used by both the transmitter and receiver, and only this case can be used here, so now I only handle this case. It's fairly okay if adding explicit comments to indicate that currently the driver only supports its Synchronous mode with clocks controlled by TX only. Just think, on other platforms maybe only the Rx's clock is available. Thus I think there should be one DT property to control this, and then the SAI driver can be more flexible. Or could you give me some more practical ideas ? -- Best Regards, Xiubo ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH -V2 1/5] powerpc: Use HPTE constants when updating hpte bits
On Mon, Nov 18, 2013 at 02:58:09PM +0530, Aneesh Kumar K.V wrote: From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com Even though we have same value for linux PTE bits and hash PTE pits bits, not pits :) use the hash pte bits wen updating hash pte when, not wen Signed-off-by: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com If you fix the spelling errors in the patch description: Acked-by: Paul Mackerras pau...@samba.org ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH -V2 4/5] powerpc: mm: Only check for _PAGE_PRESENT in set_pte/pmd functions
On Mon, Nov 18, 2013 at 02:58:12PM +0530, Aneesh Kumar K.V wrote: From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com We want to make sure we don't use these function when updating a pte or pmd entry that have a valid hpte entry, because these functions don't invalidate them. So limit the check to _PAGE_PRESENT bit. Numafault core changes use these functions for updating _PAGE_NUMA bits. That should be ok because when _PAGE_NUMA is set we can be sure that hpte entries are not present. Signed-off-by: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com Acked-by: Paul Mackerras pau...@samba.org ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH -V2 5/5] powerpc: mm: book3s: Enable _PAGE_NUMA for book3s
On Mon, Nov 18, 2013 at 02:58:13PM +0530, Aneesh Kumar K.V wrote: From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com We steal the _PAGE_COHERENCE bit and use that for indicating NUMA ptes. Signed-off-by: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com Acked-by: Paul Mackerras pau...@samba.org ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH -V2 2/5] powerpc: Free up _PAGE_COHERENCE for numa fault use later
On Mon, Nov 18, 2013 at 02:58:10PM +0530, Aneesh Kumar K.V wrote: From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com Set memory coherence always on hash64 config. If a platform cannot have memory coherence always set they can infer that from _PAGE_NO_CACHE and _PAGE_WRITETHRU like in lpar. So we dont' really need a separate bit for tracking _PAGE_COHERENCE. Signed-off-by: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com Acked-by: Paul Mackerras pau...@samba.org ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH] powerpc/signals: Mark VSX not saved with small contexts
The VSX MSR bit in the user context indicates if the context contains VSX state. Currently we set this when the process has touched VSX at any stage. Unfortunately, if the user has not provided enough space to save the VSX state, we can't save it but we currently still set the MSR VSX bit. This patch changes this to clear the MSR VSX bit when the user doesn't provide enough space. This indicates that there is no valid VSX state in the user context. This is needed to support get/set/make/swapcontext for applications that use VSX but only provide a small context. For example, getcontext in glibc provides a smaller context since the VSX registers don't need to be saved over the glibc function call. But since the program calling getcontext may have used VSX, the kernel currently says the VSX state is valid when it's not. If the returned context is then used in setcontext (ie. a small context without VSX but with MSR VSX set), the kernel will refuse the context. This situation has been reported by the glibc community. Based on patch from Carlos O'Donell. Tested-by: Haren Myneni ha...@linux.vnet.ibm.com Signed-off-by: Michael Neuling mi...@neuling.org Cc: sta...@vger.kernel.org --- arch/powerpc/kernel/signal_32.c | 10 +- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/kernel/signal_32.c b/arch/powerpc/kernel/signal_32.c index 749778e..1844298 100644 --- a/arch/powerpc/kernel/signal_32.c +++ b/arch/powerpc/kernel/signal_32.c @@ -457,7 +457,15 @@ static int save_user_regs(struct pt_regs *regs, struct mcontext __user *frame, if (copy_vsx_to_user(frame-mc_vsregs, current)) return 1; msr |= MSR_VSX; - } + } else if (!ctx_has_vsx_region) + /* +* With a small context structure we can't hold the VSX +* registers, hence clear the MSR value to indicate the state +* was not saved. +*/ + msr = ~MSR_VSX; + + #endif /* CONFIG_VSX */ #ifdef CONFIG_SPE /* save spe registers */ -- 1.8.3.2 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH v3] KVM: PPC: vfio kvm device: support spapr tce
In addition to the external VFIO user API, a VFIO KVM device
has been introduced recently.
sPAPR TCE IOMMU is para-virtualized and the guest does map/unmap
via hypercalls which take a logical bus id (LIOBN) as a target IOMMU
identifier. LIOBNs are made up and linked to IOMMU groups by the user
space. In order to accelerate IOMMU operations in the KVM, we need
to tell KVM the information about LIOBN-to-group mapping.
For that, a new KVM_DEV_VFIO_GROUP_SET_SPAPR_TCE_LIOBN parameter
is added. It accepts a pair of a VFIO group fd and LIOBN.
This also adds a new kvm_vfio_find_group_by_liobn() function which
receives kvm struct, LIOBN and a callback. As it increases the IOMMU
group use counter, the KVMr is required to pass a callback which
called when the VFIO group is about to be removed VFIO-KVM tracking so
the KVM is able to call iommu_group_put() to release the IOMMU group.
The KVM uses kvm_vfio_find_group_by_liobn() once per KVM run and caches
the result in kvm_arch. iommu_group_put() for all groups will be called
when KVM finishes (in the SPAPR TCE in KVM enablement patch).
Signed-off-by: Alexey Kardashevskiy a...@ozlabs.ru
---
Changes:
v3:
* total rework
* added a release callback into kvm_vfio_find_group_by_liobn so now
the user of the API can get a notification if the group is about to
disappear
---
Documentation/virtual/kvm/devices/vfio.txt | 19 -
arch/powerpc/kvm/Kconfig | 1 +
arch/powerpc/kvm/Makefile | 3 +
include/linux/kvm_host.h | 18 +
include/uapi/linux/kvm.h | 7 ++
virt/kvm/vfio.c| 116 -
6 files changed, 161 insertions(+), 3 deletions(-)
diff --git a/Documentation/virtual/kvm/devices/vfio.txt
b/Documentation/virtual/kvm/devices/vfio.txt
index ef51740..7ecb3b2 100644
--- a/Documentation/virtual/kvm/devices/vfio.txt
+++ b/Documentation/virtual/kvm/devices/vfio.txt
@@ -16,7 +16,22 @@ Groups:
KVM_DEV_VFIO_GROUP attributes:
KVM_DEV_VFIO_GROUP_ADD: Add a VFIO group to VFIO-KVM device tracking
+ kvm_device_attr.addr points to an int32_t file descriptor
+ for the VFIO group.
+
KVM_DEV_VFIO_GROUP_DEL: Remove a VFIO group from VFIO-KVM device tracking
+ kvm_device_attr.addr points to an int32_t file descriptor
+ for the VFIO group.
+
+ KVM_DEV_VFIO_GROUP_SET_SPAPR_TCE_LIOBN: sets a liobn for a VFIO group
+ kvm_device_attr.addr points to a struct:
+ struct kvm_vfio_spapr_tce_liobn {
+ __u32 argsz;
+ __u32 fd;
+ __u32 liobn;
+ };
+ where
+ @argsz is a struct size;
+ @fd is a file descriptor for a VFIO group;
+ @liobn is a logical bus id to be associated with the group.
-For each, kvm_device_attr.addr points to an int32_t file descriptor
-for the VFIO group.
diff --git a/arch/powerpc/kvm/Kconfig b/arch/powerpc/kvm/Kconfig
index 61b3535..d1b7f64 100644
--- a/arch/powerpc/kvm/Kconfig
+++ b/arch/powerpc/kvm/Kconfig
@@ -60,6 +60,7 @@ config KVM_BOOK3S_64
select KVM_BOOK3S_64_HANDLER
select KVM
select SPAPR_TCE_IOMMU
+ select KVM_VFIO
---help---
Support running unmodified book3s_64 and book3s_32 guest kernels
in virtual machines on book3s_64 host processors.
diff --git a/arch/powerpc/kvm/Makefile b/arch/powerpc/kvm/Makefile
index 6646c95..2438d2e 100644
--- a/arch/powerpc/kvm/Makefile
+++ b/arch/powerpc/kvm/Makefile
@@ -87,6 +87,9 @@ kvm-book3s_64-builtin-objs-$(CONFIG_KVM_BOOK3S_64_HV) := \
kvm-book3s_64-objs-$(CONFIG_KVM_XICS) += \
book3s_xics.o
+kvm-book3s_64-objs-$(CONFIG_KVM_VFIO) += \
+ $(KVM)/vfio.o \
+
kvm-book3s_64-module-objs := \
$(KVM)/kvm_main.o \
$(KVM)/eventfd.o \
diff --git a/include/linux/kvm_host.h b/include/linux/kvm_host.h
index 88ff96a..1d2ad5e 100644
--- a/include/linux/kvm_host.h
+++ b/include/linux/kvm_host.h
@@ -1112,5 +1112,23 @@ static inline bool
kvm_vcpu_eligible_for_directed_yield(struct kvm_vcpu *vcpu)
}
#endif /* CONFIG_HAVE_KVM_CPU_RELAX_INTERCEPT */
+
+typedef void (*kvm_vfio_release_group_callback)(struct kvm *kvm,
+ unsigned long liobn);
+
+#if defined(CONFIG_KVM_VFIO) defined(CONFIG_SPAPR_TCE_IOMMU)
+
+extern struct iommu_group *kvm_vfio_find_group_by_liobn(struct kvm *kvm,
+ unsigned long liobn, kvm_vfio_release_group_callback cb);
+
+#else
+
+static inline struct iommu_group *kvm_vfio_find_group_by_liobn(struct kvm *kvm,
+ unsigned long liobn, ikvm_vfio_release_group_callback cb)
+{
+ return NULL;
+}
+#endif /* CONFIG_KVM_VFIO CONFIG_SPAPR_TCE_IOMMU */
+
#endif
diff --git a/include/uapi/linux/kvm.h b/include/uapi/linux/kvm.h
index 7c1a349..3d77dde 100644
--- a/include/uapi/linux/kvm.h
+++ b/include/uapi/linux/kvm.h
@@ -847,6 +847,13 @@ struct kvm_device_attr {
#define
Re: [PATCH RFC v5 2/5] dma: mpc512x: add support for peripheral transfers
2013/11/15 Gerhard Sittig g...@denx.de: As for the not yet addressed feedback: From the top of my head I can think of the execute comment which contradicts the code (which suggests that at least one of them is wrong), and the data type mismatch in the config routine (where code just happens to work by coincidence). And in bypassing I noticed that your recent submission has coding style issues (braces, indentation), which should no longer happen after several iterations as you should know how to prepare and check the next version. I'll doublecheck this and return with improved code. Without feedback, reviewers may see several submissions which suffer from the same issues, and expect more to show up and thus feel that their feedback is getting ignored. Which quickly becomes tiring. Thanks for your patience and comprehensive replies. Best regards, Alexander. ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
RE: [PATCHv2 6/8] ASoC: fsl: add SGTL5000 based audio machine driver.
+ /* TODO: The SAI driver should figure this out for us */
+ switch (channels) {
+ case 2:
+ snd_soc_dai_set_tdm_slot(cpu_dai, 0xfffc, 0xfffc, 2,
0);
+ break;
+ case 1:
+ snd_soc_dai_set_tdm_slot(cpu_dai, 0xfffe, 0xfffe, 1,
0);
+ break;
+ default:
+ return -EINVAL;
+ }
Yes, it should - this code should probably just be copied straight into
the SAI driver. If we need to support other configurations we can do
that later.
Well, yes.
I have considered carefully about this, It maybe nicer to move this to SAI
driver's .hw_params.
--
Best Regards,
Xiubo
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Re: PCIE device errors after linux kernel upgrade
I compared the configuration hexdump of my pci controller and pci device (FPGA) on old kernel(working 2.6.32) and new (3.8.13) and the only difference was on the controller configuration on the memory base at Type 1 configuration header registers . what does it mean and could it be the trigger for my problem ? Thanks a lot. Leonid -- View this message in context: http://linuxppc.10917.n7.nabble.com/Re-PCIE-device-errors-after-linux-kernel-upgrade-tp74563p78251.html Sent from the linuxppc-dev mailing list archive at Nabble.com. ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
