On Tue, Mar 11, 2014 at 06:51:20PM -0500, Scott Wood wrote:
On Fri, 2014-03-07 at 12:58 +0800, Chenhui Zhao wrote:
In 64-bit mode, kernel just clears the irq soft-enable flag
in struct paca_struct to disable external irqs. But, in
the case of suspend, irqs should be disabled by hardware.
On Tue, Mar 11, 2014 at 07:00:27PM -0500, Scott Wood wrote:
On Fri, 2014-03-07 at 12:58 +0800, Chenhui Zhao wrote:
In sleep mode, the clocks of e500 cores and unused IP blocks is
turned off. The IP blocks which are allowed to wake up the processor
are still running.
The sleep mode is
Signed-off-by: Tony Breeds t...@bakeyournoodle.com
---
arch/powerpc/platforms/pseries/setup.c | 4
1 file changed, 4 insertions(+)
diff --git a/arch/powerpc/platforms/pseries/setup.c
b/arch/powerpc/platforms/pseries/setup.c
index 972df0f..5a32caa 100644
---
Signed-off-by: Zhao Qiang b45...@freescale.com
---
arch/powerpc/boot/dts/t1040rdb.dts | 43 ++
1 file changed, 43 insertions(+)
diff --git a/arch/powerpc/boot/dts/t1040rdb.dts
b/arch/powerpc/boot/dts/t1040rdb.dts
index e2eee18..6ff0412 100644
---
On Tue, Mar 11, 2014 at 07:08:43PM -0500, Scott Wood wrote:
On Fri, 2014-03-07 at 12:58 +0800, Chenhui Zhao wrote:
From: Hongbo Zhang hongbo.zh...@freescale.com
In the last stage of deep sleep, software will trigger a Finite
State Machine (FSM) to control the hardware precedure, such as
On Tue, Mar 11, 2014 at 07:45:14PM -0500, Scott Wood wrote:
On Fri, 2014-03-07 at 12:58 +0800, Chenhui Zhao wrote:
From: Wang Dongsheng dongsheng.w...@freescale.com
Add booke_cpu_state_save() and booke_cpu_state_restore() functions which
can be
used to save/restore CPU's registers in
On Tue, Mar 11, 2014 at 08:10:24PM -0500, Scott Wood wrote:
On Fri, 2014-03-07 at 12:58 +0800, Chenhui Zhao wrote:
From: Zhao Chenhui chenhui.z...@freescale.com
T1040 supports deep sleep feature, which can switch off most parts of
the SoC when it is in deep sleep mode. This way, it
2013/7/14 Gerhard Sittig g...@denx.de:
this series
- introduces slave s/g support (that's support for DMA transfers which
involve peripherals in contrast to mem-to-mem transfers)
- adds device tree based lookup support for DMA channels
- combines floating patches and related feedback which
Concentrate the specific code for MPC8308 in the 'if' branch
and handle MPC512x in the 'else' branch.
This modification only reorders instructions but doesn't change behaviour.
Signed-off-by: Alexander Popov a13xp0p0...@gmail.com
Acked-by: Anatolij Gustschin ag...@denx.de
Acked-by: Gerhard Sittig
Introduce support for slave s/g transfer preparation and the associated
device control callback in the MPC512x DMA controller driver, which adds
support for data transfers between memory and peripheral I/O to the
previously supported mem-to-mem transfers.
Signed-off-by: Alexander Popov
Replace devm_request_irq() with request_irq() since there is no need
to use it because the original code always frees IRQ manually with
devm_free_irq(). Replace devm_free_irq() with free_irq() accordingly.
Signed-off-by: Alexander Popov a13xp0p0...@gmail.com
---
drivers/dma/mpc512x_dma.c | 11
This patch adds a new common OF dma xlate callback function which will match a
channel by it's id. The binding expects one integer argument which it will use
to
lookup the channel by the id.
Unlike of_dma_simple_xlate this function is able to handle a system with
multiple DMA controllers. When
From: Gerhard Sittig g...@denx.de
introduce a device tree binding document for the MPC512x DMA controller
Signed-off-by: Gerhard Sittig g...@denx.de
[ a13xp0p0...@gmail.com: turn this into a separate patch ]
---
.../devicetree/bindings/dma/mpc512x-dma.txt| 55 ++
1
Register the controller for device tree based lookup of DMA channels
(non-fatal for backwards compatibility with older device trees) and
provide the '#dma-cells' property in the shared mpc5121.dtsi file
Signed-off-by: Gerhard Sittig g...@denx.de
Signed-off-by: Alexander Popov
On Tue, 11 Mar 2014, Nishanth Aravamudan wrote:
I have a P7 system that has no node0, but a node0 shows up in numactl
--hardware, which has no cpus and no memory (and no PCI devices):
Well as you see from the code there has been so far the assumption that
node 0 has memory. I have never run a
On Wed, 2014-03-12 at 13:57 +0800, Kevin Hao wrote:
On Tue, Mar 11, 2014 at 08:10:24PM -0500, Scott Wood wrote:
+ FSL_DIS_ALL_IRQ
+
+ /*
+ * Place DDR controller in self refresh mode.
+ * From here on, DDR can't be access any more.
+ */
+ lwz r10, 0(r13)
+ oris
Alistair Popple has volunteered to take over maintainership of the ppc4xx
stuff upstream. Switch the MAINTAINERS entry over to him.
Signed-off-by: Josh Boyer jwbo...@gmail.com
---
MAINTAINERS | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index
On Wed, 2014-03-12 at 16:26 +0800, Zhao Qiang wrote:
Signed-off-by: Zhao Qiang b45...@freescale.com
---
arch/powerpc/boot/dts/t1040rdb.dts | 43
++
1 file changed, 43 insertions(+)
diff --git a/arch/powerpc/boot/dts/t1040rdb.dts
On Wed, 2014-03-12 at 16:26 +0800, Zhao Qiang wrote:
Signed-off-by: Zhao Qiang b45...@freescale.com
---
arch/powerpc/boot/dts/t1040rdb.dts | 43
++
1 file changed, 43 insertions(+)
Presumably this is on top of this patch:
On 03/12/2014 03:37 AM, Andrew Morton wrote:
On Tue, 11 Mar 2014 02:03:52 +0530 Srivatsa S. Bhat
srivatsa.b...@linux.vnet.ibm.com wrote:
Hi,
Many subsystems and drivers have the need to register CPU hotplug callbacks
from their init routines and also perform initialization for the CPUs
On Wed, 2014-03-13 at 2:46 AM, Scott wrote:
-Original Message-
From: Wood Scott-B07421
Sent: Thursday, March 13, 2014 2:46 AM
To: Zhao Qiang-B45475
Cc: linuxppc-dev@lists.ozlabs.org; Wood Scott-B07421; Xie Xiaobo-R63061
Subject: Re: [PATCH] T1040RDB: add qe node for T1040RDB dts
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