The facility unavailable exception can be triggered from userspace by
accessing PMU registers when EBB is not enabled. This causes the
included pr_err() to run, hence spamming the kernel log buffer.
This avoids this by rate limiting these messages.
Signed-off-by: Michael Neuling
On Tue, Mar 11, 2014 at 02:09:59AM +0530, Srivatsa S. Bhat wrote:
Subsystems that want to register CPU hotplug callbacks, as well as perform
initialization for the CPUs that are already online, often do it as shown
below:
get_online_cpus();
for_each_online_cpu(cpu)
On Wed, 2014-03-12 at 15:47 +0400, Alexander Popov wrote:
Introduce support for slave s/g transfer preparation and the associated
device control callback in the MPC512x DMA controller driver, which adds
support for data transfers between memory and peripheral I/O to the
previously supported
On Wed, 2014-03-12 at 15:47 +0400, Alexander Popov wrote:
Replace devm_request_irq() with request_irq() since there is no need
to use it because the original code always frees IRQ manually with
devm_free_irq(). Replace devm_free_irq() with free_irq() accordingly.
Signed-off-by: Alexander
On Thursday 13 March 2014, Mark Rutland wrote:
+
+Example:
+
+ dma0: dma@14000 {
+ compatible = fsl,mpc5121-dma;
+ reg = 0x14000 0x1800;
+ interrupts = 65 0x8;
+ #dma-cells = 1;
+ };
+
+
+Client node properties:
+
On Fri, 21 Feb 2014, Sebastian Andrzej Siewior wrote:
A MSI device may have multiple interrupts. That means that the
interrupts numbers should be continuos so that pdev-irq refers to the
first interrupt, pdev-irq + 1 to the second and so on.
This patch adds support for continuous allocation
On Thu, 2014-03-13 at 19:00 -0500, Scott Wood wrote:
@@ -444,6 +451,9 @@ _GLOBAL(kvmppc_resume_host)
PPC_STD(r8, VCPU_SHARED_SPRG6, r11)
mfxer r3
PPC_STD(r9, VCPU_SHARED_SPRG7, r11)
+#ifdef CONFIG_64BIT
+ mtspr SPRN_SPRG_VDSO_WRITE, r3
+#endif
Oops, this hunk was
On Thu, 2014-03-13 at 15:46 +0800, Kevin Hao wrote:
On Wed, Mar 12, 2014 at 12:43:05PM -0500, Scott Wood wrote:
Shouldn't we use readback, sync here? The following is quoted form
t4240RM:
To guarantee that the results of any sequence of writes to configuration
registers are in
On Wed, 2014-03-12 at 11:59 +0800, Chenhui Zhao wrote:
On Tue, Mar 11, 2014 at 06:42:51PM -0500, Scott Wood wrote:
On Fri, 2014-03-07 at 12:57 +0800, Chenhui Zhao wrote:
+int fsl_rcpm_init(void)
+{
+ struct device_node *np;
+
+ np = of_find_compatible_node(NULL, NULL,
On Wed, 2014-03-12 at 15:46 +0800, Chenhui Zhao wrote:
On Tue, Mar 11, 2014 at 06:51:20PM -0500, Scott Wood wrote:
On Fri, 2014-03-07 at 12:58 +0800, Chenhui Zhao wrote:
In 64-bit mode, kernel just clears the irq soft-enable flag
in struct paca_struct to disable external irqs. But, in
On Wed, 2014-03-12 at 16:08 +0800, Chenhui Zhao wrote:
On Tue, Mar 11, 2014 at 07:00:27PM -0500, Scott Wood wrote:
On Fri, 2014-03-07 at 12:58 +0800, Chenhui Zhao wrote:
In sleep mode, the clocks of e500 cores and unused IP blocks is
turned off. The IP blocks which are allowed to wake up
On Wed, 2014-03-12 at 16:34 +0800, Chenhui Zhao wrote:
On Tue, Mar 11, 2014 at 07:08:43PM -0500, Scott Wood wrote:
On Fri, 2014-03-07 at 12:58 +0800, Chenhui Zhao wrote:
From: Hongbo Zhang hongbo.zh...@freescale.com
In the last stage of deep sleep, software will trigger a Finite
On Wed, 2014-03-12 at 18:40 +0800, Chenhui Zhao wrote:
On Tue, Mar 11, 2014 at 08:10:24PM -0500, Scott Wood wrote:
On Fri, 2014-03-07 at 12:58 +0800, Chenhui Zhao wrote:
From: Zhao Chenhui chenhui.z...@freescale.com
T1040 supports deep sleep feature, which can switch off most parts of
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