I made a cleanup suggestion on 27143b9a0 (powerpc/le: Avoid creatng
R_PPC64_TOCSAVE relocations for modules) that had a stupid typo. Fix
it.
Signed-off-by: Anton Blanchard an...@samba.org
---
diff --git a/arch/powerpc/Makefile b/arch/powerpc/Makefile
index a9f814a..4c0cedf 100644
---
[ removed cscope-devel from Cc:, non-subscriber mails get blocked anyway ]
On Mon, 2014-04-07 at 14:42 +0200, Gerhard Sittig wrote:
On Mon, 2014-04-07 at 06:42 -0400, Neil Horman wrote:
On Thu, Apr 03, 2014 at 03:16:15PM +0200, Yann Droneaud wrote:
[ ... ]
cscope reports
On 04/08/2014 08:49 AM, Michael wang wrote:
Since v1:
Edited the comment according to Srivatsa's suggestion.
During the testing, we encounter below WARN followed by Oops:
WARNING: at kernel/sched/core.c:6218
...
NIP [c0101660]
On Tue, Apr 08, 2014 at 09:56:10AM +0200, Gerhard Sittig wrote:
[ removed cscope-devel from Cc:, non-subscriber mails get blocked anyway ]
On Mon, 2014-04-07 at 14:42 +0200, Gerhard Sittig wrote:
On Mon, 2014-04-07 at 06:42 -0400, Neil Horman wrote:
On Thu, Apr 03, 2014 at
On Fri, Apr 04, 2014 at 11:05:32AM +0100, Mark Brown wrote:
On Fri, Apr 04, 2014 at 03:09:47PM +0800, Nicolin Chen wrote:
The BCP bit in TCR4/RCR4 register rules as followings:
0 Bit clock is active high with drive outputs on rising edge
and sample inputs on falling edge.
1 Bit
On Tue, Apr 08, 2014 at 07:07:40PM +0800, Nicolin Chen wrote:
Sir, I can't find this patch on any of the remote branches: for-next,
topic/fsl-sai and fix/fsl-sai. Where could I find it?
It's in the fix branch.
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On Sun, 2014-04-06 at 18:48 +0530, Prabhakar Kushwaha wrote:
On 3/20/2014 4:03 AM, Scott Wood wrote:
On Sat, Jan 25, 2014 at 05:10:59PM +0530, Prabhakar Kushwaha wrote:
+ clockgen: global-utilities@e1000 {
+ compatible = fsl,t1040-clockgen, fsl,qoriq-clockgen-2.0,
+
On Tue, 2014-03-25 at 14:41 +0100, Valentin Longchamp wrote:
These are the bindings for 2 MFD devices used on some of the Keymile boards.
The first one is the chassis managmenet bfticu FPGA.
The second one is the board controller (reset, LEDs, GPIOs) QRIO CPDL.
These FPGAs are used in the
On Tue, 2014-03-25 at 14:41 +0100, Valentin Longchamp wrote:
+ lbc: localbus@ffe124000 {
+ reg = 0xf 0xfe124000 0 0x1000;
+ ranges = 0 0 0xf 0xffa0 0x0004 /* LB 0 */
+ 1 0 0xf 0xfb00 0x0001 /* LB 1 */
+
On Tue, 2014-03-18 at 17:09 +0800, Xie Xiaobo wrote:
diff --git a/arch/powerpc/sysdev/qe_lib/qe.c b/arch/powerpc/sysdev/qe_lib/qe.c
index 238a07b..9a9f733 100644
--- a/arch/powerpc/sysdev/qe_lib/qe.c
+++ b/arch/powerpc/sysdev/qe_lib/qe.c
@@ -1,5 +1,6 @@
/*
- * Copyright (C) 2006-2010
On Friday 04 April 2014 06:47 PM, Kirill A. Shutemov wrote:
On Fri, Apr 04, 2014 at 11:57:14AM +0530, Madhavan Srinivasan wrote:
Kirill A. Shutemov with faultaround patchset introduced
vm_ops-map_pages() for mapping easy accessible pages around
fault address in hope to reduce number of minor
On Friday 04 April 2014 09:48 PM, Dave Hansen wrote:
On 04/03/2014 11:27 PM, Madhavan Srinivasan wrote:
This patch creates infrastructure to move the FAULT_AROUND_ORDER
to arch/ using Kconfig. This will enable architecture maintainers
to decide on suitable FAULT_AROUND_ORDER value based on
On Friday 04 April 2014 11:20 PM, David Miller wrote:
From: Dave Hansen dave.han...@intel.com
Date: Fri, 04 Apr 2014 09:18:43 -0700
On 04/03/2014 11:27 PM, Madhavan Srinivasan wrote:
This patch creates infrastructure to move the FAULT_AROUND_ORDER
to arch/ using Kconfig. This will enable
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