This add support for the Coherent Accelerator (cxl) attached to POWER8
processors. This coherent accelerator interface is designed to allow the
coherent connection of FPGA based accelerators (and other devices) to a POWER
systems.
IBM refers to this as the Coherent Accelerator Processor
From: Ian Munsie imun...@au1.ibm.com
Currently spu_handle_mm_fault() is in the cell platform.
This code is generically useful for other non-cell co-processors on powerpc.
This patch moves this function out of the cell platform into arch/powerpc/mm so
that others may use it.
Signed-off-by: Ian
From: Ian Munsie imun...@au1.ibm.com
__spu_trap_data_seg() currently contains code to determine the VSID and ESID
required for a particular EA and mm struct.
This code is generically useful for other co-processors. This moves the code
of the cell platform so it can be used by other powerpc
From: Ian Munsie imun...@au1.ibm.com
Currently msi_bitmap_alloc_hwirqs() will round up any IRQ allocation requests
to the nearest power of 2. eg. ask for 5 IRQs and you'll get 8. This wastes a
lot of IRQs which can be a scarce resource.
For cxl we can require multiple IRQs for every contexts
From: Ian Munsie imun...@au1.ibm.com
Signed-off-by: Ian Munsie imun...@au1.ibm.com
Signed-off-by: Michael Neuling mi...@neuling.org
---
arch/powerpc/mm/hash_utils_64.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/powerpc/mm/hash_utils_64.c b/arch/powerpc/mm/hash_utils_64.c
index
From: Ian Munsie imun...@au1.ibm.com
Some of the MSI IRQ code in pnv_pci_ioda_msi_setup() is generically useful so
split it out.
This will be used by some of the cxl PCIe code later.
Signed-off-by: Ian Munsie imun...@au1.ibm.com
Signed-off-by: Michael Neuling mi...@neuling.org
---
From: Ian Munsie imun...@au1.ibm.com
This new header add defines for callbacks and structs needed by the rest of the
kernel to hook into the cxl infrastructure.
Empty functions are provided when CONFIG CXL_BASE is not enabled.
Signed-off-by: Ian Munsie imun...@au1.ibm.com
Signed-off-by: Michael
From: Ian Munsie imun...@au1.ibm.com
This adds a number of functions for allocating IRQs under powernv PCIe for cxl.
Signed-off-by: Ian Munsie imun...@au1.ibm.com
Signed-off-by: Michael Neuling mi...@neuling.org
---
arch/powerpc/include/asm/pnv-pci.h| 27 +
From: Ian Munsie imun...@au1.ibm.com
This adds a new function hash_page_mm() based on the existing hash_page().
This version allows any struct mm to be passed in, rather than assuming
current. This is useful for servicing co-processor faults which are not in the
context of the current running
From: Ian Munsie imun...@au1.ibm.com
This adds the OPAL call to change a PHB into cxl mode.
Signed-off-by: Ian Munsie imun...@au1.ibm.com
Signed-off-by: Michael Neuling mi...@neuling.org
---
arch/powerpc/include/asm/opal.h| 2 ++
arch/powerpc/platforms/powernv/opal-wrappers.S |
From: Ian Munsie imun...@au1.ibm.com
This add a hook into tlbie() so that we use global invalidations when there are
cxl contexts active.
Normally cxl snoops broadcast tlbie. cxl can have TLB entries invalidated via
MMIO, but we aren't doing that yet. So for now we are just disabling local
From: Ian Munsie imun...@au1.ibm.com
This adds the base cxl support that needs to be build into the kernel to use
cxl as a module. This is needed so that the cxl call backs from the core
powerpc mm code always exist irrespective of if the cxl module is loaded or
not. This is similar to how cell
From: Ian Munsie imun...@au1.ibm.com
This defines structs and magic numbers required for userspace to interact with
the kernel cxl driver via /dev/cxl/afu0.0.
It adds this header file Kbuild so it's exported when doing make
headers_installs.
Signed-off-by: Ian Munsie imun...@au1.ibm.com
From: Ian Munsie imun...@au1.ibm.com
Signed-off-by: Ian Munsie imun...@au1.ibm.com
Signed-off-by: Michael Neuling mi...@neuling.org
---
drivers/misc/cxl/Kconfig | 18 ++
drivers/misc/cxl/Makefile | 3 +++
2 files changed, 21 insertions(+)
diff --git a/drivers/misc/cxl/Kconfig
From: Ian Munsie imun...@au1.ibm.com
This documentation gives an overview of the hardware architecture, userspace
APIs via /dev/cxl/afu0.0 and the syfs files. It also adds a MAINTAINERS file
entry for cxl.
Signed-off-by: Ian Munsie imun...@au1.ibm.com
Signed-off-by: Michael Neuling
Hi Mikey Ian,
Currently spu_handle_mm_fault() is in the cell platform.
This code is generically useful for other non-cell co-processors on powerpc.
This patch moves this function out of the cell platform into arch/powerpc/mm
so
that others may use it.
Makes sense.
Acked-by: Jeremy
Hi Mikey Ian,
__spu_trap_data_seg() currently contains code to determine the VSID and ESID
required for a particular EA and mm struct.
This code is generically useful for other co-processors. This moves the code
of the cell platform so it can be used by other powerpc code.
OK, nice.
+
Christophe Leroy christophe.le...@c-s.fr wrote on 2014/09/17 18:36:57:
Exception InstructionAccess does not exist on MPC8xx. No need to branch
there from somewhere else.
Handling can be done directly in InstructionTLBError Exception.
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
Le 18/09/2014 17:15, Joakim Tjernlund a écrit :
Christophe Leroy christophe.le...@c-s.fr wrote on 2014/09/17 18:36:57:
Exception InstructionAccess does not exist on MPC8xx. No need to branch
there from somewhere else.
Handling can be done directly in InstructionTLBError Exception.
leroy christophe christophe.le...@c-s.fr wrote on 2014/09/18 18:42:14:
Le 18/09/2014 17:15, Joakim Tjernlund a écrit :
Christophe Leroy christophe.le...@c-s.fr wrote on 2014/09/17
18:36:57:
Exception InstructionAccess does not exist on MPC8xx. No need to
branch
there from somewhere
Le 18/09/2014 18:42, leroy christophe a écrit :
Le 18/09/2014 17:15, Joakim Tjernlund a écrit :
Christophe Leroy christophe.le...@c-s.fr wrote on 2014/09/17 18:36:57:
Exception InstructionAccess does not exist on MPC8xx. No need to branch
there from somewhere else.
Handling can be done
Le 18/09/2014 20:12, Joakim Tjernlund a écrit :
leroy christophe christophe.le...@c-s.fr wrote on 2014/09/18 18:42:14:
Le 18/09/2014 17:15, Joakim Tjernlund a écrit :
Christophe Leroy christophe.le...@c-s.fr wrote on 2014/09/17
18:36:57:
Exception InstructionAccess does not exist on
On Thu, 2014-09-18 at 20:52 +0200, christophe leroy wrote:
Le 18/09/2014 18:42, leroy christophe a écrit :
Le 18/09/2014 17:15, Joakim Tjernlund a écrit :
Christophe Leroy christophe.le...@c-s.fr wrote on 2014/09/17 18:36:57:
Exception InstructionAccess does not exist on MPC8xx. No need
christophe leroy christophe.le...@c-s.fr wrote on 2014/09/18 21:11:01:
Le 18/09/2014 20:12, Joakim Tjernlund a écrit :
leroy christophe christophe.le...@c-s.fr wrote on 2014/09/18
18:42:14:
Le 18/09/2014 17:15, Joakim Tjernlund a écrit :
Christophe Leroy christophe.le...@c-s.fr wrote
On 09/12, Aaron Tomlin wrote:
Tasks get their end of stack set to STACK_END_MAGIC with the
aim to catch stack overruns. Currently this feature does not
apply to init_task. This patch removes this restriction.
Note that a similar patch was posted by Prarit Bhargava [1]
some time ago but was
looks like previous email not had the email ids added by kumar gala.
adding the missing ids and sending again.
On Thu, Sep 18, 2014 at 9:32 AM, Ganapatrao Kulkarni
gpkulka...@gmail.com wrote:
On Thu, Sep 18, 2014 at 4:42 AM, Zi Shen Lim zlim@gmail.com wrote:
On Wed, Sep 17, 2014 at 2:48 PM,
Commit 1c98025c6c95bc057a25e2c6596de23288c68160 powerpc: Dynamic DMA
zone limits updated how zones are created in paging_init(), but missed
the NUMA version of paging_init(). This was noticed via a linker
error, since dma_pfn_limit_to_zone() was, like the non-NUMA
paging_init(), limited by
@@ -58,12 +56,12 @@ int spu_handle_mm_fault(struct mm_struct *mm, unsigned
long ea,
goto out_unlock;
}
- is_write = dsisr MFC_DSISR_ACCESS_PUT;
+ is_write = dsisr DSISR_ISSTORE;
if (is_write) {
if (!(vma-vm_flags VM_WRITE))
This series adds an optimised version of word-at-a-time.h for ppc64le.
It uses the cmpb instruction which compares each byte in two 64 bit
values and for each matching byte places 0xff in the target and 0x00
otherwise.
The intermediate functions diverge a bit from what might have been
intended
Implement a bi-arch and bi-endian version of load_unaligned_zeropad.
Since the fallback case is so rare, a userspace test harness was used
to test this on ppc64le, ppc64 and ppc32:
http://ozlabs.org/~anton/junkcode/test_load_unaligned_zeropad.c
It uses mprotect to force a SEGV across a page
Use cmpb which compares each byte in two 64 bit values and
for each matching byte places 0xff in the target and 0x00
otherwise.
A simple hash_name microbenchmark:
http://ozlabs.org/~anton/junkcode/hash_name_bench.c
shows this version to be 10-20% faster than running the x86
version on POWER8,
Enable on DCACHE_WORD_ACCESS on ppc64le. It should work on
ppc64 and ppc32 but we need to do some testing first.
A somewhat reasonable testcase used to show the performance
improvement - a repeated stat of a 33 byte filename that
doesn't exist:
#include sys/types.h
#include sys/stat.h
+
+int copro_data_segment(struct mm_struct *mm, u64 ea, u64 *esid, u64 *vsid)
+{
+ int psize, ssize;
+
+ *esid = (ea ESID_MASK) | SLB_ESID_V;
+
+ switch (REGION_ID(ea)) {
+ case USER_REGION_ID:
+ pr_devel(copro_data_segment: 0x%llx -- USER_REGION_ID\n, ea);
The patch uses eeh_unfreeze_pe() to replace the code clearing
frozen IO and DMA, in order to simplify the things.
Signed-off-by: Gavin Shan gws...@linux.vnet.ibm.com
---
arch/powerpc/kernel/eeh.c| 19 +--
arch/powerpc/kernel/eeh_driver.c | 18 ++
As Anton suggested, the patch decreases the message level on EEH
initialization to avoid unnecessary messages if required. Also,
we have unified hint if any of needful RTAS calls is missed, and
then we can check /proc/device-tree to figure out the missed RTAS
calls.
Suggested-by: Anton Blanchard
The function eeh_pci_enable() is called to apply various requests
to one particular PE: Enabling EEH, Disabling EEH, Enabling IO,
Enabling DMA, Freezing PE. When enabling IO or DMA on one specific
PE, we need check that IO or DMA isn't enabled previously. But
the condition used to do the check
When passing through PE to guest, that's possibly in frozen
state. The driver for the pass-through devices on guest side
can't be loaded successfully as reported. We already had one
gate in eeh_dev_open() to clear PE frozen state accordingly,
but that's not enough because the function is only
Function pcibios_set_pcie_reset_state() can be used to do PCI
reset. PCI config access during the reset usually causes EEH
errors unexpectedly. In order to avoid the EEH error, the patch
blocks PCI config access during reset with the help of flag
EEH_PE_RESET, which is similar to what we did in
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