On Thu, Sep 18, 2014 at 06:26:50PM +1000, Michael Neuling wrote:
From: Ian Munsie imun...@au1.ibm.com
Some of the MSI IRQ code in pnv_pci_ioda_msi_setup() is generically useful so
split it out.
This will be used by some of the cxl PCIe code later.
Signed-off-by: Ian Munsie imun...@au1.ibm.com
On Thu, Sep 18, 2014 at 06:26:52PM +1000, Michael Neuling wrote:
From: Ian Munsie imun...@au1.ibm.com
This adds a number of functions for allocating IRQs under powernv PCIe for cxl.
Signed-off-by: Ian Munsie imun...@au1.ibm.com
Signed-off-by: Michael Neuling mi...@neuling.org
---
Le 18/09/2014 22:02, Joakim Tjernlund a écrit :
christophe leroy christophe.le...@c-s.fr wrote on 2014/09/18 21:11:01:
Le 18/09/2014 20:12, Joakim Tjernlund a écrit :
leroy christophe christophe.le...@c-s.fr wrote on 2014/09/18
18:42:14:
Le 18/09/2014 17:15, Joakim Tjernlund a écrit :
SCRATCH0 and SCRATCH1 are only used in Exceptions prologs where no other
exception can happen. There is therefore no need to preserve them accross
TLB handlers, we can use them there as in other exceptions. One of the
advantages is that they do not suffer CPU6 errata unlike M_TW register.
This patchset:
1) provides several MMU TLB handling optimisation on MPC8xx.
2) adds support of 16k pages on MPC8xx.
All changes have been successfully tested on a custom board equipped with MPC885
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
Tested-by: Christophe Leroy
Since coming 469d62be9263b92f2c3329540cbb1c076111f4f3, SPRG2 is used as a
scratch register just like SPRG0 and SPRG1. So Declare it as such and fix
the comment which is not valid anymore since that commit.
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
Changes in v2:
- None
Changes
Exception InstructionAccess does not exist on MPC8xx. No need to branch there
from somewhere else.
Handling can be done directly in InstructionTLBError Exception.
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
Changes in v2:
- None
Changes in v3:
- arch/powerpc/mm/fault.c uses
Since commit 2321f33790a6c5b80322d907a92d5739e7521a13, r10 is not used anymore
after FixupDAR. There is therefore no need to set it up with the value of DAR.
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
Changes in v2:
- None
Changes in v3:
- None
Changes in v4:
- None
Branching takes two cycles on MPC8xx. Lets duplicate the two instructions
and avoid the branching.
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
Changes in v2:
- None
Changes in v3:
- None
Changes in v4:
- None
arch/powerpc/kernel/head_8xx.S |6 --
1 files changed, 4
Since commit 2321f33790a6c5b80322d907a92d5739e7521a13, dirty handling is not
handled here anymore. So we fix the comment.
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
Changes in v2:
- None
Changes in v3:
- None
Changes in v4:
- None
arch/powerpc/kernel/head_8xx.S | 8 ++--
DataAccess exception is never generated by MPC8xx so do the job directly where
it is used to avoid an unnecessary branching.
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
Changes in v2:
- None
Changes in v3:
- arch/powerpc/mm/fault.c uses the vector number, so make sure it
MD_TWC can only be used properly with 4k pages.
So lets calculate level 2 table index by ourselves.
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
Changes in v2:
- No need to save r11 in cr, we can do without modifying r11 in DataStoreTLBMiss
Changes in v3:
- None
Changes in v4:
-
Value 0x00f0 is used to force bits in TLB level 2 entry. This value is linked
to the page size and will vary when we change the page size. Lets define a const
for it in order to have it at only one place.
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
Changes in v2:
- None
Changes
There is not need to restore r10, r11 and cr registers at this end of ITLBmiss
handler as they are saved again to the same place in ITLBError handler we are
jumping to.
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
Changes in v2:
- None
Changes in v3:
- None
Changes in v4:
- None
8xx sometimes need to load a invalid/non-present TLBs in
it DTLB asm handler.
These must be invalidated separaly as linux mm doesn't.
Commit 5efab4a02c89c252fb4cce097aafde5f8208dbfe was invalidating them in
arch/powerpc/mm/fault.c.
This patch does the invalidation earlier in order to free
This patch hiddes that SPR address needed for CPU6 ERRATA handling in the macro.
Then we don't have to worry about this address directly in the code.
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
Changes in v2:
- None
Changes in v3:
- None
Changes in v4:
- None
When a PMD entry is valid, _PMD_PRESENT is set. Therefore, forcing that bit
during TLB loading is useless.
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
Changes in v2:
- None
Changes in v3:
- None
Changes in v4:
- None
arch/powerpc/kernel/head_8xx.S |2 --
1 files changed,
No need to re-set this bit at each TLB miss. Let's set it in the PTE.
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
Changes in v2:
- None
Changes in v3:
- Removed PPC405 related macro from PPC8xx specific code
- PTE_NONE_MASK doesn't need PAGE_ACCESSED in Linux 2.6
Changes in v4:
As we are not using anymore DAR to save registers, it is now available for
saving the r3 register used for CPU6 ERRATA handling. Therefore we can
remove the major hack which was to use memory location 0 to save r3.
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
Changes in v3:
- New
This patch activates the handling of 16k pages on the MPC8xx.
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
Changes in v2:
- None
Changes in v3:
- None
Changes in v4:
- None
arch/powerpc/Kconfig |2 +-
arch/powerpc/include/asm/mmu-8xx.h |2 ++
Use M_TW instead of M_TWB for storing Level 1 table address as M_TWB requires
4k aligned tables, which is only the case with 4k pages.
Consequently, we have to calculate the level 1 table index by ourselves.
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
Changes in v2:
- None
By XORing the upper part of the instruction code, we get a value that can
directly be verified with the second test and we can remove the first test.
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
Changes in v2:
- None
Changes in v3:
- None
Changes in v4:
- None
r10 and r3 are only used inside FixupDAR function. So lets save them inside
that function only.
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
Changes in v2:
- None
Changes in v3:
- None
Changes in v4:
- None
arch/powerpc/kernel/head_8xx.S | 27 +--
1
In DTLBError handler there is not need to restore r10, r11 and cr registers
after fixing DAR as they are saved again to the same place just after.
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
Changes in v2:
- None
Changes in v3:
- None
Changes in v4:
- None
For PAGE size related operations, use PAGE size consts in order to be able to
use different page size in the futur.
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
Changes in v2:
- None
Changes in v3:
- None
Changes in v4:
- None
arch/powerpc/kernel/head_8xx.S | 30
pci_bus_find_capability() is decleared in pci.h, so it is not necessary to do
it again.
This patch removes it.
Signed-off-by: Wei Yang weiy...@linux.vnet.ibm.com
---
arch/powerpc/kernel/pci-common.c |1 -
1 file changed, 1 deletion(-)
diff --git a/arch/powerpc/kernel/pci-common.c
On Fri, Sep 19, 2014 at 05:25:22PM +0800, Wei Yang wrote:
pci_bus_find_capability() is decleared in pci.h, so it is not necessary to do
it again.
This patch removes it.
Signed-off-by: Wei Yang weiy...@linux.vnet.ibm.com
Reviewed-by: Gavin Shan gws...@linux.vnet.ibm.com
Thanks,
Gavin
---
On PPC_8xx, lwz has a 2 cycles latency, and branching also takes 2 cycles.
As the size of the header is minimum 5 words, we can unroll the loop for the
first words to reduce number of branching, and we can re-order the instructions
to limit loading latency.
Signed-off-by: Christophe Leroy
This patchset provides a few optimisations related to IP checksum functions.
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
Tested-by: Christophe Leroy christophe.le...@c-s.fr
---
arch/powerpc/include/asm/checksum.h | 28
arch/powerpc/lib/checksum_32.S
csum_tcpudp_magic() is only a few instructions, and does not modifies any other
register than the returned result. So it is not worth having it as a separate
function and suffer function branching and saving of volatile registers.
This patch makes it inline by use of the already existing
The C version of csum_add() as defined in include/net/checksum.h gives the
following assembly:
0: 7c 04 1a 14 add r0,r4,r3
4: 7c 64 00 10 subfc r3,r4,r0
8: 7c 63 19 10 subfe r3,r3,r3
c: 7c 63 00 50 subfr3,r3,r0
Christophe Leroy christophe.le...@c-s.fr wrote on 2014/09/19 15:57:56:
Subject: [PATCH 2/2] powerpc32: add support for csum_add()
The C version of csum_add() as defined in include/net/checksum.h gives
the
following assembly:
0: 7c 04 1a 14 add r0,r4,r3
4:
Christophe Leroy christophe.le...@c-s.fr wrote on 2014/09/19 15:57:56:
+#define HAVE_ARCH_CSUM_ADD
+static inline __wsum csum_add(__wsum csum, __wsum addend)
+{
+__asm__(\n\
+ addc %0,%0,%1 \n\
+ addze %0,%0 \n\
+
+ : =r (csum)
+ : r (addend), 0(csum));
hmm, I wonder if
On Thu, 2014-09-18 at 18:26 +1000, Michael Neuling wrote:
From: Ian Munsie imun...@au1.ibm.com
Currently msi_bitmap_alloc_hwirqs() will round up any IRQ allocation requests
to the nearest power of 2. eg. ask for 5 IRQs and you'll get 8. This wastes
a
lot of IRQs which can be a scarce
On Fri, 2014-09-19 at 15:16 -0500, Scott Wood wrote:
On Thu, 2014-09-18 at 18:26 +1000, Michael Neuling wrote:
From: Ian Munsie imun...@au1.ibm.com
Currently msi_bitmap_alloc_hwirqs() will round up any IRQ allocation
requests
to the nearest power of 2. eg. ask for 5 IRQs and you'll
On 09/03/14 10:00, Sudeep Holla wrote:
From: Sudeep Holla sudeep.ho...@arm.com
This patch adds initial support for providing processor cache information
to userspace through sysfs interface. This is based on already existing
implementations(x86, ia64, s390 and powerpc) and hence the interface
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