[PATCH] powerpc: mpc85xx: flush the l1 cache before cpu down in kexec
We observe a Zero PT_NOTE entries found warning when vmcore_init()
is running on the dump-capture kernel. Actually the PT_NOTE segments
is not empty, but the entries generated by crash_save_cpu() are not
flushed to the memory before we reset these cores. So we should flush
the l1 cache as what we do in cpu hotplug. With this change, we can
also kill the mpc85xx_smp_flush_dcache_kexec() since that becomes
unnecessary.
Please note: this only fix the issue on e500 core, we still need to
implement the function to flush the l2 cache for the e500mc core.
Fortunately we already had proposing patch for this support [1].
Hope we can fix this issue for e500mc after that merged.
[1] https://lists.ozlabs.org/pipermail/linuxppc-dev/2014-March/115830.html
Signed-off-by: Kevin Hao haoke...@gmail.com
---
arch/powerpc/platforms/85xx/smp.c | 51 +--
1 file changed, 1 insertion(+), 50 deletions(-)
diff --git a/arch/powerpc/platforms/85xx/smp.c
b/arch/powerpc/platforms/85xx/smp.c
index 8631ac5f0e57..b8b821697910 100644
--- a/arch/powerpc/platforms/85xx/smp.c
+++ b/arch/powerpc/platforms/85xx/smp.c
@@ -345,6 +345,7 @@ void mpc85xx_smp_kexec_cpu_down(int crash_shutdown, int
secondary)
local_irq_disable();
if (secondary) {
+ __flush_disable_L1();
atomic_inc(kexec_down_cpus);
/* loop forever */
while (1);
@@ -357,61 +358,11 @@ static void mpc85xx_smp_kexec_down(void *arg)
ppc_md.kexec_cpu_down(0,1);
}
-static void map_and_flush(unsigned long paddr)
-{
- struct page *page = pfn_to_page(paddr PAGE_SHIFT);
- unsigned long kaddr = (unsigned long)kmap_atomic(page);
-
- flush_dcache_range(kaddr, kaddr + PAGE_SIZE);
- kunmap_atomic((void *)kaddr);
-}
-
-/**
- * Before we reset the other cores, we need to flush relevant cache
- * out to memory so we don't get anything corrupted, some of these flushes
- * are performed out of an overabundance of caution as interrupts are not
- * disabled yet and we can switch cores
- */
-static void mpc85xx_smp_flush_dcache_kexec(struct kimage *image)
-{
- kimage_entry_t *ptr, entry;
- unsigned long paddr;
- int i;
-
- if (image-type == KEXEC_TYPE_DEFAULT) {
- /* normal kexec images are stored in temporary pages */
- for (ptr = image-head; (entry = *ptr) !(entry IND_DONE);
-ptr = (entry IND_INDIRECTION) ?
- phys_to_virt(entry PAGE_MASK) : ptr + 1) {
- if (!(entry IND_DESTINATION)) {
- map_and_flush(entry);
- }
- }
- /* flush out last IND_DONE page */
- map_and_flush(entry);
- } else {
- /* crash type kexec images are copied to the crash region */
- for (i = 0; i image-nr_segments; i++) {
- struct kexec_segment *seg = image-segment[i];
- for (paddr = seg-mem; paddr seg-mem + seg-memsz;
-paddr += PAGE_SIZE) {
- map_and_flush(paddr);
- }
- }
- }
-
- /* also flush the kimage struct to be passed in as well */
- flush_dcache_range((unsigned long)image,
- (unsigned long)image + sizeof(*image));
-}
-
static void mpc85xx_smp_machine_kexec(struct kimage *image)
{
int timeout = INT_MAX;
int i, num_cpus = num_present_cpus();
- mpc85xx_smp_flush_dcache_kexec(image);
-
if (image-type == KEXEC_TYPE_DEFAULT)
smp_call_function(mpc85xx_smp_kexec_down, NULL, 0);
--
2.1.0
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Re: [PATCH] i2c: powermac: don't workaround for keywest
Hi, Sorry for the delay, I found this message in my spam folder. Anyway, for my machine model, cat /proc/device-tree/compatible returns: PowerBook4,3MacRISC2MacRISCPower Macintosh It's a 14 in. iBook G3 700 MHz. Regards, Dan On Mon, 5/11/15, Benjamin Herrenschmidt b...@kernel.crashing.org wrote: Subject: Re: [PATCH] i2c: powermac: don't workaround for keywest To: w...@the-dreams.de Cc: linux-...@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, Dan DeVoto dand1...@yahoo.com, Mark Elliott txliteb...@gmail.com Date: Monday, May 11, 2015, 4:26 PM On Mon, 2015-05-11 at 09:34 +0200, w...@the-dreams.de wrote: On Mon, May 11, 2015 at 08:14:47AM +1000, Benjamin Herrenschmidt wrote: On Sun, 2015-05-10 at 20:34 +0200, Wolfram Sang wrote: Okay, so this patch is bogus. I understand now that onyx uses another codec than TAS, so this change will regress on other machines. However, it shows that this unconditional instantiation of the TAS breaks sound on Macintoshs which still need non-aoa sound support. I assume there will be noone in the near future to convert Keywest to AOA, so we'll need to find a hackish way around this instantiation problem. Converting the old macs that use TAS shouldn't be *that* hard, main problem is I don't have the hardware to test... Dan and Mark (on CC) have been very helpful with testing. Maybe they are also in to test the proper solution? Possibly, depends how many machines we can cover. I also have extremely little time, so I'm not that keen on volunteering :-) I'll *try* to have a look some time this or next week. The main problem is the difference in the way the layout of the codec etc... is reported from the DT by the firmware. Otherwise the HW is the same between pre-AOA and post-AOA really ... I do have a bunch of DT snapshots lying around, so I can try to figure out something. Dan, Mark, what machine models specifically do you have ? (compatible property in the DT pls, ie, /proc/device-tree/compatible). Cheers, Ben. ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH] powerpc/iommu: Support hybrid iommu/direct DMA ops for coherent_mask dma_mask
This patch adds the ability to the DMA direct ops to fallback to the IOMMU
ops for coherent alloc/free if the coherent mask of the device isn't
suitable for accessing the direct DMA space and the device also happens
to have an active IOMMU table.
Signed-off-by: Benjamin Herrenschmidt b...@kernel.crashing.org
Tested-by: Brian King brk...@linux.vnet.ibm.com
---
Identical to RFC v3
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 22b0940..cd46474 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -82,6 +82,9 @@ config GENERIC_HWEIGHT
bool
default y
+config ARCH_HAS_DMA_SET_COHERENT_MASK
+bool
+
config PPC
bool
default y
@@ -152,6 +155,7 @@ config PPC
select DCACHE_WORD_ACCESS if PPC64 CPU_LITTLE_ENDIAN
select NO_BOOTMEM
select HAVE_GENERIC_RCU_GUP
+ select ARCH_HAS_DMA_SET_COHERENT_MASK
config GENERIC_CSUM
def_bool CPU_LITTLE_ENDIAN
diff --git a/arch/powerpc/include/asm/device.h
b/arch/powerpc/include/asm/device.h
index 9f1371b..9ce2199 100644
--- a/arch/powerpc/include/asm/device.h
+++ b/arch/powerpc/include/asm/device.h
@@ -10,6 +10,7 @@ struct dma_map_ops;
struct device_node;
#ifdef CONFIG_PPC64
struct pci_dn;
+struct iommu_table;
#endif
/*
@@ -23,13 +24,15 @@ struct dev_archdata {
struct dma_map_ops *dma_ops;
/*
-* When an iommu is in use, dma_data is used as a ptr to the base of the
-* iommu_table. Otherwise, it is a simple numerical offset.
+* These two used to be a union. However, with the hybrid ops we need
+* both so here we store both a DMA offset for direct mappings and
+* an iommu_table for remapped DMA.
*/
- union {
- dma_addr_t dma_offset;
- void*iommu_table_base;
- } dma_data;
+ dma_addr_t dma_offset;
+
+#ifdef CONFIG_PPC64
+ struct iommu_table *iommu_table_base;
+#endif
#ifdef CONFIG_IOMMU_API
void*iommu_domain;
diff --git a/arch/powerpc/include/asm/dma-mapping.h
b/arch/powerpc/include/asm/dma-mapping.h
index 894d538..2e12366 100644
--- a/arch/powerpc/include/asm/dma-mapping.h
+++ b/arch/powerpc/include/asm/dma-mapping.h
@@ -21,12 +21,12 @@
#define DMA_ERROR_CODE (~(dma_addr_t)0x0)
/* Some dma direct funcs must be visible for use in other dma_ops */
-extern void *dma_direct_alloc_coherent(struct device *dev, size_t size,
- dma_addr_t *dma_handle, gfp_t flag,
+extern void *__dma_direct_alloc_coherent(struct device *dev, size_t size,
+dma_addr_t *dma_handle, gfp_t flag,
+struct dma_attrs *attrs);
+extern void __dma_direct_free_coherent(struct device *dev, size_t size,
+ void *vaddr, dma_addr_t dma_handle,
struct dma_attrs *attrs);
-extern void dma_direct_free_coherent(struct device *dev, size_t size,
-void *vaddr, dma_addr_t dma_handle,
-struct dma_attrs *attrs);
extern int dma_direct_mmap_coherent(struct device *dev,
struct vm_area_struct *vma,
void *cpu_addr, dma_addr_t handle,
@@ -106,7 +106,7 @@ static inline void set_dma_ops(struct device *dev, struct
dma_map_ops *ops)
static inline dma_addr_t get_dma_offset(struct device *dev)
{
if (dev)
- return dev-archdata.dma_data.dma_offset;
+ return dev-archdata.dma_offset;
return PCI_DRAM_OFFSET;
}
@@ -114,7 +114,7 @@ static inline dma_addr_t get_dma_offset(struct device *dev)
static inline void set_dma_offset(struct device *dev, dma_addr_t off)
{
if (dev)
- dev-archdata.dma_data.dma_offset = off;
+ dev-archdata.dma_offset = off;
}
/* this will be removed soon */
diff --git a/arch/powerpc/include/asm/iommu.h b/arch/powerpc/include/asm/iommu.h
index e2abbe8..e67e678 100644
--- a/arch/powerpc/include/asm/iommu.h
+++ b/arch/powerpc/include/asm/iommu.h
@@ -2,17 +2,17 @@
* Copyright (C) 2001 Mike Corrigan Dave Engebretsen, IBM Corporation
* Rewrite, cleanup:
* Copyright (C) 2004 Olof Johansson o...@lixom.net, IBM Corporation
- *
+ *
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
- *
+ *
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
- *
+ *
* You should have received a copy of the GNU General
Re: [PATCH 1/6] crypto: md5: add MD5 initial vectors
On Sun, May 17, 2015 at 12:54:12PM +0200, LABBE Corentin wrote: This patch simply adds the MD5 IV in the md5 header. Signed-off-by: LABBE Corentin clabbe.montj...@gmail.com All applied. Thanks! -- Email: Herbert Xu herb...@gondor.apana.org.au Home Page: http://gondor.apana.org.au/~herbert/ PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH V3 09/13] selftests, powerpc: Add test for DSCR value inheritence across fork
Hi Anshuman, Thanks for getting these testcases into the kernel. This patch adds a test to verify that the changed DSCR value inside any process would be inherited to it's child process across the fork system call. One issue I do notice (a bug in my original test cases too), is that we don't restore the DSCR on exit. I'm not sure we need to go to the trouble of saving and restoring it, but we should at least get it back to 0 when done. Also a tiny nit, no need for a newline in perror(): open() failed : Permission denied With those changes you can add: Signed-off-by: Anton Blanchard an...@samba.org to the patches based on my testcases. Anton ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH 2/6] crypto: md5: use md5 IV MD5_HX instead of their raw value
Since MD5 IV are now available in crypto/md5.h, use them.
Signed-off-by: LABBE Corentin clabbe.montj...@gmail.com
---
crypto/md5.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/crypto/md5.c b/crypto/md5.c
index 36f5e5b..33d17e9 100644
--- a/crypto/md5.c
+++ b/crypto/md5.c
@@ -51,10 +51,10 @@ static int md5_init(struct shash_desc *desc)
{
struct md5_state *mctx = shash_desc_ctx(desc);
- mctx-hash[0] = 0x67452301;
- mctx-hash[1] = 0xefcdab89;
- mctx-hash[2] = 0x98badcfe;
- mctx-hash[3] = 0x10325476;
+ mctx-hash[0] = MD5_H0;
+ mctx-hash[1] = MD5_H1;
+ mctx-hash[2] = MD5_H2;
+ mctx-hash[3] = MD5_H3;
mctx-byte_count = 0;
return 0;
--
2.3.6
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[PATCH 1/6] crypto: md5: add MD5 initial vectors
This patch simply adds the MD5 IV in the md5 header.
Signed-off-by: LABBE Corentin clabbe.montj...@gmail.com
---
include/crypto/md5.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/include/crypto/md5.h b/include/crypto/md5.h
index 65f299b..146af82 100644
--- a/include/crypto/md5.h
+++ b/include/crypto/md5.h
@@ -8,6 +8,11 @@
#define MD5_BLOCK_WORDS16
#define MD5_HASH_WORDS 4
+#define MD5_H0 0x67452301UL
+#define MD5_H1 0xefcdab89UL
+#define MD5_H2 0x98badcfeUL
+#define MD5_H3 0x10325476UL
+
struct md5_state {
u32 hash[MD5_HASH_WORDS];
u32 block[MD5_BLOCK_WORDS];
--
2.3.6
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[PATCH 3/6] crypto: powerpc/md5: use md5 IV MD5_HX instead of their raw value
Since MD5 IV are now available in crypto/md5.h, use them.
Signed-off-by: LABBE Corentin clabbe.montj...@gmail.com
---
arch/powerpc/crypto/md5-glue.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/crypto/md5-glue.c b/arch/powerpc/crypto/md5-glue.c
index 452fb4d..9228967 100644
--- a/arch/powerpc/crypto/md5-glue.c
+++ b/arch/powerpc/crypto/md5-glue.c
@@ -37,10 +37,10 @@ static int ppc_md5_init(struct shash_desc *desc)
{
struct md5_state *sctx = shash_desc_ctx(desc);
- sctx-hash[0] = 0x67452301;
- sctx-hash[1] = 0xefcdab89;
- sctx-hash[2] = 0x98badcfe;
- sctx-hash[3] = 0x10325476;
+ sctx-hash[0] = MD5_H0;
+ sctx-hash[1] = MD5_H1;
+ sctx-hash[2] = MD5_H2;
+ sctx-hash[3] = MD5_H3;
sctx-byte_count = 0;
return 0;
--
2.3.6
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[PATCH 5/6] crypto: n2: use md5 IV MD5_HX instead of their raw value
Since MD5 IV are now available in crypto/md5.h, use them.
Signed-off-by: LABBE Corentin clabbe.montj...@gmail.com
---
drivers/crypto/n2_core.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/crypto/n2_core.c b/drivers/crypto/n2_core.c
index 10a9aef..2e8dab9 100644
--- a/drivers/crypto/n2_core.c
+++ b/drivers/crypto/n2_core.c
@@ -1281,10 +1281,10 @@ static const char md5_zero[MD5_DIGEST_SIZE] = {
0xe9, 0x80, 0x09, 0x98, 0xec, 0xf8, 0x42, 0x7e,
};
static const u32 md5_init[MD5_HASH_WORDS] = {
- cpu_to_le32(0x67452301),
- cpu_to_le32(0xefcdab89),
- cpu_to_le32(0x98badcfe),
- cpu_to_le32(0x10325476),
+ cpu_to_le32(MD5_H0),
+ cpu_to_le32(MD5_H1),
+ cpu_to_le32(MD5_H2),
+ cpu_to_le32(MD5_H3),
};
static const char sha1_zero[SHA1_DIGEST_SIZE] = {
0xda, 0x39, 0xa3, 0xee, 0x5e, 0x6b, 0x4b, 0x0d, 0x32,
--
2.3.6
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[PATCH 4/6] crypto: sparc/md5: use md5 IV MD5_HX instead of their raw value
Since MD5 IV are now available in crypto/md5.h, use them.
Signed-off-by: LABBE Corentin clabbe.montj...@gmail.com
---
arch/sparc/crypto/md5_glue.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/sparc/crypto/md5_glue.c b/arch/sparc/crypto/md5_glue.c
index b688731..c9d2b92 100644
--- a/arch/sparc/crypto/md5_glue.c
+++ b/arch/sparc/crypto/md5_glue.c
@@ -33,10 +33,10 @@ static int md5_sparc64_init(struct shash_desc *desc)
{
struct md5_state *mctx = shash_desc_ctx(desc);
- mctx-hash[0] = cpu_to_le32(0x67452301);
- mctx-hash[1] = cpu_to_le32(0xefcdab89);
- mctx-hash[2] = cpu_to_le32(0x98badcfe);
- mctx-hash[3] = cpu_to_le32(0x10325476);
+ mctx-hash[0] = cpu_to_le32(MD5_H0);
+ mctx-hash[1] = cpu_to_le32(MD5_H1);
+ mctx-hash[2] = cpu_to_le32(MD5_H2);
+ mctx-hash[3] = cpu_to_le32(MD5_H3);
mctx-byte_count = 0;
return 0;
--
2.3.6
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[PATCH 6/6] crypto: octeon: use md5 IV MD5_HX instead of their raw value
Since MD5 IV are now available in crypto/md5.h, use them.
Signed-off-by: LABBE Corentin clabbe.montj...@gmail.com
---
arch/mips/cavium-octeon/crypto/octeon-md5.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/mips/cavium-octeon/crypto/octeon-md5.c
b/arch/mips/cavium-octeon/crypto/octeon-md5.c
index 12dccdb..af4c712 100644
--- a/arch/mips/cavium-octeon/crypto/octeon-md5.c
+++ b/arch/mips/cavium-octeon/crypto/octeon-md5.c
@@ -69,10 +69,10 @@ static int octeon_md5_init(struct shash_desc *desc)
{
struct md5_state *mctx = shash_desc_ctx(desc);
- mctx-hash[0] = cpu_to_le32(0x67452301);
- mctx-hash[1] = cpu_to_le32(0xefcdab89);
- mctx-hash[2] = cpu_to_le32(0x98badcfe);
- mctx-hash[3] = cpu_to_le32(0x10325476);
+ mctx-hash[0] = cpu_to_le32(MD5_H0);
+ mctx-hash[1] = cpu_to_le32(MD5_H1);
+ mctx-hash[2] = cpu_to_le32(MD5_H2);
+ mctx-hash[3] = cpu_to_le32(MD5_H3);
mctx-byte_count = 0;
return 0;
--
2.3.6
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