On 11/05/2015 12:12 AM, Gavin Shan wrote:
This adds standalone driver to support PCI hotplug for PowerPC PowerNV
platform that runs on top of skiboot firmware. The firmware identifies
hotpluggable slots and marked their device tree node with proper
"ibm,slot-pluggable" and "ibm,reset-by-firmware"
HMIs (Hypervisor Management|Maintenance Interrupts) are a class of interrupt
on POWER systems.
HMI support has traditionally been exceptionally difficult to test. However
Skiboot ships a tool that, with the correct magic numbers, will inject them.
This, therefore, is a first pass at a script to i
On 11/05/2015 12:12 AM, Gavin Shan wrote:
The pdn (struct pci_dn) instances are allocated from memblock or
bootmem when creating PCI controller (hoses) in setup_arch(). PCI
hotplug, which will be supported by proceeding patches, release
PCI device nodes and their corresponding pdn on unplugging e
On 11/05/2015 12:12 AM, Gavin Shan wrote:
This renames pcibios_find_pci_bus() to pci_find_bus_by_node() to
avoid conflicts with those PCI subsystem weak function names, which
have prefix "pcibios". No logical changes introduced.
Could be merged into [PATCH v7 28/50] powerpc/pci: Rename
pcibios
Load up the non volatile FPU and VMX regs and ensure that they are the
expected value in a signal handler
Signed-off-by: Cyril Bur
---
tools/testing/selftests/powerpc/math/Makefile | 4 +-
tools/testing/selftests/powerpc/math/fpu_signal.c | 119 +
tools/testing/selftest
Test that the non volatile floating point and Altivec registers get
correctly preserved across the fork() syscall.
fork() works nicely for this purpose, the registers should be the same for
both parent and child
Signed-off-by: Cyril Bur
---
tools/testing/selftests/powerpc/Makefile |
This patch adds the ability to be able to save the VSX registers to the
thread struct without giving up (disabling the facility) next time the
process returns to userspace.
This patch builds on a previous optimisation for the FPU and VEC registers
in the thread copy path to avoid a possibly pointl
This patch adds the ability to be able to save the VEC registers to the
thread struct without giving up (disabling the facility) next time the
process returns to userspace.
This patch builds on a previous optimisation for the FPU registers in the
thread copy path to avoid a possibly pointless relo
Currently the FPU, VEC and VSX facilities are lazily loaded. This is not a
problem unless a process is using these facilities.
Modern versions of GCC are very good at automatically vectorising code, new
and modernised workloads make use of floating point and vector facilities,
even the kernel make
This patch adds the ability to be able to save the FPU registers to the
thread struct without giving up (disabling the facility) next time the
process returns to userspace.
This patch optimises the thread copy path (as a result of a fork() or
clone()) so that the parent thread can return to usersp
With threads leaving the math bits enabled in their saved MSR to indicate
that the hardware is hot and a restore is not needed, children need to turn
it off as when they do get scheduled, there's no way their registers could
have been hot.
Signed-off-by: Cyril Bur
---
arch/powerpc/kernel/process
Loop in assembly checking the registers with many threads.
Signed-off-by: Cyril Bur
---
tools/testing/selftests/powerpc/math/Makefile | 7 +-
tools/testing/selftests/powerpc/math/fpu_asm.S | 34
tools/testing/selftests/powerpc/math/fpu_preempt.c | 92 ++
to
Hi,
These patches are an extension of the work done by Anton
https://patchwork.ozlabs.org/patch/537621/, they'll need to be applied on
top of them.
The goal of these patches is to rework how the 'math' registers (FP, VEC
and VSX) are context switched. Currently the kernel adopts a lazy approach,
On 11/05/2015 12:12 AM, Gavin Shan wrote:
This renames traverse_pci_devices() to pci_traverse_device_nodes().
Why? pci_traverse_device_nodes() is not moved to some more generic header
where is would be required to have a standard prefix. And the ppc-pci.h
header does not use any standard pref
On 11/05/2015 12:12 AM, Gavin Shan wrote:
This renames pcibios_{add,remove}_pci_devices() to avoid conflicts
with names of the weak functions in PCI subsystem, which have the
prefix "pcibios". No logical changes introduced.
As you mentioned before, the patchset is organized as "code refactorin
On 11/05/2015 12:12 AM, Gavin Shan wrote:
This adds a reference count of PE, representing the number of PCI
devices associated with the PE. The reference count is increased
or decreased when PCI devices join or leave the PE. Once it becomes
zero, the PE together with its used resources (IO, MMIO,
Hi Joseph,
On Tue, 2015-11-17 at 15:55 +, Joseph Myers wrote:
> On Tue, 17 Nov 2015, kbuild test robot wrote:
> > tree: https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git
> > test
> > head: e37d8480fbd6b9ad3665ac85a903098413ba67ae
> > commit: 71fa67f178c6c3c338d0b99644bce
On 11/17/2015 08:03 PM, Gavin Shan wrote:
On Tue, Nov 17, 2015 at 04:08:30PM +1100, Alexey Kardashevskiy wrote:
On 11/05/2015 12:12 AM, Gavin Shan wrote:
In current implementation, the PEs that are allocated or picked
>from the reserved list are identified by PE number. The PE instance
has to
On 11/17/2015 07:48 PM, Gavin Shan wrote:
On Tue, Nov 17, 2015 at 12:07:17PM +1100, Alexey Kardashevskiy wrote:
On 11/05/2015 12:12 AM, Gavin Shan wrote:
In pnv_ioda_setup_dma(), it's unnecessary to calculate the DMA32
segments for PEs on PHB3 as the whole available DMA32 space can
be assigned
On Tue, 2015-11-17 at 16:05 -0600, Rob Herring wrote:
> On Mon, Nov 16, 2015 at 8:07 PM, Scott Wood wrote:
> > On Mon, 2015-11-16 at 11:26 -0600, Rob Herring wrote:
> > > We just merged a common wakeup source binding[1]. It doesn't really work
> > > in a similar way to what you have done, but I'd
On Mon, Nov 16, 2015 at 8:07 PM, Scott Wood wrote:
> On Mon, 2015-11-16 at 11:26 -0600, Rob Herring wrote:
>> +Sudeep
>>
>> On Mon, Oct 26, 2015 at 02:44:12PM +0800, Dongsheng Wang wrote:
>> > From: Wang Dongsheng
>> >
>> > RCPM is the Run Control and Power Management module performs all
>> > dev
Mark Brown writes:
> On Tue, Nov 17, 2015 at 07:15:59AM -0200, Mauro Carvalho Chehab wrote:
>> Now that media has its own subdirectory inside platform_data,
>> let's move the headers that are already there to such subdir.
>
> Acked-by: Mark Brown
Acked-by: Robert Jarzmik
Cheers.
--
Robert
__
Hi Christophe,
[auto build test WARNING on powerpc/next]
[also build test WARNING on v4.4-rc1 next-20151117]
url:
https://github.com/0day-ci/linux/commits/Christophe-Leroy/powerpc-8xx-Use-large-pages-for-RAM-and-IMMR-and-other-improvments/20151117-221800
base: https://git.kernel.org/pub
On Tue, 17 Nov 2015, kbuild test robot wrote:
> tree: https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git test
> head: e37d8480fbd6b9ad3665ac85a903098413ba67ae
> commit: 71fa67f178c6c3c338d0b99644bce808f2f0965e [7/8] sparc/math-emu: Move
> sparc from math-emu-old to math-emu
> c
Hi Christophe,
[auto build test ERROR on powerpc/next]
[also build test ERROR on v4.4-rc1 next-20151117]
url:
https://github.com/0day-ci/linux/commits/Christophe-Leroy/powerpc-8xx-Use-large-pages-for-RAM-and-IMMR-and-other-improvments/20151117-221800
base: https://git.kernel.org/pub/scm
On recent kernels, with some debug options like for instance
CONFIG_LOCKDEP, the BSS requires more than 8M memory, allthough
the kernel code fits in the first 8M.
Today, it is necessary to activate CONFIG_PIN_TLB to get more than 8M
at startup, allthough pinning TLB is not necessary for that.
This
On PPC8xx, flushing instruction cache is performed by writing
in register SPRN_IC_CST. This registers suffers CPU6 ERRATA.
The patch rewrites the fonction in C so that CPU6 ERRATA will
be handled transparently
Signed-off-by: Christophe Leroy
---
v2: no change
v3: no change
arch/powerpc/kernel/m
On a live running system (VoIP gateway for Air Trafic Control), over
a 10 minutes period (with 277s idle), we get 87 millions DTLB misses
and approximatly 35 secondes are spent in DTLB handler.
This represents 5.8% of the overall time and even 10.8% of the
non-idle time.
Among those 87 millions DTL
There is no real need to have set_context() in assembly.
Now that we have mtspr() handling CPU6 ERRATA directly, we
can rewrite set_context() in C language for easier maintenance.
Signed-off-by: Christophe Leroy
---
v2: no change
v3: no change
arch/powerpc/kernel/head_8xx.S | 44 ---
ioremap_base is not initialised and is nowhere used so remove it
Signed-off-by: Christophe Leroy
---
v2: no change
v3: fix comment as well
arch/powerpc/include/asm/pgtable-ppc32.h| 2 +-
arch/powerpc/mm/mmu_decl.h | 1 -
arch/powerpc/mm/pgtable_32.c| 3 +-
Memory: 124428K/131072K available (3748K kernel code, 188K rwdata,
648K rodata, 508K init, 290K bss, 6644K reserved)
Kernel virtual memory layout:
* 0xfffdf000..0xf000 : fixmap
* 0xfde0..0xfe00 : consistent mem
* 0xfddf6000..0xfde0 : early ioremap
* 0xc900..0xfddf6000
The fixmap related functions try to map kernel pages that are
already mapped through Large TLBs. pte_offset_kernel() has to
return NULL for LTLBs, otherwise the caller will try to access
level 2 table which doesn't exist
Signed-off-by: Christophe Leroy
---
v3: New
arch/powerpc/include/asm/pgtab
Once the linear memory space has been mapped with 8Mb pages, as
seen in the related commit, we get 11 millions DTLB missed during
the reference 600s period. 77% of the misses are on user addresses
and 23% are on kernel addresses (1 fourth for linear address space
and 3 fourth for virtual address sp
IMMR is now mapped by page tables so it is not
anymore necessary to PIN TLBs
Signed-off-by: Christophe Leroy
---
v2: no change
v3: no change
arch/powerpc/Kconfig.debug | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/powerpc/Kconfig.debug b/arch/powerpc/Kconfig.debug
index 3a510f4..8523a
The main purpose of this patchset is to dramatically reduce the time
spent in DTLB miss handler. This is achieved by:
1/ Mapping RAM with 8M pages
2/ Mapping IMMR with a fixed 512K page
On a live running system (VoIP gateway for Air Trafic Control), over
a 10 minutes period (with 277s idle), we ge
Now we have a 8xx specific .c file for that so put it in there
as other powerpc variants do
Signed-off-by: Christophe Leroy
---
v2: no change
v3: no change
arch/powerpc/mm/8xx_mmu.c | 17 +
arch/powerpc/mm/init_32.c | 19 ---
2 files changed, 17 insertions(+), 19
Commit 771168494719 ("[POWERPC] Remove unused machine call outs")
removed the call to setup_io_mappings(), so remove the associated
progress line message
Signed-off-by: Christophe Leroy
---
v2: no change
v3: no change
arch/powerpc/mm/init_32.c | 4
1 file changed, 4 deletions(-)
diff --gi
This patch adds inline functions to use dcbz, dcbi, dcbf, dcbst
from C functions
Signed-off-by: Christophe Leroy
---
v2: new
v3: no change
arch/powerpc/include/asm/cache.h | 19 +++
1 file changed, 19 insertions(+)
diff --git a/arch/powerpc/include/asm/cache.h b/arch/powerpc/in
Now the noltlbs kernel parameter is also applicable to PPC8xx
Signed-off-by: Christophe Leroy
---
v2: no change
v3: no change
Documentation/kernel-parameters.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/kernel-parameters.txt
b/Documentation/kernel-param
Add missing SPRN defines into reg_8xx.h
Some of them are defined in mmu-8xx.h, so we include mmu-8xx.h in
reg_8xx.h, for that we remove references to PAGE_SHIFT in mmu-8xx.h
to have it self sufficient, as includers of reg_8xx.h don't all
include asm/page.h
Signed-off-by: Christophe Leroy
---
v2:
CPU6 ERRATA is now handled directly in mtspr(), so we can use the
standard set_dec() fonction in all cases.
Signed-off-by: Christophe Leroy
---
v2: no change
v3: no change
arch/powerpc/include/asm/time.h | 6 +-
arch/powerpc/kernel/head_8xx.S | 18 --
2 files changed, 1 in
We are spending between 40 and 160 cycles with a mean of 65 cycles in
the DTLB handling routine (measured with mftbl) so make it more
simple althought it adds one instruction.
With this modification, we get three registers available at all time,
which will help with following patch.
Signed-off-by:
clear_pages() is never used expect by clear_page, and PPC32 is the
only architecture (still) having this function. Neither PPC64 nor
any other architecture has it.
This patch removes clear_pages() and moves clear_page() function
inline (same as PPC64) as it only is a few isns
Signed-off-by: Chris
This simplification helps the compiler. We now have only one test
instead of two, so it reduces the number of branches.
Signed-off-by: Christophe Leroy
---
v2: new
v3: no change
arch/powerpc/mm/dma-noncoherent.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/mm
flush/clean/invalidate _dcache_range() functions are all very
similar and are quite short. They are mainly used in __dma_sync()
perf_event locate them in the top 3 consumming functions during
heavy ethernet activity
They are good candidate for inlining, as __dma_sync() does
almost nothing but call
x_mapped_by_bats() and x_mapped_by_tlbcam() serve the same kind of
purpose, and are never defined at the same time.
So rename them x_block_mapped() and define them in the relevant
places
Signed-off-by: Christophe Leroy
---
v2: no change
v3: Functions are mutually exclusive so renamed iaw Scott co
Remove one instruction in mulhdu
Signed-off-by: Christophe Leroy
---
v2: new
v3: no change
arch/powerpc/kernel/misc_32.S | 11 +--
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/arch/powerpc/kernel/misc_32.S b/arch/powerpc/kernel/misc_32.S
index 1597424..870dc63 100644
--
MPC8xx has an ERRATA on the use of mtspr() for some registers
This patch includes the ERRATA handling directly into mtspr() macro
so that mtspr() users don't need to bother about that errata
Signed-off-by: Christophe Leroy
---
v2: no change
v3: no change
arch/powerpc/include/asm/reg.h | 2
Inlining of _dcache_range() functions has shown that the compiler
does the same thing a bit better with one insn less
Signed-off-by: Christophe Leroy
---
v2: new
v3: no change
arch/powerpc/kernel/misc_32.S | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/ker
On 17.11.2015 10:23, Arnd Bergmann wrote:
On Tuesday 17 November 2015 07:15:59 Mauro Carvalho Chehab wrote:
Now that media has its own subdirectory inside platform_data,
let's move the headers that are already there to such subdir.
Acked-by: Arnd Bergmann
_
On Tue, Nov 17, 2015 at 07:15:59AM -0200, Mauro Carvalho Chehab wrote:
> Now that media has its own subdirectory inside platform_data,
> let's move the headers that are already there to such subdir.
Acked-by: Mark Brown
signature.asc
Description: PGP signature
__
On Tuesday 17 November 2015 11:43:27 Anton Bondarenko wrote:
> On 17.11.2015 10:23, Arnd Bergmann wrote:
> > On Tuesday 17 November 2015 07:15:59 Mauro Carvalho Chehab wrote:
> >> Now that media has its own subdirectory inside platform_data,
> >> let's move the headers that are already there to suc
On Mon, 2015-11-16 at 21:05 +1100, Michael Ellerman wrote:
> On Fri, 2015-11-13 at 15:57 +1100, Michael Neuling wrote:
>
> > Currently we allow both the MSR T and S bits to be set by userspace
> > on
> > a signal return. Unfortunately this is a reserved configuration
> > and
> > will cause a TM B
hOn Mon, 2015-11-16 at 21:24 +1100, Michael Ellerman wrote:
> On Fri, 2015-11-13 at 15:57 +1100, Michael Neuling wrote:
>
> > Test the kernel's signal return code to ensure that it doesn't
> > crash
> > when both the transactional and suspend MSR bits are set in the
> > signal
> > context.
> >
>
On Mon, 2015-11-16 at 20:27 +1100, Michael Ellerman wrote:
> On Fri, 2015-11-13 at 15:57 +1100, Michael Neuling wrote:
>
> > Print the MSR TM bits in oops messages. This appends them to the
> > end
> > like this:
> > MSR: 800502823031
> >
> > You get the TM[] only if at least one TM MSR bi
Now that media has its own subdirectory inside platform_data,
let's move the headers that are already there to such subdir.
After moving those files, the references were adjusted using this
script:
MAIN_DIR="linux/platform_data/"
PREV_DIR="linux/platform_data/"
DIRS="media/"
echo
On Tuesday 17 November 2015 07:15:59 Mauro Carvalho Chehab wrote:
> Now that media has its own subdirectory inside platform_data,
> let's move the headers that are already there to such subdir.
>
>
Acked-by: Arnd Bergmann
___
Linuxppc-dev mailing list
On Tue, Nov 17, 2015 at 06:57:20PM +1100, Alexey Kardashevskiy wrote:
>On 11/05/2015 12:12 AM, Gavin Shan wrote:
>>Currently, the PEs and their associated resources are assigned
>>in ppc_md.pcibios_fixup() except those used by SRIOV VFs. The
>>function is called for once after PCI probing and resou
On Tue, Nov 17, 2015 at 05:04:42PM +1100, Alexey Kardashevskiy wrote:
>On 11/05/2015 12:12 AM, Gavin Shan wrote:
>>We're going to reserve/assign PEs when pcibios_setup_bridge() is
>>called. The function won't be called for root bus as it doesn't
>>have parent bridge. However, the root bus still nee
On Tue, Nov 17, 2015 at 04:08:30PM +1100, Alexey Kardashevskiy wrote:
>On 11/05/2015 12:12 AM, Gavin Shan wrote:
>>In current implementation, the PEs that are allocated or picked
>>from the reserved list are identified by PE number. The PE instance
>>has to be picked according to the PE number even
On Tue, Nov 17, 2015 at 12:07:17PM +1100, Alexey Kardashevskiy wrote:
>On 11/05/2015 12:12 AM, Gavin Shan wrote:
>>In pnv_ioda_setup_dma(), it's unnecessary to calculate the DMA32
>>segments for PEs on PHB3 as the whole available DMA32 space can
>>be assigned to one specific PE on PHB3.
>>
>>This s
On Tue, Nov 17, 2015 at 03:43:28PM +1100, Alexey Kardashevskiy wrote:
>On 11/17/2015 02:04 PM, Gavin Shan wrote:
>>On Tue, Nov 17, 2015 at 01:37:22PM +1100, Alexey Kardashevskiy wrote:
>>>On 11/17/2015 12:42 PM, Gavin Shan wrote:
On Mon, Nov 16, 2015 at 07:02:18PM +1100, Alexey Kardashevskiy wr
tree: https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git test
head: e37d8480fbd6b9ad3665ac85a903098413ba67ae
commit: 71fa67f178c6c3c338d0b99644bce808f2f0965e [7/8] sparc/math-emu: Move
sparc from math-emu-old to math-emu
config: sparc-defconfig (attached as .config)
reproduce:
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