Re: [RFC PATCH 2/2] powerpc/mm: Replace _PAGE_USER with _PAGE_PRIV

Benjamin Herrenschmidt writes: > On Fri, 2016-02-26 at 08:50 +0530, Aneesh Kumar K.V wrote: >> _PAGE_PRIV means the page can be accessed only by kernel. This is >> done >> to keep pte bits similar to PowerISA 3.0 radix PTE format. User >> pages are now makred by

Re: [PATCH 8/9] powerpc: simplify csum_add(a, b) in case a or b is constant 0

Le 23/10/2015 05:33, Scott Wood a écrit : On Tue, 2015-09-22 at 16:34 +0200, Christophe Leroy wrote: Simplify csum_add(a, b) in case a or b is constant 0 Signed-off-by: Christophe Leroy --- arch/powerpc/include/asm/checksum.h | 6 ++ 1 file changed, 6

Re: [PATCH 4/9] powerpc: inline ip_fast_csum()

Le 23/09/2015 07:43, Denis Kirjanov a écrit : On 9/22/15, Christophe Leroy wrote: In several architectures, ip_fast_csum() is inlined There are functions like ip_send_check() which do nothing much more than calling ip_fast_csum(). Inlining ip_fast_csum() allows the

[PATCH 9/9] powerpc: Add the ability to save VSX without giving it up

This patch adds the ability to be able to save the VSX registers to the thread struct without giving up (disabling the facility) next time the process returns to userspace. This patch builds on a previous optimisation for the FPU and VEC registers in the thread copy path to avoid a possibly

[PATCH 0/9] FP/VEC/VSX switching optimisations

Cover-letter for V1 of the series is at https://lists.ozlabs.org/pipermail/linuxppc-dev/2015-November/136350.html Cover-letter for V2 of the series is at https://lists.ozlabs.org/pipermail/linuxppc-dev/2016-January/138054.html Changes in V3: Addressed review comments from Michael Neuling - Made

[PATCH 5/9] powerpc: Restore FPU/VEC/VSX if previously used

Currently the FPU, VEC and VSX facilities are lazily loaded. This is not a problem unless a process is using these facilities. Modern versions of GCC are very good at automatically vectorising code, new and modernised workloads make use of floating point and vector facilities, even the kernel

[PATCH 7/9] powerpc: Add the ability to save FPU without giving it up

This patch adds the ability to be able to save the FPU registers to the thread struct without giving up (disabling the facility) next time the process returns to userspace. This patch optimises the thread copy path (as a result of a fork() or clone()) so that the parent thread can return to

[PATCH 8/9] powerpc: Add the ability to save Altivec without giving it up

This patch adds the ability to be able to save the VEC registers to the thread struct without giving up (disabling the facility) next time the process returns to userspace. This patch builds on a previous optimisation for the FPU registers in the thread copy path to avoid a possibly pointless

[PATCH 6/9] powerpc: Prepare for splitting giveup_{fpu, altivec, vsx} in two

This prepares for the decoupling of saving {fpu,altivec,vsx} registers and marking {fpu,altivec,vsx} as being unused by a thread. Currently giveup_{fpu,altivec,vsx}() does both however optimisations to task switching can be made if these two operations are decoupled. save_all() will permit the

[PATCH 3/9] selftests/powerpc: Test FPU and VMX regs in signal ucontext

Load up the non volatile FPU and VMX regs and ensure that they are the expected value in a signal handler Signed-off-by: Cyril Bur --- tools/testing/selftests/powerpc/math/.gitignore | 2 + tools/testing/selftests/powerpc/math/Makefile | 4 +-

[PATCH 2/9] selftests/powerpc: Test preservation of FPU and VMX regs across preemption

Loop in assembly checking the registers with many threads. Signed-off-by: Cyril Bur --- tools/testing/selftests/powerpc/math/.gitignore| 2 + tools/testing/selftests/powerpc/math/Makefile | 5 +- tools/testing/selftests/powerpc/math/fpu_asm.S | 36 +++

[PATCH 4/9] powerpc: Explicitly disable math features when copying thread

Currently when threads get scheduled off they always giveup the FPU, Altivec (VMX) and Vector (VSX) units if they were using them. When they are scheduled back on a fault is then taken to enable each facility and load registers. As a result explicitly disabling FPU/VMX/VSX has not been necessary.

[PATCH 1/9] selftests/powerpc: Test the preservation of FPU and VMX regs across syscall

Test that the non volatile floating point and Altivec registers get correctly preserved across the fork() syscall. fork() works nicely for this purpose, the registers should be the same for both parent and child Signed-off-by: Cyril Bur ---

Re: [PATCH v10 2/2] cpufreq: powernv: Add sysfs attributes to show throttle stats

On 26-02-16, 16:06, Shilpasri G Bhat wrote: > +static int powernv_cpufreq_policy_notifier(struct notifier_block *nb, > +unsigned long action, void *data) > +{ > + struct cpufreq_policy *policy = data; > + int ret; > + > + if (action ==

[PATCH] selftests/powerpc: Remove -flto from common CFLAGS

LTO can cause GCC to inline some functions which have attributes set. The act of inlining the functions can lead to GCC forgetting about the attributes which leads to incorrect tests. Notable example being: __attribute__((__target__("no-vsx"))) LTO can also interact strangely with custom assembly

Re: [PATCH v5 1/9] selftests/powerpc: Test the preservation of FPU and VMX regs across syscall

On 2016/02/26 09:18AM, Cyril Bur wrote: > On Thu, 25 Feb 2016 11:52:05 +0530 > "Naveen N. Rao" wrote: > > > On 2016/02/25 10:44AM, Cyril Bur wrote: > > > On Wed, 24 Feb 2016 19:57:38 +0530 > > > "Naveen N. Rao" wrote: > > > >

[PATCH] cxl: Ignore probes for virtual afu pci devices

Add a check at the beginning of cxl_probe function to ignore virtual pci devices created for each afu registered. This fixes the the errors messages logged about missing CXL vsec, when cxl probe is unable to find necessary vsec entries in device pci config space. The error message logged are of

Re: [RFC PATCH] powerpc/mm: Use big endian page table for book3s 64

On 29/02/16 12:59, Balbir Singh wrote: > > On 26/02/16 14:53, Aneesh Kumar K.V wrote: >> This enables us to share the same page table code for >> both radix and hash. Radix use a hardware defined big endian > ^uses >> page table >> >> Asm -> C conversion makes it

Re: [RFC PATCH 2/2] powerpc/mm: Replace _PAGE_USER with _PAGE_PRIV

On Fri, 2016-02-26 at 08:50 +0530, Aneesh Kumar K.V wrote: > _PAGE_PRIV means the page can be accessed only by kernel. This is > done > to keep pte bits similar to PowerISA 3.0 radix PTE format. User > pages are now makred by clearing _PAGE_PRIV bit. Very minor nit: It's not clear that PRIV means

Re: [RFC PATCH] powerpc/mm: Use big endian page table for book3s 64

On 26/02/16 14:53, Aneesh Kumar K.V wrote: > This enables us to share the same page table code for > both radix and hash. Radix use a hardware defined big endian ^uses > page table > > Asm -> C conversion makes it simpler to build code for both little > and big