> -Original Message-
> From: Ulf Hansson [mailto:ulf.hans...@linaro.org]
> Sent: Tuesday, April 05, 2016 7:28 PM
> To: Yangbo Lu
> Cc: devicet...@vger.kernel.org; linux-arm-ker...@lists.infradead.org;
> linux-ker...@vger.kernel.org; linuxppc-dev@lists.ozlabs.org; linux-
> c...@vger.kernel.o
On 27/03/16 19:23, Aneesh Kumar K.V wrote:
> We also add mach dep call back for updating partition table entry.
The changelog needs to be enhanced.
> Signed-off-by: Aneesh Kumar K.V
> ---
> arch/powerpc/include/asm/book3s/64/mmu.h | 31 +--
> arch/powerpc/include/asm
On 04/06/2016 12:41 PM, David Gibson wrote:
On Wed, Apr 06, 2016 at 11:45:34AM +1000, Alexey Kardashevskiy wrote:
Ping?
On 03/24/2016 12:42 PM, Alexey Kardashevskiy wrote:
IBM POWER8 NVlink systems come with Tesla K40-ish GPUs each of which
also has a couple of fast speed links (NVLink). The i
On 2016/4/6 8:00, Gavin Shan wrote:
On Tue, Apr 05, 2016 at 09:46:44PM +0800, Yongji Xie wrote:
This patch enables mmapping MSI-X tables if
hardware supports interrupt remapping which
can ensure that a given pci device can only
shoot the MSIs assigned for it.
Signed-off-by: Yongji Xie
---
driv
On 2016/4/6 8:11, Gavin Shan wrote:
On Tue, Apr 05, 2016 at 09:46:43PM +0800, Yongji Xie wrote:
I'm trying to find a proper way to indicate
the capability of interrupt remapping on PPC64
because we need this to determine whether it is
safe to mmap MSI-X table in VFIO driver.
There is a existing
On 2016/4/6 9:43, Gavin Shan wrote:
On Tue, Apr 05, 2016 at 09:43:31PM +0800, Yongji Xie wrote:
When using resource_alignment kernel parameter,
the current implement reassigns the alignment by
changing resources' size which can potentially
break some drivers. For example, the driver uses
the siz
On Wed, Apr 06, 2016 at 11:45:34AM +1000, Alexey Kardashevskiy wrote:
> Ping?
>
> On 03/24/2016 12:42 PM, Alexey Kardashevskiy wrote:
> >IBM POWER8 NVlink systems come with Tesla K40-ish GPUs each of which
> >also has a couple of fast speed links (NVLink). The interface to links
> >is exposed as a
On 2016/4/6 8:48, Gavin Shan wrote:
On Tue, Apr 05, 2016 at 09:43:29PM +0800, Yongji Xie wrote:
The resource_alignment will releases memory
resources allocated by firmware so that kernel
can reassign new resources later on. But this
will cause the problem that no resources can be
allocated by ke
On 2016/4/6 8:55, Gavin Shan wrote:
On Tue, Apr 05, 2016 at 09:43:30PM +0800, Yongji Xie wrote:
Now we use the IORESOURCE_STARTALIGN to identify
bridge resources in __assign_resources_sorted().
That's quite fragile. We can't make sure that
the PCI devices' resources will not use
IORESOURCE_START
Ping?
On 03/24/2016 12:42 PM, Alexey Kardashevskiy wrote:
IBM POWER8 NVlink systems come with Tesla K40-ish GPUs each of which
also has a couple of fast speed links (NVLink). The interface to links
is exposed as an emulated PCI bridge which is included into the same
IOMMU group as the correspond
On Tue, Apr 05, 2016 at 09:43:31PM +0800, Yongji Xie wrote:
>When using resource_alignment kernel parameter,
>the current implement reassigns the alignment by
>changing resources' size which can potentially
>break some drivers. For example, the driver uses
>the size to locate some register whose le
On Tue, Apr 05, 2016 at 09:43:30PM +0800, Yongji Xie wrote:
>Now we use the IORESOURCE_STARTALIGN to identify
>bridge resources in __assign_resources_sorted().
>That's quite fragile. We can't make sure that
>the PCI devices' resources will not use
>IORESOURCE_STARTALIGN any more.
>
>In this patch,
On Tue, Apr 05, 2016 at 09:43:29PM +0800, Yongji Xie wrote:
>The resource_alignment will releases memory
>resources allocated by firmware so that kernel
>can reassign new resources later on. But this
>will cause the problem that no resources can be
>allocated by kernel if PCI_PROBE_ONLY was set,
>e
On Tue, Apr 05, 2016 at 09:46:43PM +0800, Yongji Xie wrote:
>I'm trying to find a proper way to indicate
>the capability of interrupt remapping on PPC64
>because we need this to determine whether it is
>safe to mmap MSI-X table in VFIO driver.
>
>There is a existing flag for this in the IOMMU
>spac
On Tue, Apr 05, 2016 at 09:46:44PM +0800, Yongji Xie wrote:
>This patch enables mmapping MSI-X tables if
>hardware supports interrupt remapping which
>can ensure that a given pci device can only
>shoot the MSIs assigned for it.
>
>Signed-off-by: Yongji Xie
>---
> drivers/vfio/pci/vfio_pci.c
On 27/03/16 19:23, Aneesh Kumar K.V wrote:
> The radix variant is going to require a flush_tlb_range. With
> flush_tlb_range added, ptep_clear_flush_young is same as the generic
> version. So drop the powerpc specific variant
>
> Signed-off-by: Aneesh Kumar K.V
>
The changelog is same as 11/65..
From: Thomas Falcon
Date: Fri, 1 Apr 2016 17:20:35 -0500
> Enable RX Checksum offload feature in the ibmvnic driver.
>
> Signed-off-by: Thomas Falcon
Applied.
___
Linuxppc-dev mailing list
Linuxppc-dev@lists.ozlabs.org
https://lists.ozlabs.org/listi
From: Thomas Falcon
Date: Fri, 1 Apr 2016 17:20:34 -0500
> Allow the VNIC driver to provide descriptors containing
> L2/L3/L4 headers to firmware. This feature is needed
> for greater hardware compatibility and enablement of checksum
> and TCP offloading features.
>
> A new function is include
On 27/03/16 19:23, Aneesh Kumar K.V wrote:
> The radix variant is going to require a flush_pmd_tlb_range. With
> flush_pmd_tlb_range added, pmdp_clear_flush_young is same as the generic
> version. So drop the powerpc specific variant
>
> Signed-off-by: Aneesh Kumar K.V
>
Make sense, what happens
On 5 April 2016 7:56:23 pm AEST, Benjamin Herrenschmidt
wrote:
>On Tue, 2016-04-05 at 19:35 +1000, Michael Ellerman wrote:
>> Shouldn't we be clearing the user feature there too?
>>
>> The ibm_pa_features array and the logic in scan_features() knows to
>> flip the
>> cpu_user_features bits, it
Several properties in the DRC device tree format are replaced by
more compact representations to allow, for example, for the encoding
of vast amounts of memory, and or reduced duplication of information
in related data structures.
"ibm,drc-info": This property, when present, replaces the followin
On 04/05/2016 12:02 PM, Naveen N. Rao wrote:
Some of these tests proved useful with the powerpc eBPF JIT port due to
sign-extended 16-bit immediate loads. Though some of these aspects get
covered in other tests, it is better to have explicit tests so as to
quickly tag the precise problem.
Cc: Al
On 04/05/2016 12:02 PM, Naveen N. Rao wrote:
BPF_ALU32 and BPF_ALU64 tests for adding two 32-bit values that results in
32-bit overflow.
Cc: Alexei Starovoitov
Cc: Daniel Borkmann
Cc: "David S. Miller"
Cc: Ananth N Mavinakayanahalli
Cc: Michael Ellerman
Cc: Paul Mackerras
Signed-off-by: Na
On 04/05/2016 12:02 PM, Naveen N. Rao wrote:
Unsigned Jump-if-Greater-Than.
Cc: Alexei Starovoitov
Cc: Daniel Borkmann
Cc: "David S. Miller"
Cc: Ananth N Mavinakayanahalli
Cc: Michael Ellerman
Cc: Paul Mackerras
Signed-off-by: Naveen N. Rao
Acked-by: Daniel Borkmann
___
On 04/05/2016 12:02 PM, Naveen N. Rao wrote:
JMP_JSET tests incorrectly used BPF_JNE. Fix the same.
Cc: Alexei Starovoitov
Cc: Daniel Borkmann
Cc: "David S. Miller"
Cc: Ananth N Mavinakayanahalli
Cc: Michael Ellerman
Cc: Paul Mackerras
Signed-off-by: Naveen N. Rao
Acked-by: Daniel Borkm
From f7b73c6b4508fe9b141a43d92be2f9dd7d3c4a58 Mon Sep 17 00:00:00 2001
From: Sukadev Bhattiprolu
Date: Thu, 24 Mar 2016 02:07:57 -0400
Subject: [PATCH 1/1] powerpc/mm: Add memory barrier in __hugepte_alloc()
__hugepte_alloc() uses kmem_cache_zalloc() to allocate a zeroed PTE
and proceeds to use t
On 2016/04/05 09:28AM, Alexei Starovoitov wrote:
> On 4/5/16 3:02 AM, Naveen N. Rao wrote:
> >Some of these tests proved useful with the powerpc eBPF JIT port due to
> >sign-extended 16-bit immediate loads. Though some of these aspects get
> >covered in other tests, it is better to have explicit te
On 2016/04/05 09:20AM, Alexei Starovoitov wrote:
> On 4/5/16 3:02 AM, Naveen N. Rao wrote:
> >Unsigned Jump-if-Greater-Than.
> >
> >Cc: Alexei Starovoitov
> >Cc: Daniel Borkmann
> >Cc: "David S. Miller"
> >Cc: Ananth N Mavinakayanahalli
> >Cc: Michael Ellerman
> >Cc: Paul Mackerras
> >Signed-
On 4/5/16 3:02 AM, Naveen N. Rao wrote:
Some of these tests proved useful with the powerpc eBPF JIT port due to
sign-extended 16-bit immediate loads. Though some of these aspects get
covered in other tests, it is better to have explicit tests so as to
quickly tag the precise problem.
Cc: Alexei
On 4/5/16 3:02 AM, Naveen N. Rao wrote:
BPF_ALU32 and BPF_ALU64 tests for adding two 32-bit values that results in
32-bit overflow.
Cc: Alexei Starovoitov
Cc: Daniel Borkmann
Cc: "David S. Miller"
Cc: Ananth N Mavinakayanahalli
Cc: Michael Ellerman
Cc: Paul Mackerras
Signed-off-by: Naveen
On 4/5/16 3:02 AM, Naveen N. Rao wrote:
Unsigned Jump-if-Greater-Than.
Cc: Alexei Starovoitov
Cc: Daniel Borkmann
Cc: "David S. Miller"
Cc: Ananth N Mavinakayanahalli
Cc: Michael Ellerman
Cc: Paul Mackerras
Signed-off-by: Naveen N. Rao
I think some of the tests already cover it, but ext
On 4/5/16 3:02 AM, Naveen N. Rao wrote:
JMP_JSET tests incorrectly used BPF_JNE. Fix the same.
Cc: Alexei Starovoitov
Cc: Daniel Borkmann
Cc: "David S. Miller"
Cc: Ananth N Mavinakayanahalli
Cc: Michael Ellerman
Cc: Paul Mackerras
Signed-off-by: Naveen N. Rao
Good catch.
Fixes: cffc642d
This patch enables mmapping MSI-X tables if
hardware supports interrupt remapping which
can ensure that a given pci device can only
shoot the MSIs assigned for it.
Signed-off-by: Yongji Xie
---
drivers/vfio/pci/vfio_pci.c |9 +++--
drivers/vfio/pci/vfio_pci_private.h |1 +
dr
I'm trying to find a proper way to indicate
the capability of interrupt remapping on PPC64
because we need this to determine whether it is
safe to mmap MSI-X table in VFIO driver.
There is a existing flag for this in the IOMMU
space:
enum iommu_cap {
IOMMU_CAP_CACHE_COHERENCY,
--->IOM
Current vfio-pci implementation disallows to mmap
sub-page(size < PAGE_SIZE) MMIO BARs because
these BARs' mmio page may be shared with other
BARs.
But we should allow to mmap these sub-page MMIO
BARs if we can make sure these BARs' mmio page
will not be shared with other BARs.
To acheive that, w
When vfio passthrough a PCI device of which MMIO
BARs are smaller than PAGE_SIZE, guest will not
handle the mmio accesses to the BARs which leads
to mmio emulations in host.
This is because vfio will not allow to passthrough
one BAR's mmio page which may be shared with other
BARs. Otherwise, there
When using resource_alignment kernel parameter,
the current implement reassigns the alignment by
changing resources' size which can potentially
break some drivers. For example, the driver uses
the size to locate some register whose length is
related to the size.
This adds a new option "noresize" f
Now we use the IORESOURCE_STARTALIGN to identify
bridge resources in __assign_resources_sorted().
That's quite fragile. We can't make sure that
the PCI devices' resources will not use
IORESOURCE_STARTALIGN any more.
In this patch, we try to use a more robust way
to identify bridge resources.
Sign
The resource_alignment will releases memory
resources allocated by firmware so that kernel
can reassign new resources later on. But this
will cause the problem that no resources can be
allocated by kernel if PCI_PROBE_ONLY was set,
e.g. on pSeries platform because PCI_PROBE_ONLY
force kernel to use
Current vfio-pci implementation disallows to mmap
sub-page(size < PAGE_SIZE) MMIO BARs and MSI-X table. This is because
sub-page BARs' mmio page may be shared with other BARs and MSI-X table
should not be accessed directly from the guest for security reasons.
But it will easily cause some performa
On 27/03/16 19:23, Aneesh Kumar K.V wrote:
> PowerISA 3.0 introduce two pte bits with the below meaning w.r.t Radix
> 00 -> Normal Memory
> 01 -> Strong Access Order
> 10 -> Non idempotent I/O (Cache inhibited and guarded)
> 11 -> Tolerant I/O (Cache inhibited)
>
> We drop the existing WIMG bit
Christian Lamparter wrote:
>
> The crash is caused by a bad read in ppc4xx_rng_enable [0]. From what I
> can tell, the driver is mapping the crypto control registers. The
> problem is that they are claimed by the main crypto driver: crypto4xx [1].
>
> I'm not sure what to do in this case. In my o
On 27/03/16 19:23, Aneesh Kumar K.V wrote:
> Use helper instead of opencoding with constants. Later patch will
> drop the WIMG bits and use PowerISA 3.0 defines
>
> Signed-off-by: Aneesh Kumar K.V
> ---
> arch/powerpc/kernel/btext.c | 2 +-
> arch/powerpc/kernel/isa-bridge.c | 4 ++--
> ar
On 1 April 2016 at 05:07, Yangbo Lu wrote:
> This patchset is used to fix a host version register bug in the
> T4240-R1.0-R2.0
> eSDHC controller. To get the SoC version and revision, it's needed to add the
> GUTS driver to access the global utilities registers.
>
> So, the first three patches ar
On Fri, Apr 01, 2016 at 11:07:30AM +0800, Yangbo Lu wrote:
> Move mpc85xx.h to include/linux/fsl and rename it to svr.h as
> a common header file. It has been used for mpc85xx and it will
> be used for ARM-based SoC as well.
>
> Signed-off-by: Yangbo Lu
> Acked-by: Wolfram Sang
Acked-by: Joerg
Some of these tests proved useful with the powerpc eBPF JIT port due to
sign-extended 16-bit immediate loads. Though some of these aspects get
covered in other tests, it is better to have explicit tests so as to
quickly tag the precise problem.
Cc: Alexei Starovoitov
Cc: Daniel Borkmann
Cc: "Dav
Unsigned Jump-if-Greater-Than.
Cc: Alexei Starovoitov
Cc: Daniel Borkmann
Cc: "David S. Miller"
Cc: Ananth N Mavinakayanahalli
Cc: Michael Ellerman
Cc: Paul Mackerras
Signed-off-by: Naveen N. Rao
---
lib/test_bpf.c | 29 +
1 file changed, 29 insertions(+)
diff
BPF_ALU32 and BPF_ALU64 tests for adding two 32-bit values that results in
32-bit overflow.
Cc: Alexei Starovoitov
Cc: Daniel Borkmann
Cc: "David S. Miller"
Cc: Ananth N Mavinakayanahalli
Cc: Michael Ellerman
Cc: Paul Mackerras
Signed-off-by: Naveen N. Rao
---
lib/test_bpf.c | 64 +
JMP_JSET tests incorrectly used BPF_JNE. Fix the same.
Cc: Alexei Starovoitov
Cc: Daniel Borkmann
Cc: "David S. Miller"
Cc: Ananth N Mavinakayanahalli
Cc: Michael Ellerman
Cc: Paul Mackerras
Signed-off-by: Naveen N. Rao
---
lib/test_bpf.c | 8
1 file changed, 4 insertions(+), 4 de
On Tue, 2016-04-05 at 19:35 +1000, Michael Ellerman wrote:
> Shouldn't we be clearing the user feature there too?
>
> The ibm_pa_features array and the logic in scan_features() knows to
> flip the
> cpu_user_features bits, it was just never updated to handle
> cpu_user_features2.
>
> So it seems
- decreasing the cc list significantly
On 1 April 2016 at 05:07, Yangbo Lu wrote:
> Move mpc85xx.h to include/linux/fsl and rename it to svr.h as
> a common header file. It has been used for mpc85xx and it will
> be used for ARM-based SoC as well.
>
> Signed-off-by: Yangbo Lu
> Acked-by: Wolfram
On Mon, 2016-04-04 at 11:11:12 UTC, Paul Mackerras via Linuxppc-dev wrote:
> In check_cpu_pa_features() we check a number of bits in the
Shouldn't we be clearing the user feature there too?
The ibm_pa_features array and the logic in scan_features() knows to flip the
cpu_user_features bits, it was
On 27/03/16 19:23, Aneesh Kumar K.V wrote:
> PS3 had used PPP bit hack to implement a read only mapping in the
> kernel area. Since we are bolt mapping the ioremap area, it used
> the pte flags _PAGE_PRESENT | _PAGE_USER to get a PPP value of 0x3
> there by resulting in a read only mapping. This
On 04/05/2016 02:09 PM, David Gibson wrote:
On Tue, Apr 05, 2016 at 12:12:01PM +1000, Paul Mackerras wrote:
On Mon, Apr 04, 2016 at 09:09:28PM +1000, Anton Blanchard wrote:
We don't support transactional memory in PR KVM, so don't tell
the OS that we do.
This assumes PR KVM won't ever support
On 04/04/2016 09:09 PM, Michael Neuling wrote:
On Mon, 2016-04-04 at 17:00 +1000, Alexey Kardashevskiy wrote:
On 04/04/2016 04:44 PM, Anton Blanchard wrote:
Hi,
I can't get an Ubuntu Wily guest to boot on an Ubuntu Wily host in PR KVM
mode. The kernel in both cases is 4.2. To reproduce:
wget
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