Re: [PATCH 2/5] iommu: Set PCI_BUS_FLAGS_MSI_REMAP if IOMMU have capability of IRQ remapping

On 2016/5/25 5:11, Bjorn Helgaas wrote: On Wed, Apr 27, 2016 at 08:43:27PM +0800, Yongji Xie wrote: The capability of IRQ remapping is abstracted on IOMMU side on some archs. There is a existing flag IOMMU_CAP_INTR_REMAP for this. To have a universal flag to test this capability for different

Re: [PATCH 3/5] PCI: Set PCI_BUS_FLAGS_MSI_REMAP if MSI controller supports IRQ remapping

On 2016/5/25 5:04, Bjorn Helgaas wrote: On Wed, Apr 27, 2016 at 08:43:28PM +0800, Yongji Xie wrote: On ARM HW the capability of IRQ remapping is abstracted on MSI controller side. MSI_FLAG_IRQ_REMAPPING is used to advertise this [1]. To have a universal flag to test this capability for

Re: [PATCH 1/5] PCI: Add a new PCI_BUS_FLAGS_MSI_REMAP flag

On 2016/5/25 4:55, Bjorn Helgaas wrote: On Wed, Apr 27, 2016 at 08:43:26PM +0800, Yongji Xie wrote: We introduce a new pci_bus_flags, PCI_BUS_FLAGS_MSI_REMAP which indicates all devices on the bus are protected by the hardware which supports IRQ remapping(intel naming). This changelog is

Re: [v4] powerpc/pci: Assign fixed PHB number based on device-tree properties

Hi Guilherme, Sorry for the very late reply, this got lost in my email filters. On Mon, 2016-03-28 at 09:36 -0300, Guilherme G. Piccoli wrote: > On 03/25/2016 06:33 AM, Michael Ellerman wrote: > > > +static int get_phb_number(struct device_node *dn) > > > +{ > > > + const __be64 *prop64; > > >

Re: [PATCH v4 08/10] powerpc/powernv: Add platform support for stop instruction

Hi Shreyas, On Tue, May 24, 2016 at 06:45:12PM +0530, Shreyas B. Prabhu wrote: > POWER ISA v3 defines a new idle processor core mechanism. In summary, > a) new instruction named stop is added. This instruction replaces > instructions like nap, sleep, rvwinkle. > b) new per thread SPR

Re: [PATCH v3 7/9] powerpc/powernv: Add platform support for stop instruction

On 05/24/2016 02:17 PM, Madhavan Srinivasan wrote: > > > On Monday 23 May 2016 08:48 PM, Shreyas B. Prabhu wrote: >> POWER ISA v3 defines a new idle processor core mechanism. In summary, >> a) new instruction named stop is added. This instruction replaces >> instructions like nap, sleep,

Re: [PATCH] powerpc: inline current_stack_pointer()

On Mon, May 23, 2016 at 07:17:38PM +0200, Gabriel Paubert wrote: > On Mon, May 23, 2016 at 10:46:02AM +0200, Christophe Leroy wrote: > > current_stack_pointeur() is a single instruction function. it > > It is not worth breaking the execution flow with a bl/blr for a > > single instruction > > Are

Re: [PATCH v3 7/9] powerpc/powernv: Add platform support for stop instruction

On 05/24/2016 03:54 PM, Gautham R Shenoy wrote: > Hi Shreyas, > > On Mon, May 23, 2016 at 08:48:40PM +0530, Shreyas B. Prabhu wrote: >> @@ -412,7 +517,8 @@ subcore_state_restored: >> first_thread_in_core: >> >> /* >> - * First thread in the core waking up from fastsleep. It needs to

RE: livepatch: change to a per-task consistency model

On Tue, 24 May 2016, David Laight wrote: > > > Related, please can we have a flag for the sleep and/or process so that > > > an uninterruptible sleep doesn't trigger the 'hung task' detector > > > > TASK_KILLABLE > > Not sure that does what I want. > It appears to allow some 'kill' actions to

[PATCH] powerpc/85xx: Don't report SRAM to L2 cache fallback as error

If the SRAM region parameters are missing the SRAM driver probing exits and the L2 region is configured as L2 cache entirely. This is the expected default behaviour, so it makes no sense to report it as an error. Signed-off-by: Claudiu Manoil ---

Re: [PATCH 2/5] iommu: Set PCI_BUS_FLAGS_MSI_REMAP if IOMMU have capability of IRQ remapping

On Wed, Apr 27, 2016 at 08:43:27PM +0800, Yongji Xie wrote: > The capability of IRQ remapping is abstracted on IOMMU side on > some archs. There is a existing flag IOMMU_CAP_INTR_REMAP for this. > > To have a universal flag to test this capability for different > archs on PCI side, we set

Re: [PATCH 3/5] PCI: Set PCI_BUS_FLAGS_MSI_REMAP if MSI controller supports IRQ remapping

On Wed, Apr 27, 2016 at 08:43:28PM +0800, Yongji Xie wrote: > On ARM HW the capability of IRQ remapping is abstracted on > MSI controller side. MSI_FLAG_IRQ_REMAPPING is used to advertise > this [1]. > > To have a universal flag to test this capability for different > archs on PCI side, we set

Re: [PATCH 1/5] PCI: Add a new PCI_BUS_FLAGS_MSI_REMAP flag

On Wed, Apr 27, 2016 at 08:43:26PM +0800, Yongji Xie wrote: > We introduce a new pci_bus_flags, PCI_BUS_FLAGS_MSI_REMAP > which indicates all devices on the bus are protected by the > hardware which supports IRQ remapping(intel naming). This changelog is ambiguous. It's possible that there is

Re: [PATCH 0215/1529] Fix typo

On Saturday 21 May 2016 05:34 PM, Andrea Gelmini wrote: Signed-off-by: Andrea Gelmini Reviewed-by: Vipin K Parashar --- arch/powerpc/include/asm/opal-api.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git

Re: [PATCH] powerpc/85xx: Don't report SRAM to L2 cache fallback as error

On 05/24/2016 10:07 AM, Claudiu Manoil wrote: > If the SRAM region parameters are missing the SRAM driver > probing exits and the L2 region is configured as L2 cache > entirely. This is the expected default behaviour, so it > makes no sense to report it as an error. > > Signed-off-by: Claudiu

Re: PAGE_GUARDED

Christian Zigotzky writes: > Ben, > > I tried: > > /* Workaround for lack of device tree */ > if (primary) { > __ioremap_at(range.cpu_addr, (void > *)ISA_IO_BASE, > range.size,

RE: livepatch: change to a per-task consistency model

From: Jiri Kosina > Sent: 23 May 2016 19:45 > > Related, please can we have a flag for the sleep and/or process so that > > an uninterruptible sleep doesn't trigger the 'hung task' detector > > TASK_KILLABLE Not sure that does what I want. It appears to allow some 'kill' actions to wake the

Re: [v5, 1/2] cxl: Add mechanism for delivering AFU driver specific events

> On May 24, 2016, at 1:59 AM, Vaibhav Jain wrote: > > Hi Philippe, > > Few comments, > > Philippe Bergheaud writes: > >> diff --git a/drivers/misc/cxl/cxl.h b/drivers/misc/cxl/cxl.h >> index 4fe5078..b0027e6 100644 >> ---

PAGE_GUARDED

Ben, I tried: /* Workaround for lack of device tree */ if (primary) { __ioremap_at(range.cpu_addr, (void *)ISA_IO_BASE, range.size, pgprot_noncached(PAGE_KERNEL)); hose->io_base_virt =

[PATCH v4 06/10] powerpc/powernv: abstraction for saving SPRs before entering deep idle states

Create a function for saving SPRs before entering deep idle states. This function can be reused for POWER9 deep idle states. Reviewed-by: Gautham R. Shenoy Signed-off-by: Shreyas B. Prabhu --- - No changes in v4 Changes in v3: =

[PATCH v4 10/10] powerpc/powernv: Use deepest stop state when cpu is offlined

If hardware supports stop state, use the deepest stop state when the cpu is offlined. Reviewed-by: Gautham R. Shenoy Signed-off-by: Shreyas B. Prabhu --- - No changes since v1 arch/powerpc/platforms/powernv/idle.c| 15 +--

[PATCH v4 09/10] cpuidle/powernv: Add support for POWER ISA v3 idle states

POWER ISA v3 defines a new idle processor core mechanism. In summary, a) new instruction named stop is added. b) new per thread SPR named PSSCR is added which controls the behavior of stop instruction. Supported idle states and value to be written to PSSCR register to enter any idle

[PATCH v4 08/10] powerpc/powernv: Add platform support for stop instruction

POWER ISA v3 defines a new idle processor core mechanism. In summary, a) new instruction named stop is added. This instruction replaces instructions like nap, sleep, rvwinkle. b) new per thread SPR named Processor Stop Status and Control Register (PSSCR) is added which controls

[PATCH v4 04/10] powerpc/powernv: Rename reusable idle functions to hardware agnostic names

Functions like power7_wakeup_loss, power7_wakeup_noloss, power7_wakeup_tb_loss are used by POWER7 and POWER8 hardware. They can also be used by POWER9. Hence rename these functions hardware agnostic names. Suggested-by: Gautham R. Shenoy Reviewed-by: Gautham R. Shenoy

[PATCH v4 07/10] powerpc/powernv: set power_save func after the idle states are initialized

pnv_init_idle_states discovers supported idle states from the device tree and does the required initialization. Set power_save function pointer only after this initialization is done Reviewed-by: Gautham R. Shenoy Signed-off-by: Shreyas B. Prabhu

[PATCH v4 05/10] powerpc/powernv: Make pnv_powersave_common more generic

pnv_powersave_common does common steps needed before entering idle state and eventually changes MSR to MSR_IDLE and does rfid to pnv_enter_arch207_idle_mode. Move the updation of HSTATE_HWTHREAD_STATE to pnv_powersave_common from pnv_enter_arch207_idle_mode and make it more generic by passing the

[PATCH v4 03/10] powerpc/powernv: Rename idle_power7.S to idle_power_common.S

idle_power7.S handles idle entry/exit for POWER7, POWER8 and in next patch for POWER9. Rename the file to a non-hardware specific name. Reviewed-by: Gautham R. Shenoy Signed-off-by: Shreyas B. Prabhu --- - No changes in v4 Changes in v3:

[PATCH v4 01/10] powerpc/powernv: Use PNV_THREAD_WINKLE macro while requesting for winkle

Signed-off-by: Shreyas B. Prabhu --- Changes in v4 = - New in v4 arch/powerpc/kernel/idle_power7.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/powerpc/kernel/idle_power7.S b/arch/powerpc/kernel/idle_power7.S index

[PATCH v4 00/10] powerpc/powernv/cpuidle: Add support for POWER ISA v3 idle states

POWER ISA v3 defines a new idle processor core mechanism. In summary, a) new instruction named stop is added. This instruction replaces instructions like nap, sleep, rvwinkle. b) new per thread SPR named PSSCR is added which controls the behavior of stop instruction.

Re: [PATCH] gpio: dt-bindings: add ibm,ppc4xx-gpio binding

On Mon, May 16, 2016 at 6:56 PM, Rob Herring wrote: > On Mon, May 16, 2016 at 10:27:46AM -0500, Rob Herring wrote: >> On Thu, May 12, 2016 at 12:07:48AM +0200, Christian Lamparter wrote: >> > This patch adds binding information for IBM/AMCC/APM GPIO >> > Controllers of the

Re: [PATCH] cxl: Update process element after allocating interrupts

Le 23/05/2016 18:14, Ian Munsie a écrit : From: Ian Munsie In the kernel API, it is possible to attempt to allocate AFU interrupts after already starting a context. Since the process element structure used by the hardware is only filled out at the time the context is

Re: PAGE_GUARDED

On Tue, 2016-05-24 at 12:48 +0200, Christian Zigotzky wrote: > Ben, > > Thanks for the hint. I'm sorry I don't know how pgprot_noncached() > works. > > I tried: > > 1) range.size, pgprot_noncached() > > 2) range.size, pgprot_val(pgprot_noncached(__pgprot(0; Hrm... The above is what is

Re: [RFC PATCH v2 1/3] arch/powerpc : Add detour buffer support for optprobes

On 2016/05/19 08:40PM, Anju T wrote: > Detour buffer contains instructions to create an in memory pt_regs. > After the execution of prehandler a call is made for instruction emulation. > The NIP is decided after the probed instruction is executed. Hence a branch > instruction is created to the NIP

PAGE_GUARDED

Ben, Thanks for the hint. I'm sorry I don't know how pgprot_noncached() works. I tried: 1) range.size, pgprot_noncached() 2) range.size, pgprot_val(pgprot_noncached(__pgprot(0; 3) range.size, pgprot_val(pgprot_noncached_wc(__pgprot(0; Unfortunately without any success. I'd like to

Re: [PATCH v3 8/9] cpuidle/powernv: Add support for POWER ISA v3 idle states

On Mon, May 23, 2016 at 08:48:41PM +0530, Shreyas B. Prabhu wrote: > POWER ISA v3 defines a new idle processor core mechanism. In summary, > a) new instruction named stop is added. > b) new per thread SPR named PSSCR is added which controls the behavior > of stop instruction. > >

Re: [PATCH v3 7/9] powerpc/powernv: Add platform support for stop instruction

Hi Shreyas, On Mon, May 23, 2016 at 08:48:40PM +0530, Shreyas B. Prabhu wrote: > @@ -412,7 +517,8 @@ subcore_state_restored: > first_thread_in_core: > > /* > - * First thread in the core waking up from fastsleep. It needs to > + * First thread in the core waking up from any

Re: [RFC PATCH v2 1/3] arch/powerpc : Add detour buffer support for optprobes

On Thursday 19 May 2016 08:40 PM, Anju T wrote: > Detour buffer contains instructions to create an in memory pt_regs. > After the execution of prehandler a call is made for instruction emulation. > The NIP is decided after the probed instruction is executed. Hence a branch > instruction is

Re: [PATCH v3 7/9] powerpc/powernv: Add platform support for stop instruction

On Monday 23 May 2016 08:48 PM, Shreyas B. Prabhu wrote: > POWER ISA v3 defines a new idle processor core mechanism. In summary, > a) new instruction named stop is added. This instruction replaces > instructions like nap, sleep, rvwinkle. > b) new per thread SPR named PSSCR is added

Re: [PATCH v3 5/9] powerpc/powernv: abstraction for saving SPRs before entering deep idle states

On Mon, May 23, 2016 at 08:48:38PM +0530, Shreyas B. Prabhu wrote: > Create a function for saving SPRs before entering deep idle states. > This function can be reused for POWER9 deep idle states. > > Signed-off-by: Shreyas B. Prabhu Reviewed-by: Gautham R. Shenoy

Re: [PATCH v3 4/9] powerpc/powernv: Make power7_powersave_common more generic

Hi Shreyas, On Mon, May 23, 2016 at 08:48:37PM +0530, Shreyas B. Prabhu wrote: > power7_powersave_common does common steps needed before entering idle > state and eventually changes MSR to MSR_IDLE and does rfid to > power7_enter_nap_mode. > > Move the updation of HSTATE_HWTHREAD_STATE to

Re: [PATCH v3 3/9] powerpc/powernv: Rename reusable idle functions to hardware agnostic names

On Mon, May 23, 2016 at 08:48:36PM +0530, Shreyas B. Prabhu wrote: > Functions like power7_wakeup_loss, power7_wakeup_noloss, > power7_wakeup_tb_loss are used by POWER7 and POWER8 hardware. They can > also be used by POWER9. Hence rename these functions hardware agnostic > names. > >

Re: [PATCH v3 2/9] powerpc/powernv: Rename idle_power7.S to idle_power_common.S

On Mon, May 23, 2016 at 08:48:35PM +0530, Shreyas B. Prabhu wrote: > idle_power7.S handles idle entry/exit for POWER7, POWER8 and in next > patch for POWER9. Rename the file to a non-hardware specific > name. > > Signed-off-by: Shreyas B. Prabhu Reviewed-by: Gautham

Re: [PATCH] powerpc32: use stmw/lmw for non volatile registers save/restore

On Mon, May 23, 2016 at 10:46:36AM +0200, Christophe Leroy wrote: > lmw/stmw have a 1 cycle (2 cycles for lmw on some ppc) in addition > and implies serialising, however it reduces the amount of instructions > hence the amount of instruction fetch compared to the equivalent > operation with

Re: [v5, 1/2] cxl: Add mechanism for delivering AFU driver specific events

Hi Philippe, Few comments, Philippe Bergheaud writes: > diff --git a/drivers/misc/cxl/cxl.h b/drivers/misc/cxl/cxl.h > index 4fe5078..b0027e6 100644 > --- a/drivers/misc/cxl/cxl.h > +++ b/drivers/misc/cxl/cxl.h > @@ -24,6 +24,7 @@ > #include > #include > >

Re: [PATCH] powerpc: inline current_stack_pointer()

On Mon, May 23, 2016 at 10:46:02AM +0200, Christophe Leroy wrote: > current_stack_pointeur() is a single instruction function. it > It is not worth breaking the execution flow with a bl/blr for a > single instruction Are you sure that the result is always the same? Calling an external function

Re: [PATCH] powerpc: inline current_stack_pointer()

On Tue, May 24, 2016 at 07:39:59AM +0200, Christophe Leroy wrote: > >>+static inline unsigned long current_stack_pointer(void) > >>+{ > >>+ register unsigned long *ptr asm("r1"); > >>+ > >>+ return *ptr; > >>+} > >Register asm is only guaranteed to work as input to inline asm. NAK. > > > Does

Re: [RFC PATCH v2 2/3] arch/powerpc : optprobes for powerpc core

Hi, On Friday 20 May 2016 06:07 PM, Masami Hiramatsu wrote: Hi Anju, Please see my comments below, On Thu, 19 May 2016 20:40:39 +0530 Anju T wrote: ppc_get_optinsn_slot() and ppc_free_optinsn_slot() are geared towards the allocation and freeing of memory from the