Re: powerpc/nvram: Fix an incorrect partition merge

[Stewart Smith]

xinhui  writes:
>> Has it always been broken?
>>
>
> no. after nvram partition corruption hit, all nvram partitions will be
> erased and re-alloc after the second machine reboot.
> I don't know who does it but i guess it is the firmware. :)

It is. PAPR says we format NVRAM when it's corrupted. This is also true
for NVRAM for PowerNV (not just pseries guest).

-- 
Stewart Smith
OPAL Architect, IBM.

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Re: [PATCH V3 8/9] cpufreq: Keep policy->freq_table sorted in ascending order

[Viresh Kumar]

On 06-06-16, 23:56, Rafael J. Wysocki wrote:
> Since you are adding new code, you can write it so it doesn't do
> unnecessary checks from the start.

Hmm, I will do all that in this series only now.

> While at it, the "if ((freq < policy->min) || (freq > policy->max))"
> checks in cpufreq_find_index_l() and cpufreq_find_index_h() don't look
> good to me, because they very well may cause those function to return
> -EINVAL even when there's a valid table and that may cause
> acpi_cpufreq_fast_switch() to do bad things.

Hmm. So, the checks are for sure required here, otherwise we may end up
returning a frequency which we aren't allowed to. Also note that 'freq' here
isn't the target-freq, but the entry in the freq-table.

This routine should be returning a valid freq within the ranges specified by
policy->min/max.

Also note that these routines shall *never* return -EINVAL, otherwise it is
mostly a bug we are hitting.

We have enough checks in place to make sure that there is at least one valid
entry in the freq-table which is >= policy->min and <= policy->max.

I will take care of rest of the comments though. Thanks.

-- 
viresh
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[PATCH V2 1/7] dt-bindings: Update QorIQ TMU thermal bindings

[Jia Hongtao]

For different types of SoC the sensor id and endianness may vary.
"#thermal-sensor-cells" is used to provide sensor id information.
"little-endian" property is to tell the endianness of TMU.

Signed-off-by: Jia Hongtao 
---
Changes for V2:
* Remove formatting chnages.

 Documentation/devicetree/bindings/thermal/qoriq-thermal.txt | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/Documentation/devicetree/bindings/thermal/qoriq-thermal.txt 
b/Documentation/devicetree/bindings/thermal/qoriq-thermal.txt
index 66223d5..20ca4ef 100644
--- a/Documentation/devicetree/bindings/thermal/qoriq-thermal.txt
+++ b/Documentation/devicetree/bindings/thermal/qoriq-thermal.txt
@@ -17,6 +17,12 @@ Required properties:
calibration data, as specified by the SoC reference manual.
The first cell of each pair is the value to be written to TTCFGR,
and the second is the value to be written to TSCFGR.
+- #thermal-sensor-cells : Must be 1. The sensor specifier is the monitoring
+   site ID, and represents the "n" in TRITSRn and TRATSRn.
+
+Optional property:
+- little-endian : If present, the TMU registers are little endian. If absent,
+   the default is big endian.

 Example:

@@ -60,4 +66,5 @@ tmu@f {

   0x0003 0x0012
   0x00030001 0x001d>;
+   #thermal-sensor-cells = <1>;
 };
--
2.1.0.27.g96db324

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Re: powerpc/pseries: Fix PCI config address for DDW

[Michael Ellerman]

On Wed, 2016-25-05 at 23:56:07 UTC, Gavin Shan wrote:
> In commit <8445a87f7092> ("powerpc/iommu: Remove the dependency
> on EEH struct in DDW mechanism"), the PE address was replaced
> with the PCI config address in order to remove dependency on EEH.
> According to PAPR spec, firmware (pHyp or QEMU) should accept
> "xxBBSSxx" format PCI config address, not "BBSS" provided
> by the patch. Note that "BB" is PCI bus number and "SS" is the
> combination of slot and function number.
> 
> This fixes the PCI address passed to DDW RTAS calls.
> 
> Fixes: 8445a87f7092 ("powerpc/iommu: Remove the dependency on EEH struct in 
> DDW mechanism")
> Reported-by: Guilherme G. Piccoli 
> Signed-off-by: Gavin Shan 
> Tested-by: Guilherme G. Piccoli 

Applied to powerpc fixes, thanks.

https://git.kernel.org/powerpc/c/8a934efe94347eee843aeea65b

cheers
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Re: [V2] powerpc/ptrace: Fix out of bounds array access warning

[Michael Ellerman]

On Mon, 2016-25-04 at 16:19:17 UTC, Khem Raj wrote:
> gcc-6 correctly warns about a out of bounds access
> 
> arch/powerpc/kernel/ptrace.c:407:24: warning: index 32 denotes an offset 
> greater than size of 'u64[32][1] {aka long long unsigned int[32][1]}' 
> [-Warray-bounds]
> offsetof(struct thread_fp_state, fpr[32][0]));
> ^
> 
> check the end of array instead of beginning of next element to fix this
> 
> Signed-off-by: Khem Raj 
> Cc: Kees Cook 
> Cc: Michael Ellerman 
> Cc: Segher Boessenkool 
> Tested-by: Aaro Koskinen 
> Acked-by: Olof Johansson 

Applied to powerpc fixes, thanks.

https://git.kernel.org/powerpc/c/1e407ee3b21f981140491d5b8a

cheers
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答复: [PATCH 1/7] dt-bindings: Update QorIQ TMU thermal bindings

[Hongtao Jia]

> -邮件原件-
> 发件人: Rob Herring [mailto:r...@kernel.org]
> 发送时间: Monday, June 06, 2016 9:47 PM
> 收件人: Hongtao Jia 
> 抄送: edubez...@gmail.com; rui.zh...@intel.com; ga...@codeaurora.org;
> Scott Wood ; shawn...@kernel.org;
> devicet...@vger.kernel.org; linux...@vger.kernel.org; linux-
> ker...@vger.kernel.org; linuxppc-dev@lists.ozlabs.org; linux-arm-
> ker...@lists.infradead.org
> 主题: Re: [PATCH 1/7] dt-bindings: Update QorIQ TMU thermal bindings
> 
> On Fri, Jun 03, 2016 at 02:57:33PM +0800, Jia Hongtao wrote:
> > For different types of SoC the sensor id and endianness may vary.
> > "#thermal-sensor-cells" is used to provide sensor id information.
> > "little-endian" property is to tell the endianness of TMU.
> >
> > Signed-off-by: Jia Hongtao 
> > ---
> >  .../devicetree/bindings/thermal/qoriq-thermal.txt | 19 +---
> ---
> >  1 file changed, 13 insertions(+), 6 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/thermal/qoriq-thermal.txt
> b/Documentation/devicetree/bindings/thermal/qoriq-thermal.txt
> > index 66223d5..8eeef80 100644
> > --- a/Documentation/devicetree/bindings/thermal/qoriq-thermal.txt
> > +++ b/Documentation/devicetree/bindings/thermal/qoriq-thermal.txt
> > @@ -1,22 +1,28 @@
> >  * Thermal Monitoring Unit (TMU) on Freescale QorIQ SoCs
> >
> >  Required properties:
> > -- compatible : Must include "fsl,qoriq-tmu". The version of the device is
> > +- compatible: Must include "fsl,qoriq-tmu". The version of the device is
> 
> Please split functional changes from formatting changes. This one seems
> pretty pointless.

I will remove formatting changes in the next version.
Thanks.

> 
> > determined by the TMU IP Block Revision Register (IPBRR0) at
> > offset 0x0BF8.
> > -   Table of correspondences between IPBRR0 values and example  chips:
> > +   Table of correspondences between IPBRR0 values and example chips:
> > Value   Device
> > --  -
> > 0x01900102  T1040
> > -- reg : Address range of TMU registers.
> > -- interrupts : Contains the interrupt for TMU.
> > -- fsl,tmu-range : The values to be programmed into TTRnCR, as specified by
> > +- reg: Address range of TMU registers.
> > +- interrupts: Contains the interrupt for TMU.
> > +- fsl,tmu-range: The values to be programmed into TTRnCR, as specified by
> > the SoC reference manual. The first cell is TTR0CR, the second is
> > TTR1CR, etc.
> > -- fsl,tmu-calibration : A list of cell pairs containing temperature
> > +- fsl,tmu-calibration: A list of cell pairs containing temperature
> > calibration data, as specified by the SoC reference manual.
> > The first cell of each pair is the value to be written to TTCFGR,
> > and the second is the value to be written to TSCFGR.
> > +- #thermal-sensor-cells: Must be 1. The sensor specifier is the monitoring
> > +   site ID, and represents the "n" in TRITSRn and TRATSRn.
> > +
> > +Optional property:
> > +- little-endian: If present, the TMU registers are little endian.  If 
> > absent,
> > +   the default is big endian.
> >
> >  Example:
> >
> > @@ -60,4 +66,5 @@ tmu@f {
> >
> >0x0003 0x0012
> >0x00030001 0x001d>;
> > +   #thermal-sensor-cells = <1>;
> >  };
> > --
> > 2.1.0.27.g96db324
> >
> >
> > ___
> > linux-arm-kernel mailing list
> > linux-arm-ker...@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
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Re: [PATCH v5 1/6] qspinlock: powerpc support qspinlock

[Benjamin Herrenschmidt]

On Mon, 2016-06-06 at 17:59 +0200, Peter Zijlstra wrote:
> On Fri, Jun 03, 2016 at 02:33:47PM +1000, Benjamin Herrenschmidt wrote:
> > 
> >  - For the above, can you show (or describe) where the qspinlock
> >    improves things compared to our current locks.
> So currently PPC has a fairly straight forward test-and-set spinlock
> IIRC. You have this because LPAR/virt muck and lock holder preemption
> issues etc..
> qspinlock is 1) a fair lock (like ticket locks) and 2) provides
> out-of-word spinning, reducing cacheline pressure.

Thanks Peter. I think I understand the theory, but I'd like see it
translate into real numbers.

> Esp. on multi-socket x86 we saw the out-of-word spinning being a big win
> over our ticket locks.
> 
> And fairness, brought to us by the ticket locks a long time ago,
> eliminated starvation issues we had, where a spinner local to the holder
> would 'always' win from a spinner further away. So under heavy enough
> local contention, the spinners on 'remote' CPUs would 'never' get to own
> the lock.

I think our HW has tweaks to avoid that from happening with the simple
locks in the underlying ll/sc implementation. In any case, what I'm
asking is actual tests to verify it works as expected for us.

> pv-qspinlock tries to preserve the fairness while allowing limited lock
> stealing and explicitly managing which vcpus to wake.

Right.
> > 
> > While there's
> >    theory and to some extent practice on x86, it would be nice to
> >    validate the effects on POWER.
> Right; so that will have to be from benchmarks which I cannot help you
> with ;-)

Precisely :-) This is what I was asking for ;-)

Cheers,
Ben.

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Re: [PATCH v2] powerpc: export cpu_to_core_id()

[Guilherme G. Piccoli]

On 06/02/2016 08:45 AM, Mauricio Faria de Oliveira wrote:

Export cpu_to_core_id().  This will be used by the lpfc driver.

This enables topology_core_id() from   (defined
to cpu_to_core_id() in arch/powerpc/include/asm/topology.h) to be
used by (non-builtin) modules.

That is arch-neutral, already used by eg, drivers/base/topology.c,
but it is builtin (obj-y in Makefile) thus didn't need the export.

Since the module uses topology_core_id() and this is defined to
cpu_to_core_id(), it needs the export, otherwise:

 ERROR: "cpu_to_core_id" [drivers/scsi/lpfc/lpfc.ko] undefined!
 make[1]: *** [__modpost] Error 1
 make: *** [modules] Error 2

Tested on next-20160601.

Changelog:
  - v2: include details about the need for this patch with regards
to the architecture-neutral topology API.

Signed-off-by: Mauricio Faria de Oliveira 
---
  arch/powerpc/kernel/smp.c | 1 +
  1 file changed, 1 insertion(+)

diff --git a/arch/powerpc/kernel/smp.c b/arch/powerpc/kernel/smp.c
index 55c924b..67136e7 100644
--- a/arch/powerpc/kernel/smp.c
+++ b/arch/powerpc/kernel/smp.c
@@ -593,6 +593,7 @@ out:
of_node_put(np);
return id;
  }
+EXPORT_SYMBOL_GPL(cpu_to_core_id);

  /* Helper routines for cpu to core mapping */
  int cpu_core_index_of_thread(int cpu)



Hi Maurício, I'm planning to use this in another driver heheh
Thanks for exporting the symbol.

I built a kernel with your patch and it's working fine, so you can add:

"Tested-by: Guilherme G. Piccoli "

Cheers,


Guilherme

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Re: [PATCH V3 8/9] cpufreq: Keep policy->freq_table sorted in ascending order

[Rafael J. Wysocki]

On Mon, Jun 6, 2016 at 6:25 PM, Viresh Kumar  wrote:
> On 6 June 2016 at 18:27, Rafael J. Wysocki  wrote:
>> On Mon, Jun 6, 2016 at 2:24 PM, Viresh Kumar  wrote:
>>> On 6 June 2016 at 17:40, Rafael J. Wysocki  wrote:
 On Monday, June 06, 2016 09:22:31 AM Viresh Kumar wrote:
>>>
> I agree with that, though that requires larger changes across multiple
> sites.

 What changes and where?
>>>
>>> s/larger/some :)
>>>
>>> So we can change all the callers of cpufreq_frequency_table_target(),
>>
>> But why?
>>
>> It just works as a static inline wrapper around cpufreq_find_index_l()
>> for the code in question after this patch, doesn't it?
>>
>> So if the caller knows it will always ask for RELATION_L, why bother
>> with using the wrapper?
>
> Sorry, I got a bit confused. Are you saying that we should do that change
> right in the patch?
>
> Because I am also saying that yes, there is no point calling the wrapper.

OK

> I can update this patch to make direct calls to the relation specific routines
> if you want.

I'm not sure if I like this patch at all in the first place.

>> Also I'm wondering about the cpufreq_for_each_valid_entry() used all
>> over.  Can't the things be arranged so all of the entries are valid?
>
> Yeah, there would be multiple opportunities available to optimize code
> after this series is in. The policy->table after this series is all sorted
> properly and all the entries are valid as well.
>
> But surely that should be done in a separate series

So I'm reading this as "I will add overhead to that code now, but I
can remove it later" which makes me go "What?!" right away.

Moreover, you seem to be saying something like "all of the entries are
valid now, but I'm using cpufreq_for_each_valid_entry() to walk freq
tables anyway, so that I can get rid of it in a future patch" which
makes me go "What?!" again.

Since you are adding new code, you can write it so it doesn't do
unnecessary checks from the start.

While at it, the "if ((freq < policy->min) || (freq > policy->max))"
checks in cpufreq_find_index_l() and cpufreq_find_index_h() don't look
good to me, because they very well may cause those function to return
-EINVAL even when there's a valid table and that may cause
acpi_cpufreq_fast_switch() to do bad things.

Also, if you are going to return an index, why don't you iterate over
indexes and avoid using pointer subtractions to compute the return
value?

With that, cpufreq_find_index_l() would look like

static inline int cpufreq_find_index_l(struct cpufreq_policy *policy,
   unsigned int target_freq)
{
struct cpufreq_frequency_table *table = policy->freq_table;
int i;

for (i = 0; table[i].frequency != CPUFREQ_TABLE_END; i++)
if (table[i].frequency >= target_freq)
return i;

return i > 0 ? --i : 0;
}

and that can go into cpufreq.h IMO (ie. no need for the new header file).
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[PATCH v4] powerpc: Define and use PPC64_ELF_ABI_v2/v1

[Naveen N. Rao]

From: Michael Ellerman 

We're approaching 20 locations where we need to check for ELF ABI v2.
That's fine, except the logic is a bit awkward, because we have to check
that _CALL_ELF is defined and then what its value is.

So check it once in asm/types.h and define PPC64_ELF_ABI_v2 when ELF ABI
v2 is detected.

We also have a few places where what we're really trying to check is
that we are using the 64-bit v1 ABI, ie. function descriptors. So also
add a #define for that, which simplifies several checks.

Signed-off-by: Naveen N. Rao 
Signed-off-by: Michael Ellerman 
---
v4 (Naveen):
 - Added #include  to ftrace.h and linkage.h as they aren't
   currently included there.

v3 (mpe):
 - Added PPC64_ELF_ABI_v1
 - Cleaned up a few more duplicate checks now that CONFIG_PPC64 is implied.

v2 (Naveen):
 - included __powerpc64__ in the check for setting the flag since ABIv2
   is ppc64 specific.
 - renamed flag to PPC64_ELF_ABI_v2 to convey the same.
 - fixed the incorrect change in ftrace.h
 - converted an additional change in ftrace.c

I have tested this with the above changes and it all looks good to me.

Thanks,
Naveen

 arch/powerpc/include/asm/code-patching.h | 10 --
 arch/powerpc/include/asm/ftrace.h|  8 +---
 arch/powerpc/include/asm/kprobes.h   |  8 +++-
 arch/powerpc/include/asm/linkage.h   |  6 +++---
 arch/powerpc/include/asm/ppc_asm.h   |  4 ++--
 arch/powerpc/include/asm/ptrace.h|  2 +-
 arch/powerpc/include/asm/sections.h  |  4 ++--
 arch/powerpc/include/asm/types.h |  8 
 arch/powerpc/kernel/entry_64.S   |  2 +-
 arch/powerpc/kernel/ftrace.c |  4 ++--
 arch/powerpc/kernel/head_64.S|  2 +-
 arch/powerpc/kernel/kprobes.c|  6 ++
 arch/powerpc/kernel/misc_64.S|  2 +-
 arch/powerpc/kernel/module_64.c  |  4 ++--
 arch/powerpc/kvm/book3s_interrupts.S |  2 +-
 arch/powerpc/kvm/book3s_rmhandlers.S |  2 +-
 16 files changed, 39 insertions(+), 35 deletions(-)

diff --git a/arch/powerpc/include/asm/code-patching.h 
b/arch/powerpc/include/asm/code-patching.h
index 994c60a..2015b07 100644
--- a/arch/powerpc/include/asm/code-patching.h
+++ b/arch/powerpc/include/asm/code-patching.h
@@ -49,8 +49,7 @@ void __patch_exception(int exc, unsigned long addr);
 
 static inline unsigned long ppc_function_entry(void *func)
 {
-#if defined(CONFIG_PPC64)
-#if defined(_CALL_ELF) && _CALL_ELF == 2
+#ifdef PPC64_ELF_ABI_v2
u32 *insn = func;
 
/*
@@ -75,14 +74,13 @@ static inline unsigned long ppc_function_entry(void *func)
return (unsigned long)(insn + 2);
else
return (unsigned long)func;
-#else
+#elif defined(PPC64_ELF_ABI_v1)
/*
 * On PPC64 ABIv1 the function pointer actually points to the
 * function's descriptor. The first entry in the descriptor is the
 * address of the function text.
 */
return ((func_descr_t *)func)->entry;
-#endif
 #else
return (unsigned long)func;
 #endif
@@ -90,7 +88,7 @@ static inline unsigned long ppc_function_entry(void *func)
 
 static inline unsigned long ppc_global_function_entry(void *func)
 {
-#if defined(CONFIG_PPC64) && defined(_CALL_ELF) && _CALL_ELF == 2
+#ifdef PPC64_ELF_ABI_v2
/* PPC64 ABIv2 the global entry point is at the address */
return (unsigned long)func;
 #else
@@ -106,7 +104,7 @@ static inline unsigned long ppc_global_function_entry(void 
*func)
  */
 
 /* This must match the definition of STK_GOT in  */
-#if defined(_CALL_ELF) && _CALL_ELF == 2
+#ifdef PPC64_ELF_ABI_v2
 #define R2_STACK_OFFSET 24
 #else
 #define R2_STACK_OFFSET 40
diff --git a/arch/powerpc/include/asm/ftrace.h 
b/arch/powerpc/include/asm/ftrace.h
index 50ca758..686c5f7 100644
--- a/arch/powerpc/include/asm/ftrace.h
+++ b/arch/powerpc/include/asm/ftrace.h
@@ -1,6 +1,8 @@
 #ifndef _ASM_POWERPC_FTRACE
 #define _ASM_POWERPC_FTRACE
 
+#include 
+
 #ifdef CONFIG_FUNCTION_TRACER
 #define MCOUNT_ADDR((unsigned long)(_mcount))
 #define MCOUNT_INSN_SIZE   4 /* sizeof mcount call */
@@ -65,8 +67,8 @@ struct dyn_arch_ftrace {
 #endif
 #endif
 
-#if defined(CONFIG_FTRACE_SYSCALLS) && defined(CONFIG_PPC64) && 
!defined(__ASSEMBLY__)
-#if !defined(_CALL_ELF) || _CALL_ELF != 2
+#if defined(CONFIG_FTRACE_SYSCALLS) && !defined(__ASSEMBLY__)
+#ifdef PPC64_ELF_ABI_v1
 #define ARCH_HAS_SYSCALL_MATCH_SYM_NAME
 static inline bool arch_syscall_match_sym_name(const char *sym, const char 
*name)
 {
@@ -79,6 +81,6 @@ static inline bool arch_syscall_match_sym_name(const char 
*sym, const char *name
return !strcmp(sym + 4, name + 3);
 }
 #endif
-#endif /* CONFIG_FTRACE_SYSCALLS && CONFIG_PPC64 && !__ASSEMBLY__ */
+#endif /* CONFIG_FTRACE_SYSCALLS && !__ASSEMBLY__ */
 
 #endif /* _ASM_POWERPC_FTRACE */
diff --git a/arch/powerpc/include/asm/kprobes.h 

Re: [PATCH V3 8/9] cpufreq: Keep policy->freq_table sorted in ascending order

[Viresh Kumar]

On 6 June 2016 at 18:27, Rafael J. Wysocki  wrote:
> On Mon, Jun 6, 2016 at 2:24 PM, Viresh Kumar  wrote:
>> On 6 June 2016 at 17:40, Rafael J. Wysocki  wrote:
>>> On Monday, June 06, 2016 09:22:31 AM Viresh Kumar wrote:
>>
 I agree with that, though that requires larger changes across multiple
 sites.
>>>
>>> What changes and where?
>>
>> s/larger/some :)
>>
>> So we can change all the callers of cpufreq_frequency_table_target(),
>
> But why?
>
> It just works as a static inline wrapper around cpufreq_find_index_l()
> for the code in question after this patch, doesn't it?
>
> So if the caller knows it will always ask for RELATION_L, why bother
> with using the wrapper?

Sorry, I got a bit confused. Are you saying that we should do that change
right in the patch?

Because I am also saying that yes, there is no point calling the wrapper.

I can update this patch to make direct calls to the relation specific routines
if you want.

> Also I'm wondering about the cpufreq_for_each_valid_entry() used all
> over.  Can't the things be arranged so all of the entries are valid?

Yeah, there would be multiple opportunities available to optimize code
after this series is in. The policy->table after this series is all sorted
properly and all the entries are valid as well.

But surely that should be done in a separate series
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Re: [PATCH v5 1/6] qspinlock: powerpc support qspinlock

[Peter Zijlstra]

On Fri, Jun 03, 2016 at 02:33:47PM +1000, Benjamin Herrenschmidt wrote:
>  - For the above, can you show (or describe) where the qspinlock
>    improves things compared to our current locks.

So currently PPC has a fairly straight forward test-and-set spinlock
IIRC. You have this because LPAR/virt muck and lock holder preemption
issues etc..

qspinlock is 1) a fair lock (like ticket locks) and 2) provides
out-of-word spinning, reducing cacheline pressure.

Esp. on multi-socket x86 we saw the out-of-word spinning being a big win
over our ticket locks.

And fairness, brought to us by the ticket locks a long time ago,
eliminated starvation issues we had, where a spinner local to the holder
would 'always' win from a spinner further away. So under heavy enough
local contention, the spinners on 'remote' CPUs would 'never' get to own
the lock.

pv-qspinlock tries to preserve the fairness while allowing limited lock
stealing and explicitly managing which vcpus to wake.

>   While there's
>    theory and to some extent practice on x86, it would be nice to
>    validate the effects on POWER.

Right; so that will have to be from benchmarks which I cannot help you
with ;-)
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Re: [PATCH v3] powerpc: spinlock: Fix spin_unlock_wait()

[Peter Zijlstra]

On Mon, Jun 06, 2016 at 10:17:25PM +1000, Michael Ellerman wrote:
> On Mon, 2016-06-06 at 13:56 +0200, Peter Zijlstra wrote:
> > On Mon, Jun 06, 2016 at 09:42:20PM +1000, Michael Ellerman wrote:
> > > +static inline void arch_spin_unlock_wait(arch_spinlock_t *lock)
> > > +{
> > > + arch_spinlock_t lock_val;
> > > +
> > > + smp_mb();
> > > +
> > > + /*
> > > +  * Atomically load and store back the lock value (unchanged). This
> > > +  * ensures that our observation of the lock value is ordered with
> > > +  * respect to other lock operations.
> > > +  */
> > > + __asm__ __volatile__(
> > > +"1:  " PPC_LWARX(%0, 0, %2, 0) "\n"
> > > +"stwcx. %0, 0, %2\n"
> > > +"bne- 1b\n"
> > > + : "=" (lock_val), "+m" (*lock)
> > > + : "r" (lock)
> > > + : "cr0", "xer");
> > > +
> > > + if (arch_spin_value_unlocked(lock_val))
> > > + goto out;
> > > +
> > > + while (!arch_spin_value_unlocked(*lock)) {
> > > + HMT_low();
> > > + if (SHARED_PROCESSOR)
> > > + __spin_yield(lock);
> > > + }
> > > + HMT_medium();
> > > +
> > > +out:
> > > + smp_mb();
> > > +}
> > 
> > Why the move to in-line this implementation? It looks like a fairly big
> > function.
> 
> I agree it's not pretty.

> 
> I'm not beholden to v3 though if you hate it.

I don't mind; its just that I am in a similar boat with qspinlock and
chose the other option. So I just figured I'd ask :-)
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Re: [RFC PATCH v2 17/18] livepatch: change to a per-task consistency model

[Josh Poimboeuf]

On Mon, Jun 06, 2016 at 03:54:41PM +0200, Petr Mladek wrote:
> On Thu 2016-04-28 15:44:48, Josh Poimboeuf wrote:
> > Change livepatch to use a basic per-task consistency model.  This is the
> > foundation which will eventually enable us to patch those ~10% of
> > security patches which change function or data semantics.  This is the
> > biggest remaining piece needed to make livepatch more generally useful.
> 
> > diff --git a/kernel/livepatch/transition.c b/kernel/livepatch/transition.c
> > new file mode 100644
> > index 000..92819bb
> > --- /dev/null
> > +++ b/kernel/livepatch/transition.c
> > +/*
> > + * Try to safely switch a task to the target patch state.  If it's 
> > currently
> > + * running, or it's sleeping on a to-be-patched or to-be-unpatched 
> > function, or
> > + * if the stack is unreliable, return false.
> > + */
> > +static bool klp_try_switch_task(struct task_struct *task)
> > +{
> > +   struct rq *rq;
> > +   unsigned long flags;
> 
> This should be of type "struct rq_flags". Otherwise, I get compilation
> warnings:
> 
> kernel/livepatch/transition.c: In function ‘klp_try_switch_task’:
> kernel/livepatch/transition.c:349:2: warning: passing argument 2 of 
> ‘task_rq_lock’ from incompatible pointer type [enabled by default]
>   rq = task_rq_lock(task, );
>   ^
> In file included from kernel/livepatch/transition.c:24:0:
> kernel/livepatch/../sched/sched.h:1468:12: note: expected ‘struct rq_flags *’ 
> but argument is of type ‘long unsigned int *’
>  struct rq *task_rq_lock(struct task_struct *p, struct rq_flags *rf)
> ^
> kernel/livepatch/transition.c:367:2: warning: passing argument 3 of 
> ‘task_rq_unlock’ from incompatible pointer type [enabled by default]
>   task_rq_unlock(rq, task, );
>   ^
> In file included from kernel/livepatch/transition.c:24:0:
> kernel/livepatch/../sched/sched.h:1480:1: note: expected ‘struct rq_flags *’ 
> but argument is of type ‘long unsigned int *’
>  task_rq_unlock(struct rq *rq, struct task_struct *p, struct rq_flags *rf)
> 
> 
> And even runtime warnings from lockdep:
> 
> [  212.847548] WARNING: CPU: 1 PID: 3847 at kernel/locking/lockdep.c:3532 
> lock_release+0x431/0x480
> [  212.847549] releasing a pinned lock
> [  212.847550] Modules linked in: livepatch_sample(E+)
> [  212.847555] CPU: 1 PID: 3847 Comm: modprobe Tainted: GE K 
> 4.7.0-rc1-next-20160602-4-default+ #336
> [  212.847556] Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS 
> Bochs 01/01/2011
> [  212.847558]   880139823aa0 814388dc 
> 880139823af0
> [  212.847562]   880139823ae0 8106fad1 
> 0dcc82b11390
> [  212.847565]  88013fc978d8 810eea1e 8800ba0ed6d0 
> 0003
> [  212.847569] Call Trace:
> [  212.847572]  [] dump_stack+0x85/0xc9
> [  212.847575]  [] __warn+0xd1/0xf0
> [  212.847578]  [] ? klp_try_switch_task.part.3+0x5e/0x2b0
> [  212.847580]  [] warn_slowpath_fmt+0x4f/0x60
> [  212.847582]  [] lock_release+0x431/0x480
> [  212.847585]  [] ? dump_trace+0x118/0x310
> [  212.847588]  [] ? entry_SYSCALL_64_fastpath+0x1f/0xbd
> [  212.847590]  [] _raw_spin_unlock+0x1f/0x30
> [  212.847600]  [] klp_try_switch_task.part.3+0x5e/0x2b0
> [  212.847603]  [] klp_try_complete_transition+0x84/0x190
> [  212.847605]  [] __klp_enable_patch+0xb0/0x130
> [  212.847607]  [] klp_enable_patch+0x55/0x80
> [  212.847610]  [] ? livepatch_cmdline_proc_show+0x30/0x30 
> [livepatch_sample]
> [  212.847613]  [] livepatch_init+0x31/0x70 
> [livepatch_sample]
> [  212.847615]  [] ? livepatch_cmdline_proc_show+0x30/0x30 
> [livepatch_sample]
> [  212.847617]  [] do_one_initcall+0x3d/0x160
> [  212.847629]  [] ? do_init_module+0x27/0x1e4
> [  212.847632]  [] ? rcu_read_lock_sched_held+0x62/0x70
> [  212.847634]  [] ? kmem_cache_alloc_trace+0x282/0x340
> [  212.847636]  [] do_init_module+0x60/0x1e4
> [  212.847638]  [] load_module+0x1482/0x1d40
> [  212.847640]  [] ? __symbol_put+0x40/0x40
> [  212.847643]  [] SYSC_finit_module+0xa9/0xd0
> [  212.847645]  [] SyS_finit_module+0xe/0x10
> [  212.847647]  [] entry_SYSCALL_64_fastpath+0x1f/0xbd
> [  212.847649] ---[ end trace e4e9f09d45443049 ]---

Thanks, I also saw this when rebasing onto a newer linux-next.

> > +   int ret;
> > +   bool success = false;
> > +
> > +   /* check if this task has already switched over */
> > +   if (task->patch_state == klp_target_state)
> > +   return true;
> > +
> > +   /*
> > +* For arches which don't have reliable stack traces, we have to rely
> > +* on other methods (e.g., switching tasks at the syscall barrier).
> > +*/
> > +   if (!IS_ENABLED(CONFIG_RELIABLE_STACKTRACE))
> > +   return false;
> > +
> > +   /*
> > +* Now try to check the stack for any to-be-patched or to-be-unpatched
> > +* functions.  If all goes well, switch the task to the target patch
> > +* state.
> > +*/
> > +   rq = task_rq_lock(task, );
> > +
> > +   if (task_running(rq, task) && 

Re: [RFC PATCH v2 17/18] livepatch: change to a per-task consistency model

[Petr Mladek]

On Thu 2016-04-28 15:44:48, Josh Poimboeuf wrote:
> Change livepatch to use a basic per-task consistency model.  This is the
> foundation which will eventually enable us to patch those ~10% of
> security patches which change function or data semantics.  This is the
> biggest remaining piece needed to make livepatch more generally useful.

> diff --git a/kernel/livepatch/transition.c b/kernel/livepatch/transition.c
> new file mode 100644
> index 000..92819bb
> --- /dev/null
> +++ b/kernel/livepatch/transition.c
> +/*
> + * Try to safely switch a task to the target patch state.  If it's currently
> + * running, or it's sleeping on a to-be-patched or to-be-unpatched function, 
> or
> + * if the stack is unreliable, return false.
> + */
> +static bool klp_try_switch_task(struct task_struct *task)
> +{
> + struct rq *rq;
> + unsigned long flags;

This should be of type "struct rq_flags". Otherwise, I get compilation
warnings:

kernel/livepatch/transition.c: In function ‘klp_try_switch_task’:
kernel/livepatch/transition.c:349:2: warning: passing argument 2 of 
‘task_rq_lock’ from incompatible pointer type [enabled by default]
  rq = task_rq_lock(task, );
  ^
In file included from kernel/livepatch/transition.c:24:0:
kernel/livepatch/../sched/sched.h:1468:12: note: expected ‘struct rq_flags *’ 
but argument is of type ‘long unsigned int *’
 struct rq *task_rq_lock(struct task_struct *p, struct rq_flags *rf)
^
kernel/livepatch/transition.c:367:2: warning: passing argument 3 of 
‘task_rq_unlock’ from incompatible pointer type [enabled by default]
  task_rq_unlock(rq, task, );
  ^
In file included from kernel/livepatch/transition.c:24:0:
kernel/livepatch/../sched/sched.h:1480:1: note: expected ‘struct rq_flags *’ 
but argument is of type ‘long unsigned int *’
 task_rq_unlock(struct rq *rq, struct task_struct *p, struct rq_flags *rf)


And even runtime warnings from lockdep:

[  212.847548] WARNING: CPU: 1 PID: 3847 at kernel/locking/lockdep.c:3532 
lock_release+0x431/0x480
[  212.847549] releasing a pinned lock
[  212.847550] Modules linked in: livepatch_sample(E+)
[  212.847555] CPU: 1 PID: 3847 Comm: modprobe Tainted: GE K 
4.7.0-rc1-next-20160602-4-default+ #336
[  212.847556] Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS 
Bochs 01/01/2011
[  212.847558]   880139823aa0 814388dc 
880139823af0
[  212.847562]   880139823ae0 8106fad1 
0dcc82b11390
[  212.847565]  88013fc978d8 810eea1e 8800ba0ed6d0 
0003
[  212.847569] Call Trace:
[  212.847572]  [] dump_stack+0x85/0xc9
[  212.847575]  [] __warn+0xd1/0xf0
[  212.847578]  [] ? klp_try_switch_task.part.3+0x5e/0x2b0
[  212.847580]  [] warn_slowpath_fmt+0x4f/0x60
[  212.847582]  [] lock_release+0x431/0x480
[  212.847585]  [] ? dump_trace+0x118/0x310
[  212.847588]  [] ? entry_SYSCALL_64_fastpath+0x1f/0xbd
[  212.847590]  [] _raw_spin_unlock+0x1f/0x30
[  212.847600]  [] klp_try_switch_task.part.3+0x5e/0x2b0
[  212.847603]  [] klp_try_complete_transition+0x84/0x190
[  212.847605]  [] __klp_enable_patch+0xb0/0x130
[  212.847607]  [] klp_enable_patch+0x55/0x80
[  212.847610]  [] ? livepatch_cmdline_proc_show+0x30/0x30 
[livepatch_sample]
[  212.847613]  [] livepatch_init+0x31/0x70 [livepatch_sample]
[  212.847615]  [] ? livepatch_cmdline_proc_show+0x30/0x30 
[livepatch_sample]
[  212.847617]  [] do_one_initcall+0x3d/0x160
[  212.847629]  [] ? do_init_module+0x27/0x1e4
[  212.847632]  [] ? rcu_read_lock_sched_held+0x62/0x70
[  212.847634]  [] ? kmem_cache_alloc_trace+0x282/0x340
[  212.847636]  [] do_init_module+0x60/0x1e4
[  212.847638]  [] load_module+0x1482/0x1d40
[  212.847640]  [] ? __symbol_put+0x40/0x40
[  212.847643]  [] SYSC_finit_module+0xa9/0xd0
[  212.847645]  [] SyS_finit_module+0xe/0x10
[  212.847647]  [] entry_SYSCALL_64_fastpath+0x1f/0xbd
[  212.847649] ---[ end trace e4e9f09d45443049 ]---


> + int ret;
> + bool success = false;
> +
> + /* check if this task has already switched over */
> + if (task->patch_state == klp_target_state)
> + return true;
> +
> + /*
> +  * For arches which don't have reliable stack traces, we have to rely
> +  * on other methods (e.g., switching tasks at the syscall barrier).
> +  */
> + if (!IS_ENABLED(CONFIG_RELIABLE_STACKTRACE))
> + return false;
> +
> + /*
> +  * Now try to check the stack for any to-be-patched or to-be-unpatched
> +  * functions.  If all goes well, switch the task to the target patch
> +  * state.
> +  */
> + rq = task_rq_lock(task, );
> +
> + if (task_running(rq, task) && task != current) {
> + pr_debug("%s: pid %d (%s) is running\n", __func__, task->pid,
> +  task->comm);

Also I think about using printk_deferred() inside the rq_lock but
it is not strictly needed. Also we use only pr_debug() here which
is a NOP when not enabled.

Best Regards,
Petr

Re: [PATCH 1/7] dt-bindings: Update QorIQ TMU thermal bindings

[Rob Herring]

On Fri, Jun 03, 2016 at 02:57:33PM +0800, Jia Hongtao wrote:
> For different types of SoC the sensor id and endianness may vary.
> "#thermal-sensor-cells" is used to provide sensor id information.
> "little-endian" property is to tell the endianness of TMU.
> 
> Signed-off-by: Jia Hongtao 
> ---
>  .../devicetree/bindings/thermal/qoriq-thermal.txt | 19 
> +--
>  1 file changed, 13 insertions(+), 6 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/thermal/qoriq-thermal.txt 
> b/Documentation/devicetree/bindings/thermal/qoriq-thermal.txt
> index 66223d5..8eeef80 100644
> --- a/Documentation/devicetree/bindings/thermal/qoriq-thermal.txt
> +++ b/Documentation/devicetree/bindings/thermal/qoriq-thermal.txt
> @@ -1,22 +1,28 @@
>  * Thermal Monitoring Unit (TMU) on Freescale QorIQ SoCs
>  
>  Required properties:
> -- compatible : Must include "fsl,qoriq-tmu". The version of the device is
> +- compatible: Must include "fsl,qoriq-tmu". The version of the device is

Please split functional changes from formatting changes. This one seems 
pretty pointless.

>   determined by the TMU IP Block Revision Register (IPBRR0) at
>   offset 0x0BF8.
> - Table of correspondences between IPBRR0 values and example  chips:
> + Table of correspondences between IPBRR0 values and example chips:
>   Value   Device
>   --  -
>   0x01900102  T1040
> -- reg : Address range of TMU registers.
> -- interrupts : Contains the interrupt for TMU.
> -- fsl,tmu-range : The values to be programmed into TTRnCR, as specified by
> +- reg: Address range of TMU registers.
> +- interrupts: Contains the interrupt for TMU.
> +- fsl,tmu-range: The values to be programmed into TTRnCR, as specified by
>   the SoC reference manual. The first cell is TTR0CR, the second is
>   TTR1CR, etc.
> -- fsl,tmu-calibration : A list of cell pairs containing temperature
> +- fsl,tmu-calibration: A list of cell pairs containing temperature
>   calibration data, as specified by the SoC reference manual.
>   The first cell of each pair is the value to be written to TTCFGR,
>   and the second is the value to be written to TSCFGR.
> +- #thermal-sensor-cells: Must be 1. The sensor specifier is the monitoring
> + site ID, and represents the "n" in TRITSRn and TRATSRn.
> +
> +Optional property:
> +- little-endian: If present, the TMU registers are little endian.  If absent,
> + the default is big endian.
>  
>  Example:
>  
> @@ -60,4 +66,5 @@ tmu@f {
>  
>  0x0003 0x0012
>  0x00030001 0x001d>;
> + #thermal-sensor-cells = <1>;
>  };
> -- 
> 2.1.0.27.g96db324
> 
> 
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[PATCH v2 7/7] crypto: talitos - templates for AEAD using HMAC_SNOOP_NO_AFEU

[Christophe Leroy]

This will allow IPSEC on SEC1

Signed-off-by: Christophe Leroy 
---
 drivers/crypto/talitos.c | 180 +++
 1 file changed, 180 insertions(+)

diff --git a/drivers/crypto/talitos.c b/drivers/crypto/talitos.c
index dfd3a93..0418a2f 100644
--- a/drivers/crypto/talitos.c
+++ b/drivers/crypto/talitos.c
@@ -811,6 +811,11 @@ static void talitos_unregister_rng(struct device *dev)
  * crypto alg
  */
 #define TALITOS_CRA_PRIORITY   3000
+/*
+ * Defines a priority for doing AEAD with descriptors type
+ * HMAC_SNOOP_NO_AFEA (HSNA) instead of type IPSEC_ESP
+ */
+#define TALITOS_CRA_PRIORITY_AEAD_HSNA (TALITOS_CRA_PRIORITY - 1)
 #define TALITOS_MAX_KEY_SIZE   96
 #define TALITOS_MAX_IV_LENGTH  16 /* max of AES_BLOCK_SIZE, 
DES3_EDE_BLOCK_SIZE */
 
@@ -2152,6 +2157,27 @@ static struct talitos_alg_template driver_algs[] = {
 DESC_HDR_MODE1_MDEU_SHA1_HMAC,
},
{   .type = CRYPTO_ALG_TYPE_AEAD,
+   .priority = TALITOS_CRA_PRIORITY_AEAD_HSNA,
+   .alg.aead = {
+   .base = {
+   .cra_name = "authenc(hmac(sha1),cbc(aes))",
+   .cra_driver_name = "authenc-hmac-sha1-"
+  "cbc-aes-talitos",
+   .cra_blocksize = AES_BLOCK_SIZE,
+   .cra_flags = CRYPTO_ALG_ASYNC,
+   },
+   .ivsize = AES_BLOCK_SIZE,
+   .maxauthsize = SHA1_DIGEST_SIZE,
+   },
+   .desc_hdr_template = DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU |
+DESC_HDR_SEL0_AESU |
+DESC_HDR_MODE0_AESU_CBC |
+DESC_HDR_SEL1_MDEUA |
+DESC_HDR_MODE1_MDEU_INIT |
+DESC_HDR_MODE1_MDEU_PAD |
+DESC_HDR_MODE1_MDEU_SHA1_HMAC,
+   },
+   {   .type = CRYPTO_ALG_TYPE_AEAD,
.alg.aead = {
.base = {
.cra_name = "authenc(hmac(sha1),"
@@ -2173,6 +2199,29 @@ static struct talitos_alg_template driver_algs[] = {
 DESC_HDR_MODE1_MDEU_PAD |
 DESC_HDR_MODE1_MDEU_SHA1_HMAC,
},
+   {   .type = CRYPTO_ALG_TYPE_AEAD,
+   .priority = TALITOS_CRA_PRIORITY_AEAD_HSNA,
+   .alg.aead = {
+   .base = {
+   .cra_name = "authenc(hmac(sha1),"
+   "cbc(des3_ede))",
+   .cra_driver_name = "authenc-hmac-sha1-"
+  "cbc-3des-talitos",
+   .cra_blocksize = DES3_EDE_BLOCK_SIZE,
+   .cra_flags = CRYPTO_ALG_ASYNC,
+   },
+   .ivsize = DES3_EDE_BLOCK_SIZE,
+   .maxauthsize = SHA1_DIGEST_SIZE,
+   },
+   .desc_hdr_template = DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU |
+DESC_HDR_SEL0_DEU |
+DESC_HDR_MODE0_DEU_CBC |
+DESC_HDR_MODE0_DEU_3DES |
+DESC_HDR_SEL1_MDEUA |
+DESC_HDR_MODE1_MDEU_INIT |
+DESC_HDR_MODE1_MDEU_PAD |
+DESC_HDR_MODE1_MDEU_SHA1_HMAC,
+   },
{   .type = CRYPTO_ALG_TYPE_AEAD,
.alg.aead = {
.base = {
@@ -2193,6 +2242,27 @@ static struct talitos_alg_template driver_algs[] = {
 DESC_HDR_MODE1_MDEU_PAD |
 DESC_HDR_MODE1_MDEU_SHA224_HMAC,
},
+   {   .type = CRYPTO_ALG_TYPE_AEAD,
+   .priority = TALITOS_CRA_PRIORITY_AEAD_HSNA,
+   .alg.aead = {
+   .base = {
+   .cra_name = "authenc(hmac(sha224),cbc(aes))",
+   .cra_driver_name = "authenc-hmac-sha224-"
+  "cbc-aes-talitos",
+   .cra_blocksize = AES_BLOCK_SIZE,
+   .cra_flags = CRYPTO_ALG_ASYNC,
+   },
+   .ivsize = AES_BLOCK_SIZE,
+   .maxauthsize = SHA224_DIGEST_SIZE,
+   },
+   .desc_hdr_template = DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU |
+DESC_HDR_SEL0_AESU |
+DESC_HDR_MODE0_AESU_CBC |
+

[PATCH v2 2/7] crypto: talitos - move mapping helpers before IPSEC functions

[Christophe Leroy]

In order to be able to use the mapping/unmapping helpers for IPSEC
it needs to be move upper in the file

Signed-off-by: Christophe Leroy 
---
 drivers/crypto/talitos.c | 244 +++
 1 file changed, 122 insertions(+), 122 deletions(-)

diff --git a/drivers/crypto/talitos.c b/drivers/crypto/talitos.c
index a92aa37..beb369e 100644
--- a/drivers/crypto/talitos.c
+++ b/drivers/crypto/talitos.c
@@ -926,6 +926,33 @@ static void talitos_sg_unmap(struct device *dev,
dma_unmap_sg(dev, src, src_nents, DMA_BIDIRECTIONAL);
 }
 
+static void unmap_sg_talitos_ptr(struct device *dev, struct scatterlist *src,
+struct scatterlist *dst, unsigned int len,
+struct talitos_edesc *edesc)
+{
+   struct talitos_private *priv = dev_get_drvdata(dev);
+   bool is_sec1 = has_ftr_sec1(priv);
+
+   if (is_sec1) {
+   if (!edesc->src_nents) {
+   dma_unmap_sg(dev, src, 1,
+dst != src ? DMA_TO_DEVICE
+   : DMA_BIDIRECTIONAL);
+   }
+   if (dst && edesc->dst_nents) {
+   dma_sync_single_for_device(dev,
+  edesc->dma_link_tbl + len,
+  len, DMA_FROM_DEVICE);
+   sg_copy_from_buffer(dst, edesc->dst_nents ? : 1,
+   edesc->buf + len, len);
+   } else if (dst && dst != src) {
+   dma_unmap_sg(dev, dst, 1, DMA_FROM_DEVICE);
+   }
+   } else {
+   talitos_sg_unmap(dev, edesc, src, dst);
+   }
+}
+
 static void ipsec_esp_unmap(struct device *dev,
struct talitos_edesc *edesc,
struct aead_request *areq)
@@ -1083,6 +1110,101 @@ static inline int sg_to_link_tbl(struct scatterlist 
*sg, int sg_count,
 link_tbl_ptr);
 }
 
+int map_sg_in_talitos_ptr(struct device *dev, struct scatterlist *src,
+ unsigned int len, struct talitos_edesc *edesc,
+ enum dma_data_direction dir, struct talitos_ptr *ptr)
+{
+   int sg_count;
+   struct talitos_private *priv = dev_get_drvdata(dev);
+   bool is_sec1 = has_ftr_sec1(priv);
+
+   to_talitos_ptr_len(ptr, len, is_sec1);
+
+   if (is_sec1) {
+   sg_count = edesc->src_nents ? : 1;
+
+   if (sg_count == 1) {
+   dma_map_sg(dev, src, 1, dir);
+   to_talitos_ptr(ptr, sg_dma_address(src), is_sec1);
+   } else {
+   sg_copy_to_buffer(src, sg_count, edesc->buf, len);
+   to_talitos_ptr(ptr, edesc->dma_link_tbl, is_sec1);
+   dma_sync_single_for_device(dev, edesc->dma_link_tbl,
+  len, DMA_TO_DEVICE);
+   }
+   } else {
+   to_talitos_ptr_ext_set(ptr, 0, is_sec1);
+
+   sg_count = dma_map_sg(dev, src, edesc->src_nents ? : 1, dir);
+
+   if (sg_count == 1) {
+   to_talitos_ptr(ptr, sg_dma_address(src), is_sec1);
+   } else {
+   sg_count = sg_to_link_tbl(src, sg_count, len,
+ >link_tbl[0]);
+   if (sg_count > 1) {
+   to_talitos_ptr(ptr, edesc->dma_link_tbl, 0);
+   to_talitos_ptr_ext_or(ptr, DESC_PTR_LNKTBL_JUMP,
+ 0);
+   dma_sync_single_for_device(dev,
+  edesc->dma_link_tbl,
+  edesc->dma_len,
+  DMA_BIDIRECTIONAL);
+   } else {
+   /* Only one segment now, so no link tbl needed*/
+   to_talitos_ptr(ptr, sg_dma_address(src),
+  is_sec1);
+   }
+   }
+   }
+   return sg_count;
+}
+
+void map_sg_out_talitos_ptr(struct device *dev, struct scatterlist *dst,
+   unsigned int len, struct talitos_edesc *edesc,
+   enum dma_data_direction dir,
+   struct talitos_ptr *ptr, int sg_count)
+{
+   struct talitos_private *priv = dev_get_drvdata(dev);
+   bool is_sec1 = has_ftr_sec1(priv);
+
+   if (dir != DMA_NONE)
+   sg_count = dma_map_sg(dev, dst, edesc->dst_nents ? : 1, dir);
+
+   to_talitos_ptr_len(ptr, len, is_sec1);
+
+   if (is_sec1) {
+

[PATCH v2 1/7] crypto: talitos - using helpers for all talitos_ptr operations

[Christophe Leroy]

Use helper for all modifications to talitos_ptr in preparation to
the implementation of AEAD for SEC1

to_talitos_ptr_extent_clear() has been removed in favor of
to_talitos_ptr_ext_set() to set any value and
to_talitos_ptr_ext_or() to or the extent field with a value
name has been shorten to help keeping single lines of 80 chars

Signed-off-by: Christophe Leroy 
---
 drivers/crypto/talitos.c | 59 
 1 file changed, 34 insertions(+), 25 deletions(-)

diff --git a/drivers/crypto/talitos.c b/drivers/crypto/talitos.c
index b7ee8d3..a92aa37 100644
--- a/drivers/crypto/talitos.c
+++ b/drivers/crypto/talitos.c
@@ -91,10 +91,17 @@ static unsigned short from_talitos_ptr_len(struct 
talitos_ptr *ptr,
return be16_to_cpu(ptr->len);
 }
 
-static void to_talitos_ptr_extent_clear(struct talitos_ptr *ptr, bool is_sec1)
+static void to_talitos_ptr_ext_set(struct talitos_ptr *ptr, u8 val,
+  bool is_sec1)
 {
if (!is_sec1)
-   ptr->j_extent = 0;
+   ptr->j_extent = val;
+}
+
+static void to_talitos_ptr_ext_or(struct talitos_ptr *ptr, u8 val, bool 
is_sec1)
+{
+   if (!is_sec1)
+   ptr->j_extent |= val;
 }
 
 /*
@@ -111,7 +118,7 @@ static void map_single_talitos_ptr(struct device *dev,
 
to_talitos_ptr_len(ptr, len, is_sec1);
to_talitos_ptr(ptr, dma_addr, is_sec1);
-   to_talitos_ptr_extent_clear(ptr, is_sec1);
+   to_talitos_ptr_ext_set(ptr, 0, is_sec1);
 }
 
 /*
@@ -1050,8 +1057,8 @@ static int sg_to_link_tbl_offset(struct scatterlist *sg, 
int sg_count,
 
to_talitos_ptr(link_tbl_ptr + count,
   sg_dma_address(sg) + offset, 0);
-   link_tbl_ptr[count].len = cpu_to_be16(len);
-   link_tbl_ptr[count].j_extent = 0;
+   to_talitos_ptr_len(link_tbl_ptr + count, len, 0);
+   to_talitos_ptr_ext_set(link_tbl_ptr + count, 0, 0);
count++;
cryptlen -= len;
offset = 0;
@@ -1062,7 +1069,8 @@ next:
 
/* tag end of link table */
if (count > 0)
-   link_tbl_ptr[count - 1].j_extent = DESC_PTR_LNKTBL_RETURN;
+   to_talitos_ptr_ext_set(link_tbl_ptr + count - 1,
+  DESC_PTR_LNKTBL_RETURN, 0);
 
return count;
 }
@@ -1102,14 +1110,14 @@ static int ipsec_esp(struct talitos_edesc *edesc, 
struct aead_request *areq,
  (areq->src == areq->dst) ? DMA_BIDIRECTIONAL
   : DMA_TO_DEVICE);
/* hmac data */
-   desc->ptr[1].len = cpu_to_be16(areq->assoclen);
+   to_talitos_ptr_len(>ptr[1], areq->assoclen, 0);
if (sg_count > 1 &&
(ret = sg_to_link_tbl_offset(areq->src, sg_count, 0,
 areq->assoclen,
 >link_tbl[tbl_off])) > 1) {
to_talitos_ptr(>ptr[1], edesc->dma_link_tbl + tbl_off *
   sizeof(struct talitos_ptr), 0);
-   desc->ptr[1].j_extent = DESC_PTR_LNKTBL_JUMP;
+   to_talitos_ptr_ext_set(>ptr[1], DESC_PTR_LNKTBL_JUMP, 0);
 
dma_sync_single_for_device(dev, edesc->dma_link_tbl,
   edesc->dma_len, DMA_BIDIRECTIONAL);
@@ -1117,13 +1125,13 @@ static int ipsec_esp(struct talitos_edesc *edesc, 
struct aead_request *areq,
tbl_off += ret;
} else {
to_talitos_ptr(>ptr[1], sg_dma_address(areq->src), 0);
-   desc->ptr[1].j_extent = 0;
+   to_talitos_ptr_ext_set(>ptr[1], 0, 0);
}
 
/* cipher iv */
to_talitos_ptr(>ptr[2], edesc->iv_dma, 0);
-   desc->ptr[2].len = cpu_to_be16(ivsize);
-   desc->ptr[2].j_extent = 0;
+   to_talitos_ptr_len(>ptr[2], ivsize, 0);
+   to_talitos_ptr_ext_set(>ptr[2], 0, 0);
 
/* cipher key */
map_single_talitos_ptr(dev, >ptr[3], ctx->enckeylen,
@@ -1136,8 +1144,8 @@ static int ipsec_esp(struct talitos_edesc *edesc, struct 
aead_request *areq,
 * extent is bytes of HMAC postpended to ciphertext,
 * typically 12 for ipsec
 */
-   desc->ptr[4].len = cpu_to_be16(cryptlen);
-   desc->ptr[4].j_extent = authsize;
+   to_talitos_ptr_len(>ptr[4], cryptlen, 0);
+   to_talitos_ptr_ext_set(>ptr[4], authsize, 0);
 
sg_link_tbl_len = cryptlen;
if (edesc->desc.hdr & DESC_HDR_MODE1_MDEU_CICV)
@@ -1150,7 +1158,7 @@ static int ipsec_esp(struct talitos_edesc *edesc, struct 
aead_request *areq,
areq->assoclen, sg_link_tbl_len,
>link_tbl[tbl_off])) >
   1) {
-   desc->ptr[4].j_extent |= DESC_PTR_LNKTBL_JUMP;
+   

[PATCH v2 4/7] crypto: talitos - Implement AEAD for SEC1 using HMAC_SNOOP_NO_AFEU

[Christophe Leroy]

This patchs enhances the IPSEC_ESP related functions for them to
also supports the same operations with descriptor type
HMAC_SNOOP_NO_AFEU.

The differences between the two descriptor types are:
* pointeurs 2 and 3 are swaped (Confidentiality key and
Primary EU Context IN)
* HMAC_SNOOP_NO_AFEU has CICV out in pointer 6
* HMAC_SNOOP_NO_AFEU has no primary EU context out so we get it
from the end of data out

Signed-off-by: Christophe Leroy 
---
 drivers/crypto/talitos.c | 209 ---
 1 file changed, 124 insertions(+), 85 deletions(-)

diff --git a/drivers/crypto/talitos.c b/drivers/crypto/talitos.c
index b0d3c24..4ff03c3 100644
--- a/drivers/crypto/talitos.c
+++ b/drivers/crypto/talitos.c
@@ -940,7 +940,13 @@ static void ipsec_esp_unmap(struct device *dev,
struct talitos_edesc *edesc,
struct aead_request *areq)
 {
-   unmap_single_talitos_ptr(dev, >desc.ptr[6], DMA_FROM_DEVICE);
+   struct crypto_aead *aead = crypto_aead_reqtfm(areq);
+   struct talitos_ctx *ctx = crypto_aead_ctx(aead);
+   unsigned int ivsize = crypto_aead_ivsize(aead);
+
+   if (edesc->desc.hdr & DESC_HDR_TYPE_IPSEC_ESP)
+   unmap_single_talitos_ptr(dev, >desc.ptr[6],
+DMA_FROM_DEVICE);
unmap_single_talitos_ptr(dev, >desc.ptr[3], DMA_TO_DEVICE);
unmap_single_talitos_ptr(dev, >desc.ptr[2], DMA_TO_DEVICE);
unmap_single_talitos_ptr(dev, >desc.ptr[0], DMA_TO_DEVICE);
@@ -951,6 +957,13 @@ static void ipsec_esp_unmap(struct device *dev,
if (edesc->dma_len)
dma_unmap_single(dev, edesc->dma_link_tbl, edesc->dma_len,
 DMA_BIDIRECTIONAL);
+
+   if (!(edesc->desc.hdr & DESC_HDR_TYPE_IPSEC_ESP)) {
+   unsigned int dst_nents = edesc->dst_nents ? : 1;
+
+   sg_pcopy_to_buffer(areq->dst, dst_nents, ctx->iv, ivsize,
+  areq->assoclen + areq->cryptlen - ivsize);
+   }
 }
 
 /*
@@ -960,6 +973,8 @@ static void ipsec_esp_encrypt_done(struct device *dev,
   struct talitos_desc *desc, void *context,
   int err)
 {
+   struct talitos_private *priv = dev_get_drvdata(dev);
+   bool is_sec1 = has_ftr_sec1(priv);
struct aead_request *areq = context;
struct crypto_aead *authenc = crypto_aead_reqtfm(areq);
unsigned int authsize = crypto_aead_authsize(authenc);
@@ -973,8 +988,11 @@ static void ipsec_esp_encrypt_done(struct device *dev,
 
/* copy the generated ICV to dst */
if (edesc->icv_ool) {
-   icvdata = >link_tbl[edesc->src_nents +
-  edesc->dst_nents + 2];
+   if (is_sec1)
+   icvdata = edesc->buf + areq->assoclen + areq->cryptlen;
+   else
+   icvdata = >link_tbl[edesc->src_nents +
+  edesc->dst_nents + 2];
sg = sg_last(areq->dst, edesc->dst_nents);
memcpy((char *)sg_virt(sg) + sg->length - authsize,
   icvdata, authsize);
@@ -995,6 +1013,8 @@ static void ipsec_esp_decrypt_swauth_done(struct device 
*dev,
struct talitos_edesc *edesc;
struct scatterlist *sg;
char *oicv, *icv;
+   struct talitos_private *priv = dev_get_drvdata(dev);
+   bool is_sec1 = has_ftr_sec1(priv);
 
edesc = container_of(desc, struct talitos_edesc, desc);
 
@@ -1006,7 +1026,12 @@ static void ipsec_esp_decrypt_swauth_done(struct device 
*dev,
icv = (char *)sg_virt(sg) + sg->length - authsize;
 
if (edesc->dma_len) {
-   oicv = (char *)>link_tbl[edesc->src_nents +
+   if (is_sec1)
+   oicv = (char *)>dma_link_tbl +
+  req->assoclen + req->cryptlen;
+   else
+   oicv = (char *)
+  >link_tbl[edesc->src_nents +
edesc->dst_nents + 2];
if (edesc->icv_ool)
icv = oicv + authsize;
@@ -1145,42 +1170,52 @@ static int ipsec_esp(struct talitos_edesc *edesc, 
struct aead_request *areq,
int tbl_off = 0;
int sg_count, ret;
int sg_link_tbl_len;
+   bool sync_needed = false;
+   struct talitos_private *priv = dev_get_drvdata(dev);
+   bool is_sec1 = has_ftr_sec1(priv);
 
/* hmac key */
map_single_talitos_ptr(dev, >ptr[0], ctx->authkeylen, >key,
   DMA_TO_DEVICE);
 
-   sg_count = dma_map_sg(dev, areq->src, edesc->src_nents ?: 1,
- (areq->src == areq->dst) ? 

[PATCH v2 3/7] crypto: talitos - making mapping helpers more generic

[Christophe Leroy]

In preparation of IPSEC for SEC1, first step is to make the mapping
helpers more generic so that they can also be used by AEAD functions.

First, the functions are moved before IPSEC functions in talitos.c

talitos_sg_unmap() and unmap_sg_talitos_ptr() are merged as they
are quite similar, the second one handling the SEC1 case an calling
the first one for SEC2

map_sg_in_talitos_ptr() and map_sg_out_talitos_ptr() are merged
into talitos_sg_map() and enhenced to support offseted zones
as used for AEAD. The actual mapping is now performed outside that
helper. The DMA sync is also done outside to not make it several
times.

talitos_edesc_alloc() size calculation are fixed to also take into
account AEAD specific parts also for SEC1

Signed-off-by: Christophe Leroy 
---
 drivers/crypto/talitos.c | 230 +++
 1 file changed, 93 insertions(+), 137 deletions(-)

diff --git a/drivers/crypto/talitos.c b/drivers/crypto/talitos.c
index beb369e..b0d3c24 100644
--- a/drivers/crypto/talitos.c
+++ b/drivers/crypto/talitos.c
@@ -911,45 +911,28 @@ struct talitos_edesc {
 static void talitos_sg_unmap(struct device *dev,
 struct talitos_edesc *edesc,
 struct scatterlist *src,
-struct scatterlist *dst)
+struct scatterlist *dst,
+unsigned int len, unsigned int offset)
 {
+   struct talitos_private *priv = dev_get_drvdata(dev);
+   bool is_sec1 = has_ftr_sec1(priv);
unsigned int src_nents = edesc->src_nents ? : 1;
unsigned int dst_nents = edesc->dst_nents ? : 1;
 
+   if (is_sec1 && dst && dst_nents > 1) {
+   dma_sync_single_for_device(dev, edesc->dma_link_tbl + offset,
+  len, DMA_FROM_DEVICE);
+   sg_pcopy_from_buffer(dst, dst_nents, edesc->buf + offset, len,
+offset);
+   }
if (src != dst) {
-   dma_unmap_sg(dev, src, src_nents, DMA_TO_DEVICE);
+   if (src_nents == 1 || !is_sec1)
+   dma_unmap_sg(dev, src, src_nents, DMA_TO_DEVICE);
 
-   if (dst) {
+   if (dst && (dst_nents == 1 || !is_sec1))
dma_unmap_sg(dev, dst, dst_nents, DMA_FROM_DEVICE);
-   }
-   } else
+   } else if (src_nents == 1 || !is_sec1) {
dma_unmap_sg(dev, src, src_nents, DMA_BIDIRECTIONAL);
-}
-
-static void unmap_sg_talitos_ptr(struct device *dev, struct scatterlist *src,
-struct scatterlist *dst, unsigned int len,
-struct talitos_edesc *edesc)
-{
-   struct talitos_private *priv = dev_get_drvdata(dev);
-   bool is_sec1 = has_ftr_sec1(priv);
-
-   if (is_sec1) {
-   if (!edesc->src_nents) {
-   dma_unmap_sg(dev, src, 1,
-dst != src ? DMA_TO_DEVICE
-   : DMA_BIDIRECTIONAL);
-   }
-   if (dst && edesc->dst_nents) {
-   dma_sync_single_for_device(dev,
-  edesc->dma_link_tbl + len,
-  len, DMA_FROM_DEVICE);
-   sg_copy_from_buffer(dst, edesc->dst_nents ? : 1,
-   edesc->buf + len, len);
-   } else if (dst && dst != src) {
-   dma_unmap_sg(dev, dst, 1, DMA_FROM_DEVICE);
-   }
-   } else {
-   talitos_sg_unmap(dev, edesc, src, dst);
}
 }
 
@@ -962,7 +945,8 @@ static void ipsec_esp_unmap(struct device *dev,
unmap_single_talitos_ptr(dev, >desc.ptr[2], DMA_TO_DEVICE);
unmap_single_talitos_ptr(dev, >desc.ptr[0], DMA_TO_DEVICE);
 
-   talitos_sg_unmap(dev, edesc, areq->src, areq->dst);
+   talitos_sg_unmap(dev, edesc, areq->src, areq->dst, areq->cryptlen,
+areq->assoclen);
 
if (edesc->dma_len)
dma_unmap_single(dev, edesc->dma_link_tbl, edesc->dma_len,
@@ -1110,99 +1094,37 @@ static inline int sg_to_link_tbl(struct scatterlist 
*sg, int sg_count,
 link_tbl_ptr);
 }
 
-int map_sg_in_talitos_ptr(struct device *dev, struct scatterlist *src,
- unsigned int len, struct talitos_edesc *edesc,
- enum dma_data_direction dir, struct talitos_ptr *ptr)
+int talitos_sg_map(struct device *dev, struct scatterlist *src,
+  unsigned int len, struct talitos_edesc *edesc,
+  struct talitos_ptr *ptr,
+  int sg_count, unsigned int offset, int tbl_off)
 {
-   int sg_count;
struct talitos_private *priv = dev_get_drvdata(dev);
bool is_sec1 = 

[PATCH v2 0/7] crypto: talitos - implementation of AEAD for SEC1

[Christophe Leroy]

This set of patches provides the implementation of AEAD for
talitos SEC1.

Changes in v2:
* Fixed compilation issue introduced by later cosmetic changes
requested by checkpatch script
* split "making mapping helpers more generic" in two parts
to better see the changes done after the move.
* reworked the DMA sync associated with mapping in order to not
spend time syncing several times

Christophe Leroy (7):
  crypto: talitos - using helpers for all talitos_ptr operations
  crypto: talitos - move mapping helpers before IPSEC functions
  crypto: talitos - making mapping helpers more generic
  crypto: talitos - Implement AEAD for SEC1 using HMAC_SNOOP_NO_AFEU
  crypto: talitos - sg_to_link_tbl() not used anymore, remove it
  crypto: talitos - implement cra_priority
  crypto: talitos - templates for AEAD using HMAC_SNOOP_NO_AFEU

 drivers/crypto/talitos.c | 672 ++-
 1 file changed, 426 insertions(+), 246 deletions(-)

-- 
2.1.0

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[PATCH v2 5/7] crypto: talitos - sg_to_link_tbl() not used anymore, remove it

[Christophe Leroy]

Signed-off-by: Christophe Leroy 
---
 drivers/crypto/talitos.c | 8 
 1 file changed, 8 deletions(-)

diff --git a/drivers/crypto/talitos.c b/drivers/crypto/talitos.c
index 4ff03c3..ff8cf39 100644
--- a/drivers/crypto/talitos.c
+++ b/drivers/crypto/talitos.c
@@ -,14 +,6 @@ next:
return count;
 }
 
-static inline int sg_to_link_tbl(struct scatterlist *sg, int sg_count,
-int cryptlen,
-struct talitos_ptr *link_tbl_ptr)
-{
-   return sg_to_link_tbl_offset(sg, sg_count, 0, cryptlen,
-link_tbl_ptr);
-}
-
 int talitos_sg_map(struct device *dev, struct scatterlist *src,
   unsigned int len, struct talitos_edesc *edesc,
   struct talitos_ptr *ptr,
-- 
2.1.0

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[PATCH v2 6/7] crypto: talitos - implement cra_priority

[Christophe Leroy]

SEC1 doesn't have IPSEC_ESP descriptor type but it is able to perform
IPSEC using HMAC_SNOOP_NO_AFEU, which is also existing on SEC2
In order to be able to define descriptors templates for SEC1 without
breaking SEC2+, we have to give lower priority to HMAC_SNOOP_NO_AFEU
so that SEC2+ selects IPSEC_ESP and not HMAC_SNOOP_NO_AFEU which is
less performant.

This is done by adding a priority field in the template. If the field
is 0, we use the default priority, otherwise we used the one in the
field.

Signed-off-by: Christophe Leroy 
---
 drivers/crypto/talitos.c | 6 +-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/crypto/talitos.c b/drivers/crypto/talitos.c
index ff8cf39..dfd3a93 100644
--- a/drivers/crypto/talitos.c
+++ b/drivers/crypto/talitos.c
@@ -2120,6 +2120,7 @@ static int ahash_setkey(struct crypto_ahash *tfm, const 
u8 *key,
 
 struct talitos_alg_template {
u32 type;
+   u32 priority;
union {
struct crypto_alg crypto;
struct ahash_alg hash;
@@ -2897,7 +2898,10 @@ static struct talitos_crypto_alg 
*talitos_alg_alloc(struct device *dev,
}
 
alg->cra_module = THIS_MODULE;
-   alg->cra_priority = TALITOS_CRA_PRIORITY;
+   if (t_alg->algt.priority)
+   alg->cra_priority = t_alg->algt.priority;
+   else
+   alg->cra_priority = TALITOS_CRA_PRIORITY;
alg->cra_alignmask = 0;
alg->cra_ctxsize = sizeof(struct talitos_ctx);
alg->cra_flags |= CRYPTO_ALG_KERN_DRIVER_ONLY;
-- 
2.1.0

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Re: [PATCH V3 8/9] cpufreq: Keep policy->freq_table sorted in ascending order

[Rafael J. Wysocki]

On Mon, Jun 6, 2016 at 2:24 PM, Viresh Kumar  wrote:
> On 6 June 2016 at 17:40, Rafael J. Wysocki  wrote:
>> On Monday, June 06, 2016 09:22:31 AM Viresh Kumar wrote:
>
>>> I agree with that, though that requires larger changes across multiple
>>> sites.
>>
>> What changes and where?
>
> s/larger/some :)
>
> So we can change all the callers of cpufreq_frequency_table_target(),

But why?

It just works as a static inline wrapper around cpufreq_find_index_l()
for the code in question after this patch, doesn't it?

So if the caller knows it will always ask for RELATION_L, why bother
with using the wrapper?

Also I'm wondering about the cpufreq_for_each_valid_entry() used all
over.  Can't the things be arranged so all of the entries are valid?
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Re: unrecoverable exception on G5 with CONFIG_PPC_EARLY_DEBUG enabled

[Michael Ellerman]

On Mon, 2016-06-06 at 10:52 +0300, Denis Kirjanov wrote:

> Update: now with the proper mailing address.
> 
> Hi,
> 
> Posting if anyone knows how to quickly fix it :)

Sorry but no.

> Enabling  CONFIG_PPC_EARLY_DEBUG on my quad G5 causes kernel to die
> with the  unrecoverable exception 4100.

That means you took a SLB miss when MSR_RI was off.

What's at c0ace328 ?

> I haven't bisected this yet. Photo attached.

A bisect would be awesome.

cheers

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Re: [PATCH V3 8/9] cpufreq: Keep policy->freq_table sorted in ascending order

[Viresh Kumar]

On 6 June 2016 at 17:40, Rafael J. Wysocki  wrote:
> On Monday, June 06, 2016 09:22:31 AM Viresh Kumar wrote:

>> I agree with that, though that requires larger changes across multiple
>> sites.
>
> What changes and where?

s/larger/some :)

So we can change all the callers of cpufreq_frequency_table_target(),
like the governors, ondemand-bias stub drivers, core, etc and call
the dedicated 'relation' specific routines directly, as we mostly know
in advance the 'relation' in which we want to update the freq.

And, so doing that with a dedicated patch might be better.

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Re: [PATCH v3] powerpc: spinlock: Fix spin_unlock_wait()

[Michael Ellerman]

On Mon, 2016-06-06 at 13:56 +0200, Peter Zijlstra wrote:
> On Mon, Jun 06, 2016 at 09:42:20PM +1000, Michael Ellerman wrote:
> > +static inline void arch_spin_unlock_wait(arch_spinlock_t *lock)
> > +{
> > +   arch_spinlock_t lock_val;
> > +
> > +   smp_mb();
> > +
> > +   /*
> > +* Atomically load and store back the lock value (unchanged). This
> > +* ensures that our observation of the lock value is ordered with
> > +* respect to other lock operations.
> > +*/
> > +   __asm__ __volatile__(
> > +"1:" PPC_LWARX(%0, 0, %2, 0) "\n"
> > +"  stwcx. %0, 0, %2\n"
> > +"  bne- 1b\n"
> > +   : "=" (lock_val), "+m" (*lock)
> > +   : "r" (lock)
> > +   : "cr0", "xer");
> > +
> > +   if (arch_spin_value_unlocked(lock_val))
> > +   goto out;
> > +
> > +   while (!arch_spin_value_unlocked(*lock)) {
> > +   HMT_low();
> > +   if (SHARED_PROCESSOR)
> > +   __spin_yield(lock);
> > +   }
> > +   HMT_medium();
> > +
> > +out:
> > +   smp_mb();
> > +}
> 
> Why the move to in-line this implementation? It looks like a fairly big
> function.

I agree it's not pretty.

I just didn't think having it out-of-line made it easier to understand. The
previous version had:

  static inline void arch_spin_unlock_wait(arch_spinlock_t *lock)
  {
...
if (!arch_spin_is_locked_sync(lock))
goto out;

Then elsewhere:

  static inline bool arch_spin_is_locked_sync(arch_spinlock_t *lock)
  {
...
return !arch_spin_value_unlocked(tmp);
  }


So two negations and one routine called "locked" and one "unlocked", which just
didn't read well IMHO.

Another minor concern was that someone might be "clever" and call the _sync()
version manually (though hopefully we'd catch that in review).

I'm not beholden to v3 though if you hate it.

cheers

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Re: [PATCH V3 8/9] cpufreq: Keep policy->freq_table sorted in ascending order

[Rafael J. Wysocki]

On Monday, June 06, 2016 09:22:31 AM Viresh Kumar wrote:
> On 03-06-16, 16:48, Steve Muckle wrote:
> > On Fri, Jun 03, 2016 at 07:05:14PM +0530, Viresh Kumar wrote:
> > ...
> > > @@ -468,20 +469,15 @@ unsigned int acpi_cpufreq_fast_switch(struct 
> > > cpufreq_policy *policy,
> > >   struct acpi_cpufreq_data *data = policy->driver_data;
> > >   struct acpi_processor_performance *perf;
> > >   struct cpufreq_frequency_table *entry;
> > > - unsigned int next_perf_state, next_freq, freq;
> > > + unsigned int next_perf_state, next_freq, index;
> > >  
> > >   /*
> > >* Find the closest frequency above target_freq.
> > > -  *
> > > -  * The table is sorted in the reverse order with respect to the
> > > -  * frequency and all of the entries are valid (see the initialization).
> > >*/
> > > - entry = policy->freq_table;
> > > - do {
> > > - entry++;
> > > - freq = entry->frequency;
> > > - } while (freq >= target_freq && freq != CPUFREQ_TABLE_END);
> > > - entry--;
> > > + index = cpufreq_frequency_table_target(policy, target_freq,
> > > +CPUFREQ_RELATION_L);
> > 
> > Can we call cpufreq_find_index_l directly here? Seems like we could
> > phase out cpufreq_frequency_table_target() for the most part and call
> > the helpers directly. It would avoid some code bloat, an unnecessary
> > switch statement and an error check for an invalid frequency table which
> > seems unnecessary for every frequency table lookup.
> 
> I agree with that, though that requires larger changes across multiple
> sites.

What changes and where?

> I hope it will be fine if I do it in a separate patch on top of
> all this. Right ?

Depending.

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Re: [PATCH v3] powerpc: spinlock: Fix spin_unlock_wait()

[Peter Zijlstra]

On Mon, Jun 06, 2016 at 09:42:20PM +1000, Michael Ellerman wrote:
> +static inline void arch_spin_unlock_wait(arch_spinlock_t *lock)
> +{
> + arch_spinlock_t lock_val;
> +
> + smp_mb();
> +
> + /*
> +  * Atomically load and store back the lock value (unchanged). This
> +  * ensures that our observation of the lock value is ordered with
> +  * respect to other lock operations.
> +  */
> + __asm__ __volatile__(
> +"1:  " PPC_LWARX(%0, 0, %2, 0) "\n"
> +"stwcx. %0, 0, %2\n"
> +"bne- 1b\n"
> + : "=" (lock_val), "+m" (*lock)
> + : "r" (lock)
> + : "cr0", "xer");
> +
> + if (arch_spin_value_unlocked(lock_val))
> + goto out;
> +
> + while (!arch_spin_value_unlocked(*lock)) {
> + HMT_low();
> + if (SHARED_PROCESSOR)
> + __spin_yield(lock);
> + }
> + HMT_medium();
> +
> +out:
> + smp_mb();
> +}

Why the move to in-line this implementation? It looks like a fairly big
function.
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Re: Status of DPAA integration for NXP QoriQ?

[Sebastian Huber]

On 04/06/16 02:07, Scott Wood wrote:

On Mon, 2016-05-09 at 10:29 +0200, Sebastian Huber wrote:

Hello,

the "fman" Ethernet driver was integrated in mainline Linux Dezember
2015 ("drivers/net/ethernet/freescale/fman"). It seems that the other
parts, e.g. BMan, QMan ("drivers/soc/fsl/qbman") and basic DPAA Ethernet
support ("drivers/net/ethernet/freescale/dpaa") are still missing. Are
there any plans to integrate them? I didn't notice any activity on the
mailing list in the last couple of months in this respect.

Yes, we are still planning to integrate the other components.


Good to hear, do you plan to add support for receive checksum offload as 
well?


https://freescale.jiveon.com/thread/388076

--
Sebastian Huber, embedded brains GmbH

Address : Dornierstr. 4, D-82178 Puchheim, Germany
Phone   : +49 89 189 47 41-16
Fax : +49 89 189 47 41-09
E-Mail  : sebastian.hu...@embedded-brains.de
PGP : Public key available on request.

Diese Nachricht ist keine geschäftliche Mitteilung im Sinne des EHUG.

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[PATCH v3] powerpc: spinlock: Fix spin_unlock_wait()

[Michael Ellerman]

From: Boqun Feng 

There is an ordering issue with spin_unlock_wait() on powerpc, because
the spin_lock primitive is an ACQUIRE and an ACQUIRE is only ordering
the load part of the operation with memory operations following it.
Therefore the following event sequence can happen:

CPU 1   CPU 2   CPU 3

==  ==
spin_unlock();
spin_lock():
  r1 = *lock; // r1 == 0;
o = object; o = READ_ONCE(object); // reordered here
object = NULL;
smp_mb();
spin_unlock_wait();
  *lock = 1;
smp_mb();
o->dead = true; < o = READ_ONCE(object); > // reordered upwards
if (o) // true
BUG_ON(o->dead); // true!!

To fix this, we add a "nop" ll/sc loop in arch_spin_unlock_wait() on
ppc, the "nop" ll/sc loop reads the lock
value and writes it back atomically, in this way it will synchronize the
view of the lock on CPU1 with that on CPU2. Therefore in the scenario
above, either CPU2 will fail to get the lock at first or CPU1 will see
the lock acquired by CPU2, both cases will eliminate this bug. This is a
similar idea as what Will Deacon did for ARM64 in:

  d86b8da04dfa ("arm64: spinlock: serialise spin_unlock_wait against concurrent 
lockers")

Furthermore, if the "nop" ll/sc figures out the lock is locked, we
actually don't need to do the "nop" ll/sc trick again, we can just do a
normal load+check loop for the lock to be released, because in that
case, spin_unlock_wait() is called when someone is holding the lock, and
the store part of the "nop" ll/sc happens before the lock release of the
current lock holder:

"nop" ll/sc -> spin_unlock()

and the lock release happens before the next lock acquisition:

spin_unlock() -> spin_lock() 

which means the "nop" ll/sc happens before the next lock acquisition:

"nop" ll/sc -> spin_unlock() -> spin_lock() 

With a smp_mb() preceding spin_unlock_wait(), the store of object is
guaranteed to be observed by the next lock holder:

STORE -> smp_mb() -> "nop" ll/sc
-> spin_unlock() -> spin_lock() 

This patch therefore fixes the issue and also cleans the
arch_spin_unlock_wait() a little bit by removing superfluous memory
barriers in loops and consolidating the implementations for PPC32 and
PPC64 into one.

Suggested-by: "Paul E. McKenney" 
Signed-off-by: Boqun Feng 
Reviewed-by: "Paul E. McKenney" 
[mpe: Inline the "nop" ll/sc loop and set EH=0, munge change log]
Signed-off-by: Michael Ellerman 
---
 arch/powerpc/include/asm/spinlock.h | 38 +++--
 arch/powerpc/lib/locks.c| 16 
 2 files changed, 32 insertions(+), 22 deletions(-)

v3 (mpe):
 - Inline the ll/sc loop.
 - Change the EH on the LWARX to 0
 - Rewrite change log to cope with the fact we removed 
arch_spin_is_locked_sync()

v1-->v2:

 - Improve the commit log, suggested by Peter Zijlstra
 - Keep two smp_mb()s for the safety, which though could be deleted
   if all the users have been aduited and fixed later.

diff --git a/arch/powerpc/include/asm/spinlock.h 
b/arch/powerpc/include/asm/spinlock.h
index 523673d7583c..5f84fc147664 100644
--- a/arch/powerpc/include/asm/spinlock.h
+++ b/arch/powerpc/include/asm/spinlock.h
@@ -162,12 +162,38 @@ static inline void arch_spin_unlock(arch_spinlock_t *lock)
lock->slock = 0;
 }
 
-#ifdef CONFIG_PPC64
-extern void arch_spin_unlock_wait(arch_spinlock_t *lock);
-#else
-#define arch_spin_unlock_wait(lock) \
-   do { while (arch_spin_is_locked(lock)) cpu_relax(); } while (0)
-#endif
+static inline void arch_spin_unlock_wait(arch_spinlock_t *lock)
+{
+   arch_spinlock_t lock_val;
+
+   smp_mb();
+
+   /*
+* Atomically load and store back the lock value (unchanged). This
+* ensures that our observation of the lock value is ordered with
+* respect to other lock operations.
+*/
+   __asm__ __volatile__(
+"1:" PPC_LWARX(%0, 0, %2, 0) "\n"
+"  stwcx. %0, 0, %2\n"
+"  bne- 1b\n"
+   : "=" (lock_val), "+m" (*lock)
+   : "r" (lock)
+   : "cr0", "xer");
+
+   if (arch_spin_value_unlocked(lock_val))
+   goto out;
+
+   while (!arch_spin_value_unlocked(*lock)) {
+   HMT_low();
+   if (SHARED_PROCESSOR)
+   __spin_yield(lock);
+   }
+   HMT_medium();
+
+out:
+   smp_mb();
+}
 
 /*
  * Read-write spinlocks, allowing multiple readers
diff --git a/arch/powerpc/lib/locks.c b/arch/powerpc/lib/locks.c
index f7deebdf3365..b7b1237d4aa6 100644
--- a/arch/powerpc/lib/locks.c
+++ b/arch/powerpc/lib/locks.c
@@ -68,19 +68,3 @@ void __rw_yield(arch_rwlock_t *rw)

Re: [v2] powerpc: spinlock: Fix spin_unlock_wait()

[Michael Ellerman]

On Fri, 2016-03-06 at 03:49:48 UTC, Boqun Feng wrote:
> diff --git a/arch/powerpc/include/asm/spinlock.h 
> b/arch/powerpc/include/asm/spinlock.h
> index 523673d7583c..2ed893662866 100644
> --- a/arch/powerpc/include/asm/spinlock.h
> +++ b/arch/powerpc/include/asm/spinlock.h
> @@ -64,6 +64,25 @@ static inline int arch_spin_is_locked(arch_spinlock_t 
> *lock)
>  }
>  
>  /*
> + * Use a ll/sc loop to read the lock value, the STORE part of this operation 
> is
> + * used for making later lock operation observe it.
> + */
> +static inline bool arch_spin_is_locked_sync(arch_spinlock_t *lock)
> +{
> + arch_spinlock_t tmp;
> +
> + __asm__ __volatile__(
> +"1:  " PPC_LWARX(%0, 0, %2, 1) "\n"

As discussed offline I think we want to use EH=0 here (the final parameter).

From the ISA:

  The value of EH provides a hint as to whether the program will perform a
  subsequent store to the word in storage addressed by EA before some other
  processor attempts to modify it.

  0 Other programs might attempt to modify the word in storage addressed by EA
regardless of the result of the corresponding stwcx. instruction.

cheers
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Re: Kernel 4.7: PAGE_GUARDED and _PAGE_NO_CACHE

[Julian Margetson]

On 6/5/2016 10:00 PM, Michael Ellerman wrote:

On Sun, 2016-06-05 at 21:23 -0400, Julian Margetson wrote:

drivers/gpu/drm/drm_vm.c: In function ‘drm_dma_prot’:
drivers/gpu/drm/drm_vm.c:83:6: error: invalid operands to binary |
(have ‘pgprot_t {aka struct }’ and ‘int’)
 tmp |= _PAGE_NO_CACHE;
 ^


That is because that usage is wrong based on type. _PAGE_NO_CACHE is not
of type pgprot_t. What you really need there is

tmp = __pgprot(pgprot_val(tmp) | _PAGE_NO_CACHE);

or a better option would be

tmp = pgprot_noncached_wc(tmp);

-aneesh

tmp = pgprot_noncached_wc(tmp);

compiles but  I then run in to the following

   CC  drivers/gpu/drm/drm_scatter.o
drivers/gpu/drm/drm_scatter.c: In function ‘drm_vmalloc_dma’:
drivers/gpu/drm/drm_scatter.c:44:49: error: invalid operands to binary |
(have ‘pgprot_t {aka struct }’ and ‘int’)
return __vmalloc(size, GFP_KERNEL, PAGE_KERNEL | _PAGE_NO_CACHE);
   ^
drivers/gpu/drm/drm_scatter.c:48:1: warning: control reaches end of
non-void function [-Wreturn-type]
   }
   ^

Aneesh showed you how to fix that in his reply above.

 return __vmalloc(size, GFP_KERNEL, pgprot_noncached_wc(PAGE_KERNEL));

cheers




Thanks .

With the two adjustment

tmp = pgprot_noncached_wc(tmp);

and

return __vmalloc(size, GFP_KERNEL, pgprot_noncached_wc(PAGE_KERNEL));

The rc2 builds and boots  on Sam460ex

Regards

Julian


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Re: [PATCH V10 00/28] Add new powerpc specific ELF core notes

[Anshuman Khandual]

On 06/03/2016 03:56 AM, Cyril Bur wrote:
> On 1 June 2016 at 18:26, Anshuman Khandual 
> wrote:
> 
>> On 05/31/2016 04:42 AM, Michael Ellerman wrote:
>>> Hi Laurent,
>>>
>>> Sorry no. My next branch closed for 4.7 about 3 weeks ago.
>>>
>>> This series has been blocked for a long time on the gdb support, but
>> that is
>>> now working. However it still doesn't pass its own selftests, and I had
>> some
>>
>> This series was clearing all of the selftests at the time it was posted.
>> But yes, it has some assumptions from timing and sync perspective which
>> gets broken some times as the kernel changes. Its been bit difficult to
>> perfect the sync requirements as we can do only some much inside the
>> transaction once it gets started. There are scopes here to improve these
>> selftests but not clearing them today does not really mean the patches are
>> now functionally broken.
>>
>>> disagreements with the implementation - it duplicates a lot of code
>> rather
>>> than refactoring things.
>>
>> hmm, sorry, I dont remember the context here. Can you please point to the
>> discussion in this regard ?
>>
>>>
>>> I'm waiting on a patch from Cyril which will rework how the TM FP state
>> is
>>> handled, and that should make this series easier to implement.
>>
>> Can you please elaborate on this ? Has this patch been posted in the
>> mailing
>> list ? How does this make it easier for us to implement these ELF notes ?
> 
> 
> Hi Anshuman,
> 
> I'm doing a bit of a rewrite of the TM handling of the FP/VMX/VSX state.
> 
> At the moment is is rather confusing since pt_regs is the always the 'live'
> state
> and theres a ckpt_regs that is the pt_regs for the checkpointed state.
> FPU/VMX/VSX
> is done differently which is really only creating confusion so I'm changing
> it to do the
> same at for pt_regs/ckpt_regs. Ultimately this is part of more work from me

But that changes the basic semantics on which this ptrace series is written.
With this change, a significant part of the ptrace series has to be changed.
Its just an improvement on how we store running and check pointed values for
FP/VSX/VMX registers inside the kernel. How does it improve ptrace interface
from the user point of view ? If not, then why this change is necessary for
the acceptance of this patch series ? This change should be implemented as
an independent work and then necessary ptrace change can be incorporated
there after.

> but
> Michael has told me that at least this bit is useful now so I'm splitting
> it off from
> the bigger picture and sending asap. At the very least it will make it
> easier to know
> what and where the transactional state it and where the checkpointed state
> is.
> 
> It isn't on the list but I hope I'll get it out today.

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Re: [RESEND PATCH v2 2/6] PCI: Set PCI_BUS_FLAGS_MSI_REMAP if MSI controller enables IRQ remapping

[Yongji Xie]

On 2016/6/6 5:11, kbuild test robot wrote:


Hi,

[auto build test ERROR on vfio/next]
[also build test ERROR on v4.7-rc1 next-20160603]
[cannot apply to pci/next]
[if your patch is applied to the wrong git tree, please drop us a note to help 
improve the system]

url:
https://github.com/0day-ci/linux/commits/Yongji-Xie/PCI-Add-a-new-PCI_BUS_FLAGS_MSI_REMAP-flag/20160530-215348
base:   https://github.com/awilliam/linux-vfio.git next
config: arm-allmodconfig (attached as .config)
compiler: arm-linux-gnueabi-gcc (Debian 5.3.1-8) 5.3.1 20160205
reproduce:
 wget 
https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross
 -O ~/bin/make.cross
 chmod +x ~/bin/make.cross
 # save the attached .config to linux build tree
 make.cross ARCH=arm

All errors (new ones prefixed by >>):

drivers/pci/msi.c: In function 'pci_bus_msi_isolated':

drivers/pci/msi.c:1146:20: error: 'MSI_FLAG_IRQ_REMAPPING' undeclared (first 
use in this function)

  if (info->flags & MSI_FLAG_IRQ_REMAPPING)
^
drivers/pci/msi.c:1146:20: note: each undeclared identifier is reported 
only once for each function it appears in

vim +/MSI_FLAG_IRQ_REMAPPING +1146 drivers/pci/msi.c

   1140 struct msi_domain_info *info;
   1141 
   1142 if (!domain)
   1143 return 0;
   1144 
   1145 info = msi_get_domain_info(domain);

1146if (info->flags & MSI_FLAG_IRQ_REMAPPING)

   1147 return 1;
   1148 #endif
   1149 return 0;


This fault is expected because this patch is based on patchset [1] which
introduce flag MSI_FLAG_IRQ_REMAPPING.

[1] 
https://www.mail-archive.com/linux-kernel%40vger.kernel.org/msg1138820.html


Thanks,
Yongji

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Re: [RESEND PATCH v2 2/6] PCI: Set PCI_BUS_FLAGS_MSI_REMAP if MSI controller enables IRQ remapping

[Yongji Xie]

On 2016/6/6 4:10, kbuild test robot wrote:


Hi,

[auto build test ERROR on vfio/next]
[also build test ERROR on v4.7-rc1 next-20160603]
[cannot apply to pci/next]
[if your patch is applied to the wrong git tree, please drop us a note to help 
improve the system]

url:
https://github.com/0day-ci/linux/commits/Yongji-Xie/PCI-Add-a-new-PCI_BUS_FLAGS_MSI_REMAP-flag/20160530-215348
base:   https://github.com/awilliam/linux-vfio.git next
config: arm-sa1100 (attached as .config)
compiler: arm-linux-gnueabi-gcc (Debian 5.3.1-8) 5.3.1 20160205
reproduce:
 wget 
https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross
 -O ~/bin/make.cross
 chmod +x ~/bin/make.cross
 # save the attached .config to linux build tree
 make.cross ARCH=arm

All errors (new ones prefixed by >>):

drivers/built-in.o: In function `pci_set_bus_msi_domain':

arm_pmu.c:(.text+0x5c58): undefined reference to `pci_bus_msi_isolated'


Sorry for this fault. I will fix it in next version.  The 
pci_bus_msi_isolated() should not
depend on CONFIG_PCI_MSI, I would move this function from 
drivers/pci/msi.c to

drivers/pci/probe.c.

Thanks,
Yongji

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Re: [RFC v3 07/45] avr32: dma-mapping: Use unsigned long for dma_attrs

[Hans-Christian Noren Egtvedt]

Around Thu 02 Jun 2016 17:39:09 +0200 or thereabout, Krzysztof Kozlowski wrote:
> Split out subsystem specific changes for easier reviews. This will be
> squashed with main commit.
> 
> Signed-off-by: Krzysztof Kozlowski 

Acked-by: Hans-Christian Noren Egtvedt 

> ---
>  arch/avr32/mm/dma-coherent.c | 8 
>  1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/avr32/mm/dma-coherent.c b/arch/avr32/mm/dma-coherent.c
> index 92cf1fb2b3e6..fc51f4421933 100644
> --- a/arch/avr32/mm/dma-coherent.c
> +++ b/arch/avr32/mm/dma-coherent.c
> @@ -99,7 +99,7 @@ static void __dma_free(struct device *dev, size_t size,
>  }
>  
>  static void *avr32_dma_alloc(struct device *dev, size_t size,
> - dma_addr_t *handle, gfp_t gfp, struct dma_attrs *attrs)
> + dma_addr_t *handle, gfp_t gfp, unsigned long attrs)
>  {
>   struct page *page;
>   dma_addr_t phys;
> @@ -119,7 +119,7 @@ static void *avr32_dma_alloc(struct device *dev, size_t 
> size,
>  }
>  
>  static void avr32_dma_free(struct device *dev, size_t size,
> - void *cpu_addr, dma_addr_t handle, struct dma_attrs *attrs)
> + void *cpu_addr, dma_addr_t handle, unsigned long attrs)
>  {
>   struct page *page;
>  
> @@ -142,7 +142,7 @@ static void avr32_dma_free(struct device *dev, size_t 
> size,
>  
>  static dma_addr_t avr32_dma_map_page(struct device *dev, struct page *page,
>   unsigned long offset, size_t size,
> - enum dma_data_direction direction, struct dma_attrs *attrs)
> + enum dma_data_direction direction, unsigned long attrs)
>  {
>   void *cpu_addr = page_address(page) + offset;
>  
> @@ -152,7 +152,7 @@ static dma_addr_t avr32_dma_map_page(struct device *dev, 
> struct page *page,
>  
>  static int avr32_dma_map_sg(struct device *dev, struct scatterlist *sglist,
>   int nents, enum dma_data_direction direction,
> - struct dma_attrs *attrs)
> + unsigned long attrs)
>  {
>   int i;
>   struct scatterlist *sg;
-- 
mvh
Hans-Christian Noren Egtvedt
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Re: [RFC v3 44/45] dma-mapping: Remove dma_get_attr

[Hans-Christian Noren Egtvedt]

Around Thu 02 Jun 2016 17:39:46 +0200 or thereabout, Krzysztof Kozlowski wrote:
> After switching DMA attributes to unsigned long it is easier to just
> compare the bits.
> 
> Signed-off-by: Krzysztof Kozlowski 
> ---
>  Documentation/DMA-API.txt  |  4 +--
>  arch/arc/mm/dma.c  |  4 +--
>  arch/arm/mm/dma-mapping.c  | 36 
> --
>  arch/arm/xen/mm.c  |  4 +--
>  arch/arm64/mm/dma-mapping.c| 10 +++
>  arch/avr32/mm/dma-coherent.c   |  4 +--

For the AVR32 related change

Acked-by: Hans-Christian Noren Egtvedt 

>  arch/ia64/sn/pci/pci_dma.c | 10 ++-
>  arch/metag/kernel/dma.c|  2 +-
>  arch/mips/mm/dma-default.c |  6 ++---
>  arch/openrisc/kernel/dma.c |  4 +--
>  arch/parisc/kernel/pci-dma.c   |  2 +-
>  arch/powerpc/platforms/cell/iommu.c| 10 +++
>  drivers/gpu/drm/rockchip/rockchip_drm_gem.c|  2 +-
>  drivers/iommu/dma-iommu.c  |  2 +-
>  drivers/media/v4l2-core/videobuf2-dma-contig.c |  2 +-
>  include/linux/dma-mapping.h| 13 --
>  16 files changed, 46 insertions(+), 69 deletions(-)



> diff --git a/arch/avr32/mm/dma-coherent.c b/arch/avr32/mm/dma-coherent.c
> index fc51f4421933..58610d0df7ed 100644
> --- a/arch/avr32/mm/dma-coherent.c
> +++ b/arch/avr32/mm/dma-coherent.c
> @@ -109,7 +109,7 @@ static void *avr32_dma_alloc(struct device *dev, size_t 
> size,
>   return NULL;
>   phys = page_to_phys(page);
>  
> - if (dma_get_attr(DMA_ATTR_WRITE_COMBINE, attrs)) {
> + if (attrs & DMA_ATTR_WRITE_COMBINE) {
>   /* Now, map the page into P3 with write-combining turned on */
>   *handle = phys;
>   return __ioremap(phys, size, _PAGE_BUFFER);
> @@ -123,7 +123,7 @@ static void avr32_dma_free(struct device *dev, size_t 
> size,
>  {
>   struct page *page;
>  
> - if (dma_get_attr(DMA_ATTR_WRITE_COMBINE, attrs)) {
> + if (attrs & DMA_ATTR_WRITE_COMBINE) {
>   iounmap(cpu_addr);
>  
>   page = phys_to_page(handle);



-- 
mvh
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[Patch v3 3/5] fsl/qe: Make regs resouce_size_t

[Zhao Qiang]

Signed-off-by: Zhao Qiang 
---
Changes for v2:
- modify subject
Changes for v3:
- na

 include/soc/fsl/qe/ucc_fast.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/soc/fsl/qe/ucc_fast.h b/include/soc/fsl/qe/ucc_fast.h
index b2633b7..e898895 100644
--- a/include/soc/fsl/qe/ucc_fast.h
+++ b/include/soc/fsl/qe/ucc_fast.h
@@ -123,7 +123,7 @@ struct ucc_fast_info {
enum qe_clock tx_clock;
enum qe_clock rx_sync;
enum qe_clock tx_sync;
-   u32 regs;
+   resource_size_t regs;
int irq;
u32 uccm_mask;
int bd_mem_part;
-- 
2.1.0.27.g96db324

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[Patch v3 5/5] drivers/net: support hdlc function for QE-UCC

[Zhao Qiang]

The driver add hdlc support for Freescale QUICC Engine.
It support NMSI and TSA mode.

Signed-off-by: Zhao Qiang 
---
Changes for v2:
- remove useless code.
- remove Unnecessary casts
- return IRQ_NONE when there are no interrupt
- remove Useless comments
Changes for v3:
- add crc err and overrun err handling code in hdlc_rx_done.

 MAINTAINERS|7 +
 drivers/net/wan/Kconfig|   11 +
 drivers/net/wan/Makefile   |1 +
 drivers/net/wan/fsl_ucc_hdlc.c | 1192 
 drivers/net/wan/fsl_ucc_hdlc.h |  147 +
 include/soc/fsl/qe/qe.h|1 +
 include/soc/fsl/qe/ucc_fast.h  |   22 +-
 7 files changed, 1379 insertions(+), 2 deletions(-)
 create mode 100644 drivers/net/wan/fsl_ucc_hdlc.c
 create mode 100644 drivers/net/wan/fsl_ucc_hdlc.h

diff --git a/MAINTAINERS b/MAINTAINERS
index 74bbff3..bdada16 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -4572,6 +4572,13 @@ F:   drivers/net/ethernet/freescale/gianfar*
 X: drivers/net/ethernet/freescale/gianfar_ptp.c
 F: Documentation/devicetree/bindings/net/fsl-tsec-phy.txt
 
+FREESCALE QUICC ENGINE UCC HDLC DRIVER
+M: Zhao Qiang 
+L: net...@vger.kernel.org
+L: linuxppc-dev@lists.ozlabs.org
+S: Maintained
+F: drivers/net/wan/fsl_ucc_hdlc*
+
 FREESCALE QUICC ENGINE UCC UART DRIVER
 M: Timur Tabi 
 L: linuxppc-dev@lists.ozlabs.org
diff --git a/drivers/net/wan/Kconfig b/drivers/net/wan/Kconfig
index a2fdd15..9e314b7 100644
--- a/drivers/net/wan/Kconfig
+++ b/drivers/net/wan/Kconfig
@@ -280,6 +280,17 @@ config DSCC4
  To compile this driver as a module, choose M here: the
  module will be called dscc4.
 
+config FSL_UCC_HDLC
+   tristate "Freescale QUICC Engine HDLC support"
+   depends on HDLC
+   depends on QUICC_ENGINE
+   help
+ Driver for Freescale QUICC Engine HDLC controller. The driver
+ supports HDLC in NMSI and TDM mode.
+
+ To compile this driver as a module, choose M here: the
+ module will be called fsl_ucc_hdlc.
+
 config DSCC4_PCISYNC
bool "Etinc PCISYNC features"
depends on DSCC4
diff --git a/drivers/net/wan/Makefile b/drivers/net/wan/Makefile
index c135ef4..25fec40 100644
--- a/drivers/net/wan/Makefile
+++ b/drivers/net/wan/Makefile
@@ -32,6 +32,7 @@ obj-$(CONFIG_WANXL)   += wanxl.o
 obj-$(CONFIG_PCI200SYN)+= pci200syn.o
 obj-$(CONFIG_PC300TOO) += pc300too.o
 obj-$(CONFIG_IXP4XX_HSS)   += ixp4xx_hss.o
+obj-$(CONFIG_FSL_UCC_HDLC) += fsl_ucc_hdlc.o
 
 clean-files := wanxlfw.inc
 $(obj)/wanxl.o:$(obj)/wanxlfw.inc
diff --git a/drivers/net/wan/fsl_ucc_hdlc.c b/drivers/net/wan/fsl_ucc_hdlc.c
new file mode 100644
index 000..19174ac
--- /dev/null
+++ b/drivers/net/wan/fsl_ucc_hdlc.c
@@ -0,0 +1,1192 @@
+/* Freescale QUICC Engine HDLC Device Driver
+ *
+ * Copyright 2016 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "fsl_ucc_hdlc.h"
+
+#define DRV_DESC "Freescale QE UCC HDLC Driver"
+#define DRV_NAME "ucc_hdlc"
+
+#define TDM_PPPOHT_SLIC_MAXIN
+#define BROKEN_FRAME_INFO
+
+static struct ucc_tdm_info utdm_primary_info = {
+   .uf_info = {
+   .tsa = 0,
+   .cdp = 0,
+   .cds = 1,
+   .ctsp = 1,
+   .ctss = 1,
+   .revd = 0,
+   .urfs = 256,
+   .utfs = 256,
+   .urfet = 128,
+   .urfset = 192,
+   .utfet = 128,
+   .utftt = 0x40,
+   .ufpt = 256,
+   .mode = UCC_FAST_PROTOCOL_MODE_HDLC,
+   .ttx_trx = UCC_FAST_GUMR_TRANSPARENT_TTX_TRX_NORMAL,
+   .tenc = UCC_FAST_TX_ENCODING_NRZ,
+   .renc = UCC_FAST_RX_ENCODING_NRZ,
+   .tcrc = UCC_FAST_16_BIT_CRC,
+   .synl = UCC_FAST_SYNC_LEN_NOT_USED,
+   },
+
+   .si_info = {
+#ifdef TDM_PPPOHT_SLIC_MAXIN
+   .simr_rfsd = 1,
+   .simr_tfsd = 2,
+#else
+   .simr_rfsd = 0,
+   .simr_tfsd = 0,
+#endif
+   .simr_crt = 0,
+   .simr_sl = 0,
+   .simr_ce = 1,
+   .simr_fe = 1,
+   .simr_gm = 0,
+   },
+};
+
+static struct ucc_tdm_info utdm_info[MAX_HDLC_NUM];
+
+static int uhdlc_init(struct ucc_hdlc_private *priv)
+{
+   struct ucc_tdm_info *ut_info;
+   

[Patch v3 4/5] fsl/qe: Add QE TDM lib

[Zhao Qiang]

QE has module to support TDM, some other protocols
supported by QE are based on TDM.
add a qe-tdm lib, this lib provides functions to the protocols
using TDM to configurate QE-TDM.

Signed-off-by: Zhao Qiang 
---
Changes for v2:
- delete dead code
- use strcmp instead of strcasecmp
- use of_find_compatible_node instead of of_find_by_name
- use devm_ioremap_resource 
- rename init_si to ucc_tdm_init
- rename of_parse_tdm to ucc_of_parse_tdm
- return err when there is not t1 or e1
Changes for v3:
- na

 drivers/soc/fsl/qe/Kconfig|   6 +-
 drivers/soc/fsl/qe/Makefile   |   1 +
 drivers/soc/fsl/qe/qe_tdm.c   | 276 ++
 include/soc/fsl/qe/immap_qe.h |   5 +-
 include/soc/fsl/qe/qe_tdm.h   |  94 ++
 5 files changed, 377 insertions(+), 5 deletions(-)
 create mode 100644 drivers/soc/fsl/qe/qe_tdm.c
 create mode 100644 include/soc/fsl/qe/qe_tdm.h

diff --git a/drivers/soc/fsl/qe/Kconfig b/drivers/soc/fsl/qe/Kconfig
index 20978f2..73a2e08 100644
--- a/drivers/soc/fsl/qe/Kconfig
+++ b/drivers/soc/fsl/qe/Kconfig
@@ -22,7 +22,7 @@ config UCC_SLOW
 
 config UCC_FAST
bool
-   default y if UCC_GETH
+   default y if UCC_GETH || QE_TDM
help
  This option provides qe_lib support to UCC fast
  protocols: HDLC, Ethernet, ATM, transparent
@@ -31,6 +31,10 @@ config UCC
bool
default y if UCC_FAST || UCC_SLOW
 
+config QE_TDM
+   bool
+   default y if FSL_UCC_HDLC
+
 config QE_USB
bool
default y if USB_FSL_QE
diff --git a/drivers/soc/fsl/qe/Makefile b/drivers/soc/fsl/qe/Makefile
index ffac541..2031d38 100644
--- a/drivers/soc/fsl/qe/Makefile
+++ b/drivers/soc/fsl/qe/Makefile
@@ -6,5 +6,6 @@ obj-$(CONFIG_CPM)   += qe_common.o
 obj-$(CONFIG_UCC)  += ucc.o
 obj-$(CONFIG_UCC_SLOW) += ucc_slow.o
 obj-$(CONFIG_UCC_FAST) += ucc_fast.o
+obj-$(CONFIG_QE_TDM)   += qe_tdm.o
 obj-$(CONFIG_QE_USB)   += usb.o
 obj-$(CONFIG_QE_GPIO)  += gpio.o
diff --git a/drivers/soc/fsl/qe/qe_tdm.c b/drivers/soc/fsl/qe/qe_tdm.c
new file mode 100644
index 000..5e48b14
--- /dev/null
+++ b/drivers/soc/fsl/qe/qe_tdm.c
@@ -0,0 +1,276 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc. All rights reserved.
+ *
+ * Authors:Zhao Qiang 
+ *
+ * Description:
+ * QE TDM API Set - TDM specific routines implementations.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+static int set_tdm_framer(const char *tdm_framer_type)
+{
+   if (strcmp(tdm_framer_type, "e1") == 0)
+   return TDM_FRAMER_E1;
+   else if (strcmp(tdm_framer_type, "t1") == 0)
+   return TDM_FRAMER_T1;
+   else
+   return -EINVAL;
+}
+
+static void set_si_param(struct ucc_tdm *utdm, struct ucc_tdm_info *ut_info)
+{
+   struct si_mode_info *si_info = _info->si_info;
+
+   if (utdm->tdm_mode == TDM_INTERNAL_LOOPBACK) {
+   si_info->simr_crt = 1;
+   si_info->simr_rfsd = 0;
+   }
+}
+
+int ucc_of_parse_tdm(struct device_node *np, struct ucc_tdm *utdm,
+struct ucc_tdm_info *ut_info)
+{
+   const char *sprop;
+   int ret = 0;
+   u32 val;
+   struct resource *res;
+   struct device_node *np2;
+   static int siram_init_flag;
+   struct platform_device *pdev;
+
+   sprop = of_get_property(np, "fsl,rx-sync-clock", NULL);
+   if (sprop) {
+   ut_info->uf_info.rx_sync = qe_clock_source(sprop);
+   if ((ut_info->uf_info.rx_sync < QE_CLK_NONE) ||
+   (ut_info->uf_info.rx_sync > QE_RSYNC_PIN)) {
+   pr_err("QE-TDM: Invalid rx-sync-clock property\n");
+   return -EINVAL;
+   }
+   } else {
+   pr_err("QE-TDM: Invalid rx-sync-clock property\n");
+   return -EINVAL;
+   }
+
+   sprop = of_get_property(np, "fsl,tx-sync-clock", NULL);
+   if (sprop) {
+   ut_info->uf_info.tx_sync = qe_clock_source(sprop);
+   if ((ut_info->uf_info.tx_sync < QE_CLK_NONE) ||
+   (ut_info->uf_info.tx_sync > QE_TSYNC_PIN)) {
+   pr_err("QE-TDM: Invalid tx-sync-clock property\n");
+   return -EINVAL;
+   }
+   } else {
+   pr_err("QE-TDM: Invalid tx-sync-clock property\n");
+   return -EINVAL;
+   }
+
+   ret = of_property_read_u32_index(np, "fsl,tx-timeslot-mask", 0, );
+   if (ret) {
+   pr_err("QE-TDM: Invalid tx-timeslot-mask property\n");
+   return -EINVAL;
+   }
+   

[Patch v3 2/5] fsl/qe: setup clock source for TDM mode

[Zhao Qiang]

Add tdm clock configuration in both qe clock system and ucc
fast controller.

Signed-off-by: Zhao Qiang 
---
Changes for v2:
- break codes getting clock_bits and source to smaller functions.
- add __iomem to qe_mux_reg
- add bits operation functions for qe and use it
- retrun -EINVAL when clock_bits is invalid
Changes for v3:
- adjust some incorrect indentations

 drivers/soc/fsl/qe/ucc.c  | 450 ++
 drivers/soc/fsl/qe/ucc_fast.c |  36 
 include/soc/fsl/qe/qe.h   |  16 ++
 include/soc/fsl/qe/ucc.h  |   4 +
 include/soc/fsl/qe/ucc_fast.h |   1 +
 5 files changed, 507 insertions(+)

diff --git a/drivers/soc/fsl/qe/ucc.c b/drivers/soc/fsl/qe/ucc.c
index b59d335..c646d87 100644
--- a/drivers/soc/fsl/qe/ucc.c
+++ b/drivers/soc/fsl/qe/ucc.c
@@ -25,6 +25,12 @@
 #include 
 #include 
 
+#define UCC_TDM_NUM 8
+#define RX_SYNC_SHIFT_BASE 30
+#define TX_SYNC_SHIFT_BASE 14
+#define RX_CLK_SHIFT_BASE 28
+#define TX_CLK_SHIFT_BASE 12
+
 int ucc_set_qe_mux_mii_mng(unsigned int ucc_num)
 {
unsigned long flags;
@@ -210,3 +216,447 @@ int ucc_set_qe_mux_rxtx(unsigned int ucc_num, enum 
qe_clock clock,
 
return 0;
 }
+
+static int ucc_get_tdm_common_clk(u32 tdm_num, enum qe_clock clock)
+{
+   int clock_bits = -EINVAL;
+
+   /*
+* for TDM[0, 1, 2, 3], TX and RX use  common
+* clock source BRG3,4 and CLK1,2
+* for TDM[4, 5, 6, 7], TX and RX use  common
+* clock source BRG12,13 and CLK23,24
+*/
+   switch (tdm_num) {
+   case 0:
+   case 1:
+   case 2:
+   case 3:
+   switch (clock) {
+   case QE_BRG3:
+   clock_bits = 1;
+   break;
+   case QE_BRG4:
+   clock_bits = 2;
+   break;
+   case QE_CLK1:
+   clock_bits = 4;
+   break;
+   case QE_CLK2:
+   clock_bits = 5;
+   break;
+   default:
+   break;
+   }
+   break;
+   case 4:
+   case 5:
+   case 6:
+   case 7:
+   switch (clock) {
+   case QE_BRG12:
+   clock_bits = 1;
+   break;
+   case QE_BRG13:
+   clock_bits = 2;
+   break;
+   case QE_CLK23:
+   clock_bits = 4;
+   break;
+   case QE_CLK24:
+   clock_bits = 5;
+   break;
+   default:
+   break;
+   }
+   break;
+   default:
+   break;
+   }
+
+   return clock_bits;
+}
+
+static int ucc_get_tdm_rx_clk(u32 tdm_num, enum qe_clock clock)
+{
+   int clock_bits = -EINVAL;
+
+   switch (tdm_num) {
+   case 0:
+   switch (clock) {
+   case QE_CLK3:
+   clock_bits = 6;
+   break;
+   case QE_CLK8:
+   clock_bits = 7;
+   break;
+   default:
+   break;
+   }
+   break;
+   case 1:
+   switch (clock) {
+   case QE_CLK5:
+   clock_bits = 6;
+   break;
+   case QE_CLK10:
+   clock_bits = 7;
+   break;
+   default:
+   break;
+   }
+   break;
+   case 2:
+   switch (clock) {
+   case QE_CLK7:
+   clock_bits = 6;
+   break;
+   case QE_CLK12:
+   clock_bits = 7;
+   break;
+   default:
+   break;
+   }
+   break;
+   case 3:
+   switch (clock) {
+   case QE_CLK9:
+   clock_bits = 6;
+   break;
+   case QE_CLK14:
+   clock_bits = 7;
+   break;
+   default:
+   break;
+   }
+   break;
+   case 4:
+   switch (clock) {
+   case QE_CLK11:
+   clock_bits = 6;
+   break;
+   case QE_CLK16:
+   clock_bits = 7;
+   break;
+   default:
+   break;
+   }
+   break;
+   case 5:
+   switch (clock) {
+   case QE_CLK13:
+   clock_bits = 6;
+   break;
+   case QE_CLK18:
+   clock_bits = 7;
+   

[Patch v3 1/5] fsl/qe: add rx_sync and tx_sync for TDM mode

[Zhao Qiang]

Rx_sync and tx_sync are used by QE-TDM mode,
add them to struct ucc_fast_info.

Signed-off-by: Zhao Qiang 
---
Changes for v2:
- use strcmp instead of strcasecmp
Changes for v3:
- na 

 drivers/soc/fsl/qe/qe.c   | 6 ++
 include/soc/fsl/qe/qe.h   | 2 ++
 include/soc/fsl/qe/ucc_fast.h | 2 ++
 3 files changed, 10 insertions(+)

diff --git a/drivers/soc/fsl/qe/qe.c b/drivers/soc/fsl/qe/qe.c
index 709fc63..7026507 100644
--- a/drivers/soc/fsl/qe/qe.c
+++ b/drivers/soc/fsl/qe/qe.c
@@ -239,6 +239,12 @@ enum qe_clock qe_clock_source(const char *source)
if (strcasecmp(source, "none") == 0)
return QE_CLK_NONE;
 
+   if (strcmp(source, "tsync_pin") == 0)
+   return QE_TSYNC_PIN;
+
+   if (strcmp(source, "rsync_pin") == 0)
+   return QE_RSYNC_PIN;
+
if (strncasecmp(source, "brg", 3) == 0) {
i = simple_strtoul(source + 3, NULL, 10);
if ((i >= 1) && (i <= 16))
diff --git a/include/soc/fsl/qe/qe.h b/include/soc/fsl/qe/qe.h
index 33b29ea..f918745 100644
--- a/include/soc/fsl/qe/qe.h
+++ b/include/soc/fsl/qe/qe.h
@@ -80,6 +80,8 @@ enum qe_clock {
QE_CLK22,   /* Clock 22 */
QE_CLK23,   /* Clock 23 */
QE_CLK24,   /* Clock 24 */
+   QE_RSYNC_PIN,   /* RSYNC from pin */
+   QE_TSYNC_PIN,   /* TSYNC from pin */
QE_CLK_DUMMY
 };
 
diff --git a/include/soc/fsl/qe/ucc_fast.h b/include/soc/fsl/qe/ucc_fast.h
index df8ea79..31548b7 100644
--- a/include/soc/fsl/qe/ucc_fast.h
+++ b/include/soc/fsl/qe/ucc_fast.h
@@ -120,6 +120,8 @@ struct ucc_fast_info {
int ucc_num;
enum qe_clock rx_clock;
enum qe_clock tx_clock;
+   enum qe_clock rx_sync;
+   enum qe_clock tx_sync;
u32 regs;
int irq;
u32 uccm_mask;
-- 
2.1.0.27.g96db324

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