On Wed, Jul 13, 2016 at 03:04:26PM -0700, Kees Cook wrote:
> On Wed, Jul 13, 2016 at 3:01 PM, Andy Lutomirski wrote:
> > On Wed, Jul 13, 2016 at 2:55 PM, Kees Cook wrote:
> >> This creates per-architecture function arch_within_stack_frames() that
> >> should validate if a given object is containe
On 14/07/16 07:17, Ian Munsie wrote:
From: Ian Munsie
The Mellanox CX4 in cxl mode uses a hybrid interrupt model, where
interrupts are routed from the networking hardware to the XSL using the
MSIX table, and from there will be transformed back into an MSIX
interrupt using the cxl style interrup
At the moment VFIO IOMMU SPAPR v2 driver pins all guest RAM pages when
the userspace starts using VFIO. When the userspace process finishes,
all the pinned pages need to be put; this is done as a part of
the userspace memory context (MM) destruction which happens on
the very last mmdrop().
This ap
On Wed, Jul 13, 2016 at 03:05:29PM +0530, Aneesh Kumar K.V wrote:
> We add a tlb flush variant, to flush LPID mappings.
>
> Signed-off-by: Aneesh Kumar K.V
> ---
> .../powerpc/include/asm/book3s/64/tlbflush-radix.h | 4 +-
> arch/powerpc/mm/tlb-radix.c| 52
> +++
On Wed, Jul 13, 2016 at 03:05:31PM +0530, Aneesh Kumar K.V wrote:
> This patch adds the kernel command line disable_radix which disable
> the radix MMU mode even if firmware indicates radix support via
> ibm,pa-features device tree node.
>
> This helps in testing different MMU mode easily.
>
> Si
On Wed, Jul 13, 2016 at 03:05:26PM +0530, Aneesh Kumar K.V wrote:
> ISA 3.0 document hash table size in bytes = 2^(HTABSIZE + 18)
>
> No functionality change by this patch.
>
> Signed-off-by: Aneesh Kumar K.V
> ---
> arch/powerpc/mm/hash_utils_64.c | 9 -
> 1 file changed, 4 insertions(
From: Balbir Singh
Subject: [RESEND][v2][PATCH] KVM: PPC: Book3S HV: Migrate pinned pages out of
CMA
When PCI Device pass-through is enabled via VFIO, KVM-PPC will
pin pages using get_user_pages_fast(). One of the downsides of
the pinning is that the page could be in CMA region. The CMA
region
On Thu, Jul 14, 2016 at 01:11:03PM +1000, Balbir Singh wrote:
>
>
The from address is bad, resending with the right email address
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On Wed, Jul 13, 2016 at 03:05:25PM +0530, Aneesh Kumar K.V wrote:
> This helps in easily identifying the MMU mode with which the kernel
> is operating.
>
> Signed-off-by: Aneesh Kumar K.V
> ---
> arch/powerpc/mm/hash_utils_64.c | 3 ++-
> arch/powerpc/mm/pgtable-radix.c | 3 ++-
> 2 files change
On Wed, Jul 13, 2016 at 03:05:24PM +0530, Aneesh Kumar K.V wrote:
> As per ISA, we need to do this only for architecture version 2.02 and
> earlier. This continued to work even for 2.07. But let's not do this for
> anything after 2.02. ISA 3.0 requires these top bits to be not cleared.
>
> Signed-
On Wed, Jul 13, 2016 at 03:05:22PM +0530, Aneesh Kumar K.V wrote:
> This switch few of the page table accessor to use the __raw variant
^^ switches ^^ accessors
> and does the cpu to big endian conversion of constants. This helps in
> generating better code.
>
> For ex: a
On Wed, Jul 13, 2016 at 03:54:59PM +1000, Alastair D'Silva wrote:
> On Wed, 2016-07-13 at 15:47 +1000, alast...@au1.ibm.com wrote:
> > From: Alastair D'Silva
> > > This series allows the vmx_crypto module to be detected and
> > automatically
> > loaded via UDEV if the CPU supports the vector crypt
On Wed, Jul 13, 2016 at 03:05:21PM +0530, Aneesh Kumar K.V wrote:
> PowerISA 3.0 requires the MMU mode (radix vs. hash) of the hypervisor
> to be mirrored in the LPCR register, in addition to the partition table.
> This is done to avoid fetching from the table when deciding, among other
> things, h
On 07/05/2016 07:25 AM, Michael Ellerman wrote:
> Anshuman Khandual writes:
>
>> For partition running on PHYP, there can be a adjunct partition
>> which shares the virtual address range with the operating system.
>> Virtual address ranges which can be used by the adjunct partition
>> are communi
> "Andrew" == Andrew Donnellan writes:
>> This patch straddles a few subsystems. Did you intend for me to queue
>> it through SCSI?
Andrew> Sorry for not stating explicitly - I'd like this taken through
Andrew> powerpc as the cxlflash change is incidental to the cxl changes.
No problem.
--
Am Mittwoch, 13 Juli 2016, 21:59:18 schrieb Arnd Bergmann:
> On Wednesday, July 13, 2016 3:45:41 PM CEST Thiago Jung Bauermann wrote:
> > Am Mittwoch, 13 Juli 2016, 15:13:42 schrieb Arnd Bergmann:
> > > On Wednesday, July 13, 2016 10:41:28 AM CEST Mark Rutland wrote:
> > > > On Wed, Jul 13, 2016 at
On 14/07/16 12:05, Andrew Donnellan wrote:
Sorry for not stating explicitly - I'd like this taken through powerpc
as the cxlflash change is incidental to the cxl changes.
I'll also be submitting a v2 that applies on top of another cxl series
that hasn't been merged yet.
--
Andrew Donnellan
On 14/07/16 12:02, Martin K. Petersen wrote:
"Andrew" == Andrew Donnellan writes:
Andrew> Remove the CXL_KERNEL_API and CXL_EEH Kconfig options, as they
Andrew> were only needed to coordinate the merging of the cxlflash
Andrew> driver. Also remove the stub implementation of
Andrew> cxl_perst_r
> "Andrew" == Andrew Donnellan writes:
Andrew> Remove the CXL_KERNEL_API and CXL_EEH Kconfig options, as they
Andrew> were only needed to coordinate the merging of the cxlflash
Andrew> driver. Also remove the stub implementation of
Andrew> cxl_perst_reloads_same_image() in cxlflash which is o
On 07/14/16 at 02:38am, AKASHI Takahiro wrote:
> Apologies for the slow response. I'm attending LinuxCon this week.
>
> On Wed, Jul 13, 2016 at 10:34:47AM +0100, Mark Rutland wrote:
> > On Wed, Jul 13, 2016 at 10:36:14AM +0800, Dave Young wrote:
> > > But consider we can kexec to a different kerne
On 07/13/16 at 10:34am, Mark Rutland wrote:
> On Wed, Jul 13, 2016 at 10:36:14AM +0800, Dave Young wrote:
> > But consider we can kexec to a different kernel and a different initrd so
> > there
> > will be use cases to pass a total different dtb as well.
>
> It depends on what you mean by "a diff
On Wed, 2016-07-13 at 13:15 +0300, Dan Carpenter wrote:
> Hello Benjamin Herrenschmidt,
>
> The patch ac171c46667c: "[PATCH] powerpc: Thermal control for dual
> core G5s" from Feb 8, 2006, leads to the following static checker
> warning:
>
> drivers/macintosh/windfarm_smu_controls.c:83 smu_
On Wed, Jul 13, 2016 at 3:01 PM, Andy Lutomirski wrote:
> On Wed, Jul 13, 2016 at 2:55 PM, Kees Cook wrote:
>> This creates per-architecture function arch_within_stack_frames() that
>> should validate if a given object is contained by a kernel stack frame.
>> Initial implementation is on x86.
>>
On Wed, Jul 13, 2016 at 2:55 PM, Kees Cook wrote:
> This creates per-architecture function arch_within_stack_frames() that
> should validate if a given object is contained by a kernel stack frame.
> Initial implementation is on x86.
>
> This is based on code from PaX.
>
This, along with Josh's li
Under CONFIG_HARDENED_USERCOPY, this adds object size checking to the
SLUB allocator to catch any copies that may span objects. Includes a
redzone handling fix from Michael Ellerman.
Based on code from PaX and grsecurity.
Signed-off-by: Kees Cook
---
init/Kconfig | 1 +
mm/slub.c| 36 +
Under CONFIG_HARDENED_USERCOPY, this adds object size checking to the
SLAB allocator to catch any copies that may span objects.
Based on code from PaX and grsecurity.
Signed-off-by: Kees Cook
---
init/Kconfig | 1 +
mm/slab.c| 30 ++
2 files changed, 31 insertio
Enables CONFIG_HARDENED_USERCOPY checks on s390.
Signed-off-by: Kees Cook
---
arch/s390/Kconfig | 1 +
arch/s390/lib/uaccess.c | 2 ++
2 files changed, 3 insertions(+)
diff --git a/arch/s390/Kconfig b/arch/s390/Kconfig
index a8c259059adf..9f694311c9ed 100644
--- a/arch/s390/Kconfig
+++ b/
Enables CONFIG_HARDENED_USERCOPY checks on sparc.
Based on code from PaX and grsecurity.
Signed-off-by: Kees Cook
---
arch/sparc/Kconfig | 1 +
arch/sparc/include/asm/uaccess_32.h | 14 ++
arch/sparc/include/asm/uaccess_64.h | 11 +--
3 files changed, 20 in
Enables CONFIG_HARDENED_USERCOPY checks on powerpc.
Based on code from PaX and grsecurity.
Signed-off-by: Kees Cook
---
arch/powerpc/Kconfig | 1 +
arch/powerpc/include/asm/uaccess.h | 21 +++--
2 files changed, 20 insertions(+), 2 deletions(-)
diff --git a/arch/
Enables CONFIG_HARDENED_USERCOPY checks on ia64.
Based on code from PaX and grsecurity.
Signed-off-by: Kees Cook
---
arch/ia64/Kconfig | 1 +
arch/ia64/include/asm/uaccess.h | 18 +++---
2 files changed, 16 insertions(+), 3 deletions(-)
diff --git a/arch/ia64/Kconfig
Enables CONFIG_HARDENED_USERCOPY checks on arm64. As done by KASAN in -next,
renames the low-level functions to __arch_copy_*_user() so a static inline
can do additional work before the copy.
Signed-off-by: Kees Cook
---
arch/arm64/Kconfig | 2 ++
arch/arm64/include/asm/uaccess.h
This creates per-architecture function arch_within_stack_frames() that
should validate if a given object is contained by a kernel stack frame.
Initial implementation is on x86.
This is based on code from PaX.
Signed-off-by: Kees Cook
---
arch/Kconfig | 9
arch/x8
Enables CONFIG_HARDENED_USERCOPY checks on arm.
Based on code from PaX and grsecurity.
Signed-off-by: Kees Cook
---
arch/arm/Kconfig | 1 +
arch/arm/include/asm/uaccess.h | 11 +--
2 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm
This is the start of porting PAX_USERCOPY into the mainline kernel. This
is the first set of features, controlled by CONFIG_HARDENED_USERCOPY. The
work is based on code by PaX Team and Brad Spengler, and an earlier port
from Casey Schaufler. Additional non-slab page tests are from Rik van Riel.
Th
Enables CONFIG_HARDENED_USERCOPY checks on x86. This is done both in
copy_*_user() and __copy_*_user() because copy_*_user() actually calls
down to _copy_*_user() and not __copy_*_user().
Based on code from PaX and grsecurity.
Signed-off-by: Kees Cook
---
arch/x86/Kconfig | 2
Hi,
This is a start of the mainline port of PAX_USERCOPY[1]. After I started
writing tests (now in lkdtm in -next) for Casey's earlier port[2], I
kept tweaking things further and further until I ended up with a whole
new patch series. To that end, I took Rik's feedback and made a number
of other c
Acked-by: Ian Munsie
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From: Andrew Donnellan
Add a new API, cxl_check_and_switch_mode() to allow for switching of
bi-modal CAPI cards, such as the Mellanox CX-4 network card.
When a driver requests to switch a card to CAPI mode, use PCI hotplug
infrastructure to remove all PCI devices underneath the slot. We then wri
From: Andrew Donnellan
When calling pnv_php_set_slot_power_state() with state ==
OPAL_PCI_SLOT_OFFLINE, remove devices from the device tree as if we're
dealing with OPAL_PCI_SLOT_POWER_OFF.
Cc: Gavin Shan
Cc: linux-...@vger.kernel.org
Cc: Bjorn Helgaas
Signed-off-by: Andrew Donnellan
Signed-o
From: Andrew Donnellan
The cxl driver will use infrastructure from pnv_php to handle device tree
updates when switching bi-modal CAPI cards into CAPI mode.
To enable this, export pnv_php_find_slot() and
pnv_php_set_slot_power_state(), and add corresponding declarations, as well
as the definition
From: Ian Munsie
The Mellanox CX4 in cxl mode uses a hybrid interrupt model, where
interrupts are routed from the networking hardware to the XSL using the
MSIX table, and from there will be transformed back into an MSIX
interrupt using the cxl style interrupts (i.e. using IVTE entries and
ranges
From: Ian Munsie
The CX4 card cannot cope with a context with PE=0 due to a hardware
limitation, resulting in:
[ 34.166577] command failed, status limits exceeded(0x8), syndrome 0x5a7939
[ 34.166580] mlx5_core :01:00.1: Failed allocating uar, aborting
Since the kernel API allocates a de
From: Ian Munsie
The Mellanox CX4 has a hardware limitation where only 4 bits of the
AFU interrupt number can be passed to the XSL when sending an interrupt,
limiting it to only 15 interrupts per context (AFU interrupt number 0 is
invalid).
In order to overcome this, we will allocate additional
From: Ian Munsie
These APIs will be used by the Mellanox CX4 support. While they function
standalone to configure existing behaviour, their primary purpose is to
allow the Mellanox driver to inform the cxl driver of a hardware
limitation, which will be used in a future patch.
Signed-off-by: Ian
From: Ian Munsie
This hooks up support for using the kernel API with a real PHB. After
the AFU initialisation has completed it calls into the PHB code to pass
it the AFU that will be used by other peer physical functions on the
adapter.
The cxl_pci_to_afu API is extended to work with peer PCI de
From: Ian Munsie
This adds support for the peer model of the cxl kernel api to the
PowerNV PHB, in which physical function 0 represents the cxl function on
the card (an XSL in the case of the CX4), which other physical functions
will use for memory access and interrupt services. It is referred to
From: Ian Munsie
The vPHB model of the cxl kernel API is a hierarchy where the AFU is
represented by the vPHB, and it's AFU configuration records are exposed
as functions under that vPHB. If there are no AFU configuration records
we will create a vPHB with nothing under it, which is a waste of
re
From: Ian Munsie
The cxl kernel API has a concept of a default context associated with
each PCI device under the virtual PHB. The Mellanox CX4 will also use
the cxl kernel API, but it does not use a virtual PHB - rather, the AFU
appears as a physical function as a peer to the networking functions
From: Ian Munsie
Devices that use CAPP DMA mode (such as the Mellanox CX4) require bus
master to be enabled in order for the CAPI traffic to flow. This should
be harmless to enable for other cxl devices, so unconditionally enable
it in the adapter init flow.
Signed-off-by: Ian Munsie
Reviewed-b
From: Ian Munsie
The Mellanox CX4 uses a model where the AFU is one physical function of
the device, and is used by other peer physical functions of the same
device. This will require those other devices to grab a reference on the
AFU when they are initialised to make sure that it does not go awa
From: Ian Munsie
This extends the check that the adapter is in a CAPI capable slot so
that it may be called by external users in the kernel API. This will be
used by the upcoming Mellanox CX4 support, which needs to know ahead of
time if the card can be switched to cxl mode so that it can leave i
From: Ian Munsie
The support for using the Mellanox CX4 in cxl mode will require
additions to the PHB code. In preparation for this, move the existing
cxl code out of pci-ioda.c into a separate pci-cxl.c file to keep things
more organised.
Signed-off-by: Ian Munsie
Reviewed-by: Andrew Donnellan
This series adds support for the Mellanox CX4 network adapter operating in cxl
mode to the cxl driver and the PowerNV PHB code. The Mellanox developers will
submit a separate patch series that makes use of this in the mlx5 driver.
The CX4 card can operate in either pci mode, or cxl mode. In cxl mo
Excerpts from andrew.donnellan's message of 2016-07-13 15:52:45 +1000:
> > +bool _cxl_pci_associate_default_context(struct pci_dev *dev, struct
> > cxl_afu *afu)
>
> If we're sharing these functions between the vPHB and peer models, do we
> have a better place than vphb.c for them?
Sure, I migh
On 06/30/2016 04:44 PM, Michael Bringmann wrote:
> Several properties in the DRC device tree format are replaced by
> more compact representations to allow, for example, for the encoding
> of vast amounts of memory, and or reduced duplication of information
> in related data structures.
>
> "ibm,d
Excerpts from andrew.donnellan's message of 2016-07-12 20:39:13 +1000:
> Some comments below - with those addressed:
>
> Reviewed-by: Andrew Donnellan
Thanks for the review :)
> > V1->V2:
> > - Add an explanation of the peer model to the commit message,
> > and a comment above the pnv
On Wednesday, July 13, 2016 3:45:41 PM CEST Thiago Jung Bauermann wrote:
> Am Mittwoch, 13 Juli 2016, 15:13:42 schrieb Arnd Bergmann:
> > On Wednesday, July 13, 2016 10:41:28 AM CEST Mark Rutland wrote:
> > > On Wed, Jul 13, 2016 at 10:01:33AM +0200, Arnd Bergmann wrote:
> > > > - kboot/petitboot w
On Wednesday, July 13, 2016 6:58:32 PM CEST Mark Rutland wrote:
>
> > we may want to remove unnecessary devices and even add a dedicated
> > storage device for storing a core dump image.
>
> I suspect that bringing up a minimal number of devices is better
> controlled by a cmdline option. In
Am Mittwoch, 13 Juli 2016, 15:13:42 schrieb Arnd Bergmann:
> On Wednesday, July 13, 2016 10:41:28 AM CEST Mark Rutland wrote:
> > On Wed, Jul 13, 2016 at 10:01:33AM +0200, Arnd Bergmann wrote:
> > > - kboot/petitboot with all of the user space being part of the trusted
> > > boot> >
> > > chain:
On Wed, Jul 13, 2016 at 06:40:10PM +0100, Russell King - ARM Linux wrote:
> On Wed, Jul 13, 2016 at 09:03:38AM -0400, Vivek Goyal wrote:
> > On Wed, Jul 13, 2016 at 09:26:39AM +0100, Russell King - ARM Linux wrote:
> > > Indeed - maybe Eric knows better, but I can't see any situation where
> > > th
On 07/11/2016 09:31 PM, Paolo Bonzini wrote:
>
>
> On 11/07/2016 19:30, David Matlack wrote:
>> On Mon, Jul 11, 2016 at 10:05 AM, Paolo Bonzini wrote:
>>>
>>>
>>> On 11/07/2016 18:51, David Matlack wrote:
>> vcpus have statistics associated with them which can be viewed within the
>> deb
On Thu, Jul 14, 2016 at 02:38:06AM +0900, AKASHI Takahiro wrote:
> Apologies for the slow response. I'm attending LinuxCon this week.
>
> On Wed, Jul 13, 2016 at 10:34:47AM +0100, Mark Rutland wrote:
> > On Wed, Jul 13, 2016 at 10:36:14AM +0800, Dave Young wrote:
> > > But consider we can kexec to
On Wed, Jul 13, 2016 at 09:03:38AM -0400, Vivek Goyal wrote:
> On Wed, Jul 13, 2016 at 09:26:39AM +0100, Russell King - ARM Linux wrote:
> > Indeed - maybe Eric knows better, but I can't see any situation where
> > the dtb we load via kexec should ever affect "the bootloader", unless
> > the "kerne
Apologies for the slow response. I'm attending LinuxCon this week.
On Wed, Jul 13, 2016 at 10:34:47AM +0100, Mark Rutland wrote:
> On Wed, Jul 13, 2016 at 10:36:14AM +0800, Dave Young wrote:
> > But consider we can kexec to a different kernel and a different initrd so
> > there
> > will be use ca
On Tue, Jul 12, 2016 at 11:07 PM, Suraj Jitindar Singh
wrote:
> On 12/07/16 16:17, Suraj Jitindar Singh wrote:
>> On 12/07/16 02:49, David Matlack wrote:
[snip]
>>> It's possible to poll and wait in one halt, conflating this stat with
>>> polling time. Is it useful to split out a third stat,
>>> h
From: Sebastian Andrzej Siewior
Install the callbacks via the state machine and let the core invoke
the callbacks on the already online CPUs.
Signed-off-by: Sebastian Andrzej Siewior
Cc: Andrew Morton
Cc: Benjamin Herrenschmidt
Cc: Bharata B Rao
Cc: Christophe Jaillet
Cc: Linus Torvalds
Cc
From: Thomas Gleixner
Install the callbacks via the state machine and let the core invoke
the callbacks on the already online CPUs.
Signed-off-by: Thomas Gleixner
Reviewed-by: Sebastian Andrzej Siewior
Cc: Anshuman Khandual
Cc: Benjamin Herrenschmidt
Cc: Linus Torvalds
Cc: Madhavan Srinivas
Thu, Jul 14, 2016 at 01:11:58AM +1000, Stephen Rothwell wrote:
> Hi Paulo,
>
> On Wed, 13 Jul 2016 10:34:27 -0300 Paulo Flabiano Smorigo
> wrote:
> >
> > Wed, Jul 13, 2016 at 01:05:03PM +1000, Stewart Smith wrote:
> > > Stephen Rothwell writes:
> > > > On Mon, 11 Jul 2016 16:07:39 -0300 Paulo
Hi Paulo,
On Wed, 13 Jul 2016 10:34:27 -0300 Paulo Flabiano Smorigo
wrote:
>
> Wed, Jul 13, 2016 at 01:05:03PM +1000, Stewart Smith wrote:
> > Stephen Rothwell writes:
> > > On Mon, 11 Jul 2016 16:07:39 -0300 Paulo Flabiano Smorigo
> > > wrote:
> > >>
> > >> diff --git a/drivers/crypto/vm
On Wed, 2016-07-13 at 19:36 +0530, Aneesh Kumar K.V wrote:
> > I'm not sure about that. This is converting way way way way more
> > functions than is needed. Especially if Michael applies my series
> > there will be very little code run before the patching, really only
> the
> > MMU initialization.
Hello Markos Chandras,
The patch c6610de353da: "MIPS: net: Add BPF JIT" from Apr 8, 2014,
leads to the following static checker warning:
arch/mips/net/bpf_jit.c:1185 build_body()
warn: potential off by one 'ctx->offsets[]' limit 'prog->len'
arch/mips/net/bpf_jit.c
652 static
Benjamin Herrenschmidt writes:
> On Wed, 2016-07-13 at 15:08 +0530, Aneesh Kumar K.V wrote:
>> This switch most of the early feature check to use the non static key
>> variant of the function. In later patches we will be switching
>> cpu_has_feature and mmu_has_feature to use static keys and we c
Benjamin Herrenschmidt writes:
> On Wed, 2016-07-13 at 15:10 +0530, Aneesh Kumar K.V wrote:
>> Hi,
>>
>> This series add support for ISA 3.0 memory segment table.
>>
>> Aneesh Kumar K.V (2):
>> powerpc/mm: Switch user slb fault handling to translation enabled
>> powerpc/mm: Support segment
Benjamin Herrenschmidt writes:
> On Wed, 2016-07-13 at 15:08 +0530, Aneesh Kumar K.V wrote:
>> This switch most of the early feature check to use the non static key
>> variant of the function. In later patches we will be switching
>> cpu_has_feature and mmu_has_feature to use static keys and we c
On 07/12/2016 08:07 PM, Mauricio Faria de Oliveira wrote:
Can you clarify which are the devices that should be tracked w/ krefs to
the PHB?
Last night I had forgotten about the fundamental point of krefs - track
references to pointers - and this answers the question.
I'm looking at the holde
Wed, Jul 13, 2016 at 01:05:03PM +1000, Stewart Smith wrote:
> Stephen Rothwell writes:
> > On Mon, 11 Jul 2016 16:07:39 -0300 Paulo Flabiano Smorigo
> > wrote:
> >>
> >> diff --git a/drivers/crypto/vmx/aesp8-ppc.pl
> >> b/drivers/crypto/vmx/aesp8-ppc.pl
> >> index 2280539..813ffcc 100644
> >> -
On Wed, Jul 13, 2016 at 09:45:22AM +1000, Stewart Smith wrote:
> Vivek Goyal writes:
> > On Tue, Jul 12, 2016 at 10:58:09AM -0300, Thiago Jung Bauermann wrote:
> >> Hello Eric,
> >>
> >> Am Dienstag, 12 Juli 2016, 08:25:48 schrieb Eric W. Biederman:
> >> > AKASHI Takahiro writes:
> >> > > Device
On Wed, Jul 13, 2016 at 09:41:39AM +1000, Stewart Smith wrote:
> Petr Tesarik writes:
> > On Tue, 12 Jul 2016 13:25:11 -0300
> > Thiago Jung Bauermann wrote:
> >
> >> Hi Eric,
> >>
> >> I'm trying to understand your concerns leading to your nack. I hope you
> >> don't mind expanding your though
On Wednesday, July 13, 2016 10:41:28 AM CEST Mark Rutland wrote:
> On Wed, Jul 13, 2016 at 10:01:33AM +0200, Arnd Bergmann wrote:
> > On Wednesday, July 13, 2016 10:36:14 AM CEST Dave Young wrote:
> > > On 07/12/16 at 03:50pm, Mark Rutland wrote:
> > > > On Tue, Jul 12, 2016 at 04:24:10PM +0200, Ar
On Wed, Jul 13, 2016 at 09:26:39AM +0100, Russell King - ARM Linux wrote:
> On Wed, Jul 13, 2016 at 05:55:33PM +1000, Stewart Smith wrote:
> > Russell King - ARM Linux writes:
> > > On Wed, Jul 13, 2016 at 02:59:51PM +1000, Stewart Smith wrote:
> > >> Russell King - ARM Linux writes:
> > >> > On
On Wed, 2016-07-13 at 15:08 +0530, Aneesh Kumar K.V wrote:
> This switch most of the early feature check to use the non static key
> variant of the function. In later patches we will be switching
> cpu_has_feature and mmu_has_feature to use static keys and we can use
> them only after static key/ju
On Wed, 2016-07-13 at 15:10 +0530, Aneesh Kumar K.V wrote:
> Hi,
>
> This series add support for ISA 3.0 memory segment table.
>
> Aneesh Kumar K.V (2):
> powerpc/mm: Switch user slb fault handling to translation enabled
> powerpc/mm: Support segment table for Power9
The segment table will o
Hello Christophe Lombard,
The patch 4752876c7170: "cxl: sysfs support for guests" from Mar 4,
2016, leads to the following static checker warning:
drivers/misc/cxl/sysfs.c:681 cxl_sysfs_afu_add()
warn: if statement not indented
drivers/misc/cxl/sysfs.c
672 err1:
673
Hello Benjamin Herrenschmidt,
The patch ac171c46667c: "[PATCH] powerpc: Thermal control for dual
core G5s" from Feb 8, 2006, leads to the following static checker
warning:
drivers/macintosh/windfarm_smu_controls.c:83 smu_set_fan()
warn: buffer overflow 'buffer' 16 <= 16
drivers/m
The udc->eps[] array has USB_MAX_ENDPOINTS elements so > should be >=.
Fixes: 3948f0e0c999 ('usb: add Freescale QE/CPM USB peripheral controller
driver')
Signed-off-by: Dan Carpenter
diff --git a/drivers/usb/gadget/udc/fsl_qe_udc.c
b/drivers/usb/gadget/udc/fsl_qe_udc.c
index 93d28cb..cf8819a 1
Arnaldo, Michael,
I've tested this patchset on ppc64 BE and LE both. Please review this.
-Ravi
On Friday 08 July 2016 10:10 AM, Ravi Bangoria wrote:
Perf can currently only support code navigation (branches and calls) in
annotate when run on the same architecture where perf.data was recorded.
On Wed, Jul 13, 2016 at 10:01:33AM +0200, Arnd Bergmann wrote:
> On Wednesday, July 13, 2016 10:36:14 AM CEST Dave Young wrote:
> > On 07/12/16 at 03:50pm, Mark Rutland wrote:
> > > On Tue, Jul 12, 2016 at 04:24:10PM +0200, Arnd Bergmann wrote:
> > > > On Tuesday, July 12, 2016 10:18:11 AM CEST Viv
PowerISA 3.0 adds an in memory table for storing segment translation
information. In this mode, which is enabled by setting both HOST RADIX
and GUEST RADIX bits in partition table to 0 and enabling UPRT to
1, we have a per process segment table. The segment table details
are stored in the process t
We also handle fault with proper stack initialized. This enable us to
callout to C in fault handling routines. We don't do this for kernel
mapping, because of the possibility of taking recursive fault if kernel
stack in not yet mapped by an slb entry.
This enable us to handle Power9 slb fault bett
Hi,
This series add support for ISA 3.0 memory segment table.
Aneesh Kumar K.V (2):
powerpc/mm: Switch user slb fault handling to translation enabled
powerpc/mm: Support segment table for Power9
Documentation/kernel-parameters.txt | 3 +
arch/powerpc/include/asm/book3s/64/hash.h
This enable us to catch the wrong usage of cpu_has_feature and
mmu_has_feature in the code. We need to use the feature bit based
check in show_regs because that is used in the reporting code.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/Kconfig.debug | 11 +++
arch/powerp
From: Kevin Hao
The mmu features are fixed once the probe of mmu features are done.
And the function mmu_has_feature() does be used in some hot path.
The checking of the mmu features for each time of invoking of
mmu_has_feature() seems suboptimal. This tries to reduce this
overhead of this check
From: Kevin Hao
The cpu features are fixed once the probe of cpu features are done.
And the function cpu_has_feature() does be used in some hot path.
The checking of the cpu features for each time of invoking of
cpu_has_feature() seems suboptimal. This tries to reduce this
overhead of this check
From: Kevin Hao
We plan to use jump label for cpu_has_feature. In order to implement
this we need to include the linux/jump_label.h in asm/cputable.h.
But it seems that asm/cputable.h is so basic header file for ppc that
it is almost included by all the other header files. The including of
the li
From: Kevin Hao
This function is only used by get_vtb(). They are almost the same
except the reading from the real register. Move the mfspr() to
get_vtb() and kill the function mfvtb(). With this, we can eliminate
the use of cpu_has_feature() in very core header file like reg.h.
This is a prepara
Call jump_label_init early so that can use static keys for cpu and
mmu feature check. We should have finalzed all the cpu/mmu features when
we call setup_system and we also did feature fixup for ASM based code.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/kernel/setup_32.c | 6 ++
arch/p
From: Kevin Hao
For some archs (such as powerpc) would want to invoke jump_label_init()
in a much earlier stage. So check static_key_initialized in order to
make sure this function run only once.
Signed-off-by: Kevin Hao
Signed-off-by: Aneesh Kumar K.V
---
Ingo did ack this patch in email
htt
We want to use the static key based feature check in set_pte_at. Since
we call radix__map_kernel_page early in boot before jump label is
initialized we can't call set_pte_at there. Add radix__set_pte for the
same.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/mm/pgtable-radix.c | 23 +
This switch most of the early feature check to use the non static key
variant of the function. In later patches we will be switching
cpu_has_feature and mmu_has_feature to use static keys and we can use
them only after static key/jump label is initialized. Any check for
feature before jump label in
In later patches, we will be switching cpu and mmu feature check to
use static keys. This would require us to have a variant of feature
check that can be used in early boot before jump label is initialized.
This patch adds the same. We also add a variant for radix_enabled()
check
We also update th
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