[PATCH] perf annotate: cross arch annotate support fixes for ARM

For ARM we remove the list that contains non-arm insns, and instead add more maintainable branch instruction regex logic. Signed-off-by: Kim Phillips Acked-by: Ravi Bangoria Cc: Namhyung Kim --- tools/perf/util/annotate.c | 177 + 1 file changed, 67

[PATCH 3/3] powerpc/pseries: Add bitmap to track updated LMBs

Recent updates to the PAPR for memory hotplug has now made the reserved field of the ibm,dynamic-memory property a capabilities field. To support this update we can no longer use the reserved field to track which LMBs have been updated during a DLPAR operation. This patch adds a bitfield to track

[PATCH 2/3] powerpc/pseries: Remove no longer needed rtas_hp_event flag

Remove the use of the rtas_hp_event flag as it is no longer needed. the managememnet of the static dynamic-memory property does not go through of_update_property so we do not need to set this flag. Signed-off-by: Nathan Fontenot --- arch/powerpc/platforms/pseries/hotplug-memory.c |5 - 1

[PATCH 1/3] powerpc/pseries: maintain single copy of ibm, dynamic-memory property

The ibm,dynamic-reconfiguration-memory/ibm,dynamic-memory property of the device-tree can be fairly big on systems with a large amount of memory. A system with 1 TB of memory (256 MB LMBs) the property size is 94k, this equates to roughly a 30MB property size for a 32 TB system. This file size is n

[PATCH 0/3] powerpc/pseries: Manage single copy of ibm, dynamic-memory

The ibm,dynamic-reconfiguration-memory/ibm,dynamic-memory property of the device-tree can be fairly big on systems with a large amount of memory. A system with 1 TB of memory (256 MB LMBs) the property size is 94k, this equates to roughly a 30MB property size for a 32 TB system. This file size is n

[PATCH] powerpc/32: fix again csum_partial_copy_generic()

commit 7aef4136566b0 ("powerpc32: rewrite csum_partial_copy_generic() based on copy_tofrom_user()") introduced a bug when destination address is odd and len is lower than cacheline size. In that case the resulting csum value doesn't have to be rotated one byte because the cache-aligned copy part i

Re: Suspected regression?

Hi Christophe, On 26 August 2016 at 14:46, Christophe Leroy wrote: [...] > Can you try the patch below ? I have identified that in case the packet is > smaller than a cacheline, it doesn't get cache-aligned so the result shall > not be rotated in case of odd dest address. > > This patch goes in a

Re: Suspected regression?

Hi Alessio, Le 26/08/2016 à 04:32, Scott Wood a écrit : On Tue, 2016-08-23 at 13:34 +0200, Christophe Leroy wrote: Le 23/08/2016 à 11:20, Alessio Igor Bogani a écrit : Hi Christophe, Sorry for delay in reply I was on vacation. On 6 August 2016 at 11:29, christophe leroy wrote: Alessio,

Re: [PATCH v6 2/7] perf annotate: Add cross arch annotate support

Hi Kim, I've tested your patch on x86 and powerpc and it looks fine to me. Can you please put your signed-off-by. Please add Act-by: Ravi Bangoria as well. Regards, -Ravi On Wednesday 24 August 2016 02:06 AM, Kim Phillips wrote: > On Tue, 23 Aug 2016 11:17:16 +0900 > Namhyung Kim wrote: > >>

Re: [PATCH] powerpc/fsl_pci: Size upper inbound window based on RAM size

Hi Scott, thanks for the patch! This one works for my setup: T4240, 12GB Ram and Radeon E6760. On 2016-08-26 08:38, Scott Wood wrote: This allows PCI devices that can only address (e.g.) 36 or 40 bit DMA to use direct DMA, at the cost of not being able to DMA to non-RAM addresses (this doesn'