Le 10/01/2017 à 03:11, Christian Kujau a écrit :
On Wed, 4 Jan 2017, Christian Kujau wrote:
So, would the following be sufficient? It compiles, but I haven't had a
chance to boot yet.
So, with -fno-stack-protector my GCC 4.9.2 compiles with
CC_STACKPROTECTOR_STRONG=y but panics during boot:
Le 10/01/2017 à 05:32, Benjamin Herrenschmidt a écrit :
On Mon, 2017-01-09 at 18:11 -0800, Christian Kujau wrote:
So, with -fno-stack-protector my GCC 4.9.2 compiles with
CC_STACKPROTECTOR_STRONG=y but panics during boot:
How can it make any sense to have -fno-stack-protector and
CC_STACKPRO
On Mon, 9 Jan 2017 19:06:18 +0530
Madhavan Srinivasan wrote:
> Rename the paca->soft_enabled to paca->soft_disabled_mask as
> it is no more used as a flag for interrupt state.
>
> Signed-off-by: Madhavan Srinivasan
Reviewed-by: Nicholas Piggin
> -static inline notrace void soft_enabled_set(
On Mon, 9 Jan 2017 19:06:15 +0530
Madhavan Srinivasan wrote:
> New Kconfig is added "CONFIG_IRQ_DEBUG_SUPPORT" to add warn_on
> to alert the invalid transitions. Also moved the code under
> the CONFIG_TRACE_IRQFLAGS in arch_local_irq_restore() to new Kconfig.
>
> Signed-off-by: Madhavan Sriniva
On Mon, 9 Jan 2017 19:06:11 +0530
Madhavan Srinivasan wrote:
> "paca->soft_enabled" is used as a flag to mask some of interrupts.
> Currently supported flags values and their details:
>
> soft_enabledMSR[EE]
>
> 0 0 Disabled (PMI and HMI not masked)
> 1 1
On Mon, 9 Jan 2017 19:06:09 +0530
Madhavan Srinivasan wrote:
> Force use of soft_enabled_set() wrapper to update paca-soft_enabled
> wherever possisble. Also add a new wrapper function,
> soft_enabled_set_return(),
> added to force the paca->soft_enabled updates.
>
> Signed-off-by: Madhavan Sr
On Monday, January 09, 2017 04:42:58 PM Jeff Moyer wrote:
> Commit 20ce44d545844 ("do_direct_IO: Use inode->i_blkbits to compute
> block count to be cleaned") introduced a regression: if the block size
> of the block device is changed while a direct I/O request is being
> setup, it can result in a
On 10/01/17 16:00, Martin K. Petersen wrote:
The first three patches in the series were submitted by you but do not
carry your Signed-off-by:...
hmm, over in linuxppc-land I don't think we particularly enforce this.
Thanks for the reminder!
--
Andrew Donnellan OzLabs, ADL Canber
> "Uma" == Uma Krishnan writes:
Uma,
Uma> This patch series includes an enhancement to support a new command
Uma> queuing model and also cleans up prints throughout the driver. The
Uma> last patch in the series fixes a racing issue.
Uma> The series is based upon v4.10-rc2, intended for 4.11
Add detection of NPU2 PHBs. NPU2/NVLink2 has a different register
layout for the TCE kill register therefore TCE invalidation should be
done via the OPAL call rather than using the register directly as it
is for PHB3 and NVLink1. This changes TCE invalidation to use the OPAL
call in the case of a N
On Mon, 2017-01-09 at 18:11 -0800, Christian Kujau wrote:
> So, with -fno-stack-protector my GCC 4.9.2 compiles with
> CC_STACKPROTECTOR_STRONG=y but panics during boot:
How can it make any sense to have -fno-stack-protector and
CC_STACKPROTECTOR_STRONG=y at the same time ?
Ben.
On Mon, Jan 09, 2017 at 05:10:35PM +0530, Aravinda Prasad wrote:
> This patch introduces a new KVM capability to control
> how KVM behaves on machine check exception (MCE).
> Without this capability, KVM redirects machine check
> exceptions to guest's 0x200 vector, if the address in
> error belongs
On Wed, 4 Jan 2017, Christian Kujau wrote:
> So, would the following be sufficient? It compiles, but I haven't had a
> chance to boot yet.
>
So, with -fno-stack-protector my GCC 4.9.2 compiles with
CC_STACKPROTECTOR_STRONG=y but panics during boot:
Kernel panic - not syncing: stack-protector:
On 01/09/2017 02:42 PM, Jeff Moyer wrote:
> Commit 20ce44d545844 ("do_direct_IO: Use inode->i_blkbits to compute
> block count to be cleaned") introduced a regression: if the block size
> of the block device is changed while a direct I/O request is being
> setup, it can result in a panic. See comm
Commit 20ce44d545844 ("do_direct_IO: Use inode->i_blkbits to compute
block count to be cleaned") introduced a regression: if the block size
of the block device is changed while a direct I/O request is being
setup, it can result in a panic. See commit ab73857e354ab ("direct-io:
don't read inode->i_
On Sun 08-01-17 20:17:10, Chandan Rajendra wrote:
> The code currently uses sdio->blkbits to compute the number of blocks to
> be cleaned. However sdio->blkbits is derived from the logical block size
> of the underlying block device (Refer to the definition of
> do_blockdev_direct_IO()). Due to thi
From: Philippe Reynes
Date: Sat, 7 Jan 2017 22:37:29 +0100
> The ethtool api {get|set}_settings is deprecated.
> We move this driver to new api {get|set}_link_ksettings.
>
> Signed-off-by: Philippe Reynes
Applied.
From: Philippe Reynes
Date: Sat, 7 Jan 2017 22:35:13 +0100
> The ethtool api {get|set}_settings is deprecated.
> We move this driver to new api {get|set}_link_ksettings.
>
> Signed-off-by: Philippe Reynes
Applied.
On 01/06/2017 01:28 PM, John Allen wrote:
> Extend the existing PRRN infrastructure to perform the actual affinity
> updating for cpus and memory in addition to the device tree updating. For
> cpus, dynamic affinity updating already appears to exist in the kernel in
> the form of arch_update_cpu_to
On 01/06/2017 01:27 PM, John Allen wrote:
> Currently, memory must be hot removed and subsequently re-added in order
> to dynamically update the affinity of LMBs specified by a PRRN event.
> Earlier implementations of the PRRN event handler ran into issues in which
> the hot remove would occur succ
Chandan Rajendra writes:
> The code currently uses sdio->blkbits to compute the number of blocks to
> be cleaned. However sdio->blkbits is derived from the logical block size
> of the underlying block device (Refer to the definition of
> do_blockdev_direct_IO()). Due to this, generic/299 test wou
On 01/08/2017 07:47 AM, Chandan Rajendra wrote:
> The code currently uses sdio->blkbits to compute the number of blocks to
> be cleaned. However sdio->blkbits is derived from the logical block size
> of the underlying block device (Refer to the definition of
> do_blockdev_direct_IO()). Due to this,
On Sun, Jan 08, 2017 at 08:17:10PM +0530, Chandan Rajendra wrote:
> The code currently uses sdio->blkbits to compute the number of blocks to
> be cleaned. However sdio->blkbits is derived from the logical block size
> of the underlying block device (Refer to the definition of
> do_blockdev_direct_I
Rename the paca->soft_enabled to paca->soft_disabled_mask as
it is no more used as a flag for interrupt state.
Signed-off-by: Madhavan Srinivasan
---
arch/powerpc/include/asm/hw_irq.h | 36 ++--
arch/powerpc/include/asm/kvm_ppc.h | 2 +-
arch/powerpc/include/asm
Local atomic operations are fast and highly reentrant per CPU counters.
Used for percpu variable updates. Local atomic operations only guarantee
variable modification atomicity wrt the CPU which owns the data and
these needs to be executed in a preemption safe way.
Here is the design of this patch
To support disabling and enabling of irq with PMI, set of
new powerpc_local_irq_pmu_save() and powerpc_local_irq_restore()
functions are added. And powerpc_local_irq_save() implemented,
by adding a new soft_enabled manipulation function soft_enabled_or_return().
Local_irq_pmu_* macros are provided
New Kconfig is added "CONFIG_IRQ_DEBUG_SUPPORT" to add warn_on
to alert the invalid transitions. Also moved the code under
the CONFIG_TRACE_IRQFLAGS in arch_local_irq_restore() to new Kconfig.
Signed-off-by: Madhavan Srinivasan
---
arch/powerpc/Kconfig | 4
arch/powerpc/kernel/irq.c |
Two new bit mask field "IRQ_DISABLE_MASK_PMU" is introduced to support
the masking of PMI and "IRQ_DISABLE_MASK_ALL" to aid interrupt masking checking.
Couple of new irq #defs "PACA_IRQ_PMI" and "SOFTEN_VALUE_0xf0*" added to
use in the exception code to check for PMI interrupts.
In the masked_int
To support addition of "bitmask" to MASKABLE_* macros,
factor out the EXCPETION_PROLOG_1 macro.
Make it explicit the interrupt masking supported
by a gievn interrupt handler. Patch correspondingly
extends the MASKABLE_* macros with an addition's parameter.
"bitmask" parameter is passed to SOFTEN_T
Currently we use both EXCEPTION_PROLOG_1 and __EXCEPTION_PROLOG_1
in the MASKABLE_* macros. As a cleanup, this patch makes MASKABLE_*
to use only __EXCEPTION_PROLOG_1. There is not logic change.
Reviewed-by: Nicholas Piggin
Signed-off-by: Madhavan Srinivasan
---
arch/powerpc/include/asm/excepti
"paca->soft_enabled" is used as a flag to mask some of interrupts.
Currently supported flags values and their details:
soft_enabledMSR[EE]
0 0 Disabled (PMI and HMI not masked)
1 1 Enabled
"paca->soft_enabled" is initialized to 1 to make the interripts
Add new soft_enabled_* manipulation function and implement
arch_local_* using the soft_enabled_* wrappers.
Reviewed-by: Nicholas Piggin
Signed-off-by: Madhavan Srinivasan
---
arch/powerpc/include/asm/hw_irq.h | 32 ++--
1 file changed, 14 insertions(+), 18 deletions(
Force use of soft_enabled_set() wrapper to update paca-soft_enabled
wherever possisble. Also add a new wrapper function, soft_enabled_set_return(),
added to force the paca->soft_enabled updates.
Signed-off-by: Madhavan Srinivasan
---
arch/powerpc/include/asm/hw_irq.h | 14 ++
arch/p
Move set_soft_enabled() from powerpc/kernel/irq.c to
asm/hw_irq.c, to force updates to paca-soft_enabled
done via these access function. Add "memory" clobber
to hint compiler since paca->soft_enabled memory is the target
here
Renaming it as soft_enabled_set() will make
namespaces works better as p
Two #defs IRQ_DISABLE_LEVEL_NONE and IRQ_DISABLE_LEVEL_LINUX
are added to be used when updating paca->soft_enabled.
Replace the hardcoded values used when updating
paca->soft_enabled with IRQ_DISABLE_MASK_* #def.
No logic change.
Reviewed-by: Nicholas Piggin
Signed-off-by: Madhavan Srinivasan
--
Local atomic operations are fast and highly reentrant per CPU counters.
Used for percpu variable updates. Local atomic operations only guarantee
variable modification atomicity wrt the CPU which owns the data and
these needs to be executed in a preemption safe way.
Here is the design of the patchs
Use 0x10012 event code for PM_BR_CMPL event in
power9 event list instead of current 0x40060.
Fixes:34922527a2bcb ('powerpc/perf: Add power9 event list macros for generic
and cache events')
Signed-off-by: Madhavan Srinivasan
---
arch/powerpc/perf/power9-events-list.h | 2 +-
1 file changed, 1 in
Fixes:34922527a2bcb ('powerpc/perf: Add power9 event list macros for generic
and cache events')
Signed-off-by: Madhavan Srinivasan
---
arch/powerpc/perf/power9-events-list.h | 2 +-
arch/powerpc/perf/power9-pmu.c | 12 ++--
2 files changed, 7 insertions(+), 7 deletions(-)
diff
On Fri, Jan 06, 2017 at 10:43:59AM +0100, Nicolas Dichtel wrote:
> Regularly, when a new header is created in include/uapi/, the developer
> forgets to add it in the corresponding Kbuild file. This error is usually
> detected after the release is out.
>
> In fact, all headers under uapi directorie
On Fri, Jan 06, 2017 at 10:43:59AM +0100, Nicolas Dichtel wrote:
> diff --git a/arch/arm/include/uapi/asm/Kbuild
> b/arch/arm/include/uapi/asm/Kbuild
> index 46a76cd6acb6..607f702c2d62 100644
> --- a/arch/arm/include/uapi/asm/Kbuild
> +++ b/arch/arm/include/uapi/asm/Kbuild
> @@ -1,23 +1,6 @@
> #
On Mon, Jan 09, 2017 at 12:33:02PM +0100, Arnd Bergmann wrote:
> On Friday, January 6, 2017 10:43:53 AM CET Nicolas Dichtel wrote:
> >
> > diff --git a/arch/arm/include/asm/types.h b/arch/arm/include/asm/types.h
> > index a53cdb8f068c..c48fee3d7b3b 100644
> > --- a/arch/arm/include/asm/types.h
> >
On Friday, January 6, 2017 10:43:52 AM CET Nicolas Dichtel wrote:
> Here is the v2 of this series. The first 5 patches are just cleanup: some
> exported headers were still under a non-uapi directory.
Since this is meant as a cleanup, I commented on this to point out a cleaner
way to do the same.
Enhance KVM to cause a guest exit with KVM_EXIT_NMI
exit reason upon a machine check exception (MCE) in
the guest address space if the KVM_CAP_PPC_FWNMI
capability is enabled (instead of delivering a 0x200
interrupt to guest). This enables QEMU to build error
log and deliver machine check exception
On Friday, January 6, 2017 10:43:53 AM CET Nicolas Dichtel wrote:
>
> diff --git a/arch/arm/include/asm/types.h b/arch/arm/include/asm/types.h
> index a53cdb8f068c..c48fee3d7b3b 100644
> --- a/arch/arm/include/asm/types.h
> +++ b/arch/arm/include/asm/types.h
> @@ -1,40 +1,6 @@
> #ifndef _ASM_TYPE
This patch introduces a new KVM capability to control
how KVM behaves on machine check exception (MCE).
Without this capability, KVM redirects machine check
exceptions to guest's 0x200 vector, if the address in
error belongs to the guest. With this capability KVM
causes a guest exit with NMI exit r
On Friday, January 6, 2017 10:43:55 AM CET Nicolas Dichtel wrote:
> diff --git a/arch/nios2/include/uapi/asm/setup.h
> b/arch/nios2/include/uapi/asm/setup.h
> new file mode 100644
> index ..8d8285997ba8
> --- /dev/null
> +++ b/arch/nios2/include/uapi/asm/setup.h
> @@ -0,0 +1,6 @@
> +#
On Fri, Jan 06, 2017 at 10:43:59AM +0100, Nicolas Dichtel wrote:
> Regularly, when a new header is created in include/uapi/, the developer
> forgets to add it in the corresponding Kbuild file. This error is usually
> detected after the release is out.
>
> In fact, all headers under uapi directorie
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