[PATCH 5/5] KVM: PPC: Add MMIO emulation for remaining floating-point instructions

For completeness, this adds emulation of the lfiwax and lfiwzx instructions. With this, all floating-point load and store instructions as of Power ISA V2.07 are emulated. Signed-off-by: Paul Mackerras --- arch/powerpc/include/asm/ppc-opcode.h | 2 ++

[PATCH 4/5] KVM: PPC: Emulation for more integer loads and stores

This adds emulation for the following integer loads and stores, thus enabling them to be used in a guest for accessing emulated MMIO locations. - lhaux - lwaux - lwzux - ldu - lwa - stdux - stwux - stdu - ldbrx - stdbrx Previously, most of these would cause an emulation failure exit to

[PATCH 2/5] KVM: PPC: Book3S: Add MMIO emulation for FP and VSX instructions

From: Bin Lu This patch provides the MMIO load/store emulation for instructions of 'double & vector unsigned char & vector signed char & vector unsigned short & vector signed short & vector unsigned int & vector signed int & vector double '. The instructions that this

[PATCH 3/5] KVM: PPC: Add MMIO emulation for stdx (store doubleword indexed)

From: Alexey Kardashevskiy This adds missing stdx emulation for emulated MMIO accesses by KVM guests. This allows the Mellanox mlx5_core driver from recent kernels to work when MMIO emulation is enforced by userspace. Signed-off-by: Alexey Kardashevskiy

[PATCH 1/5] KVM: PPC: Provide functions for queueing up FP/VEC/VSX unavailable interrupts

This provides functions that can be used for generating interrupts indicating that a given functional unit (floating point, vector, or VSX) is unavailable. These functions will be used in instruction emulation code. Signed-off-by: Paul Mackerras ---

[PATCH 0/5] KVM: PPC: Improve MMIO emulation

Guests accessing emulated MMIO can do so using a wide variety of load and store instructions on PPC machines. However, KVM currently only knows about a subset of the load and store instructions available. This patchset expands the set of load and store instructions that KVM can emulate to include

Re: [PATCH] powerpc/powernv/cpuidle: Pass correct drv->cpumask for registration

* Michael Ellerman [2017-03-22 21:55:50]: > Vaidyanathan Srinivasan writes: > > * Michael Ellerman [2017-03-20 14:05:39]: > >> Vaidyanathan Srinivasan writes: > > > >> > On powernv platform

Re: [PATCH 4/5] powerpc/smp: add cpu_cache_mask

On Wed, Mar 15, 2017 at 10:26 PM, Michael Ellerman wrote: > Oliver O'Halloran writes: > >> Traditionally we have only ever tracked which CPUs are in the same core >> (cpu_sibling_mask) and on the same die (cpu_core_mask). For Power9 we >> need to be aware

[PATCH v3 0/6] powerpc/perf: Export memory hierarchy level

Power8/Power9 Perforence Monitoring Unit (PMU) supports different sampling modes (SM) such as Random Instruction Sampling (RIS), Random Load/Store Facility Sampling (RLS) and Random Branch Sampling (RBS). Sample mode RLS updates Sampled Instruction Event Register [SIER] bits with memory hierarchy

[PATCH v3 6/6] powerpc/perf: Add Power8 mem_access event to sysfs

Patch add "mem_access" event to sysfs. This as-is not a raw event supported by Power8 pmu. Instead, it is formed based on raw event encoding specificed in isa207-common.h. Primary PMU event used here is PM_MRK_INST_CMPL. This event tracks only the completed marked instructions. Random sampling

[PATCH v3 5/6] powerpc/perf: Support to export SIERs bit in Power9

Patch to export SIER bits to userspace via perf_mem_data_src and perf_sample_data struct. Cc: Benjamin Herrenschmidt Cc: Paul Mackerras Cc: Sukadev Bhattiprolu Cc: Daniel Axtens Cc: Andrew Donnellan

[PATCH v3 3/6] powerpc/perf: Support to export MMCRA[TEC*] field to userspace

Threshold feature when used with MMCRA [Threshold Event Counter Event], MMCRA[Threshold Start event] and MMCRA[Threshold End event] will update MMCRA[Threashold Event Counter Exponent] and MMCRA[Threshold Event Counter Multiplier] with the corresponding threshold event count values. Patch to

[PATCH v3 2/6] powerpc/perf: Export memory hierarchy info to user space

The LDST field and DATA_SRC in SIER identifies the memory hierarchy level (eg: L1, L2 etc), from which a data-cache miss for a marked instruction was satisfied. Use the 'perf_mem_data_src' object to export this hierarchy level to user space. Cc: Benjamin Herrenschmidt

[PATCH v3 4/6] powerpc/perf: Support to export SIERs bit in Power8

Patch to export SIER bits to userspace via perf_mem_data_src and perf_sample_data struct. Cc: Benjamin Herrenschmidt Cc: Paul Mackerras Cc: Daniel Axtens Cc: Andrew Donnellan Cc: Peter Zijlstra

[PATCH v3 1/6] powerpc/perf: Define big-endian version of perf_mem_data_src

From: Sukadev Bhattiprolu perf_mem_data_src is an union that is initialized via the ->val field and accessed via the bitmap fields. For this to work on big endian platforms (Which is broken now), we also need a big-endian represenation of perf_mem_data_src. i.e, in a

Re: [PATCH 2/5] powerpc/smp: add set_cpus_related()

On Wed, Mar 15, 2017 at 10:18 PM, Michael Ellerman wrote: > Oliver O'Halloran writes: >> diff --git a/arch/powerpc/kernel/smp.c b/arch/powerpc/kernel/smp.c >> index dfe0e1d9cd06..1c531887ca51 100644 >> --- a/arch/powerpc/kernel/smp.c >> +++

Re: [v7] powerpc/powernv: add hdat attribute to sysfs

On 23/03/17 09:27, Matt Brown wrote: The HDAT data area is consumed by skiboot and turned into a device-tree. In some cases we would like to look directly at the HDAT, so this patch adds a sysfs node to allow it to be viewed. This is not possible through /dev/mem as it is reserved memory which

Re: [PATCH 1/5] powerpc/smp: use cpu_to_chip_id() to find siblings

On Wed, Mar 15, 2017 at 10:18 PM, Michael Ellerman wrote: > Oliver O'Halloran writes: > >> To determine which logical CPUs are on the same core the kernel uses the >> ibm,chipid property from the device tree node associated with that cpu. >> The lookup for

[v7] powerpc/powernv: add hdat attribute to sysfs

The HDAT data area is consumed by skiboot and turned into a device-tree. In some cases we would like to look directly at the HDAT, so this patch adds a sysfs node to allow it to be viewed. This is not possible through /dev/mem as it is reserved memory which is stopped by the /dev/mem filter.

[PATCH 3/3] powerpc/configs: Re-enable POWER8 crc32c

From: Anton Blanchard The config option for the POWER8 crc32c recently changed from CONFIG_CRYPT_CRC32C_VPMSUM to CONFIG_CRYPTO_CRC32C_VPMSUM. Update the configs. Signed-off-by: Anton Blanchard

[PATCH 2/3] powerpc/configs: Make oprofile a module

From: Anton Blanchard Most people use perf these days, so save about 31kB by making oprofile a module. Signed-off-by: Anton Blanchard --- arch/powerpc/configs/powernv_defconfig | 2 +- arch/powerpc/configs/ppc64_defconfig | 2 +-

[PATCH 1/3] powerpc/configs: Re-enable ISO9660_FS as a built-in in 64 bit configs

From: Anton Blanchard It turns out cloud-config uses ISO9660 filesystems to inject configuration data into cloud images. The cloud-config failures when ISO9660_FS is not enabled are cryptic, and building it in makes mainline testing easier, so re-enable it. Signed-off-by: Anton

Re: Optimised memset64/memset32 for powerpc

On Wed, Mar 22, 2017 at 06:18:05AM -0700, Matthew Wilcox wrote: > There's one other potential user I've been wondering about, which are the > various console drivers. They use 'memsetw' to blank the entire console > or lines of the console when scrolling, but the only architecture which > ever

[PATCH v4 3/3] powerpc/xmon: add debugfs entry for xmon

Currently the xmon debugger is set only via kernel boot command-line. It's disabled by default, and can be enabled with "xmon=on" on the command-line. Also, xmon may be accessed via sysrq mechanism. But we cannot enable/disable xmon in runtime, it needs kernel reload. This patch introduces a

[PATCH v4 0/3] powerpc/xmon: improvements and fixes

This series contains some improvements and fixes to xmon: 1) Pan Xinhui fixed a long-term bug, in which the xmon debugger got stuck enabled after invoked by sysrq, regardless the state it was set in the kernel command-line. 2) A debugfs entry was added in order to allow users to enable/disable

[PATCH v4 2/3] powerpc/xmon: drop the nobt option from xmon plus minor fixes

The xmon parameter nobt was added long time ago, by commit 26c8af5f01df ("[POWERPC] print backtrace when entering xmon"). The problem that time was that during a crash in a machine with USB keyboard, xmon wouldn't respond to commands from the keyboard, so printing the backtrace wouldn't be

[PATCH v4 1/3] powerpc/xmon: Fix an unexpected xmon on/off state change

From: Pan Xinhui Once xmon is triggered by sysrq-x, it is enabled always afterwards even if it is disabled during boot. This will cause a system reset interrupt fail to dump. So keep xmon in its original state after exit. We have several ways to set xmon on or

Re: [FIX PATCH v1] powerpc/pseries: Fix reference count leak during CPU unplug

I get the error when removing a CPU that has been hotplugged after boot. On 03/14/2017 03:42 PM, Tyrel Datwyler wrote: > On 03/13/2017 03:29 AM, Bharata B Rao wrote: >> On Thu, Mar 09, 2017 at 01:34:00PM -0800, Tyrel Datwyler wrote: >>> On 03/08/2017 08:37 PM, Bharata B Rao wrote: The

Re: [v3 PATCH 4/4] powernv: Recover correct PACA on wakeup from a stop on P9 DD1

On Wed, 22 Mar 2017 20:34:17 +0530 "Gautham R. Shenoy" wrote: > From: "Gautham R. Shenoy" > > POWER9 DD1.0 hardware has an issue due to which the SPRs of a thread > waking up from stop 0,1,2 with ESL=1 can endup being misplaced in the > core.

[v3 PATCH 1/4] powernv: Move CPU-Offline idle state invocation from smp.c to idle.c

From: "Gautham R. Shenoy" Move the piece of code in powernv/smp.c::pnv_smp_cpu_kill_self() which transitions the CPU to the deepest available platform idle state to a new function named pnv_cpu_offline() in powernv/idle.c. The rationale behind this code movement is that

[v3 PATCH 4/4] powernv: Recover correct PACA on wakeup from a stop on P9 DD1

From: "Gautham R. Shenoy" POWER9 DD1.0 hardware has an issue due to which the SPRs of a thread waking up from stop 0,1,2 with ESL=1 can endup being misplaced in the core. Thus the HSPRG0 of a thread waking up from can contain the paca pointer of its sibling. This patch

[v3 PATCH 3/4] powernv:idle: Don't override default/deepest directly in kernel

From: "Gautham R. Shenoy" Currently during idle-init on power9, if we don't find suitable stop states in the device tree that can be used as the default_stop/deepest_stop, we set stop0 (ESL=1,EC=1) as the default stop state psscr to be used by power9_idle and deepest

[v3 PATCH 2/4] powernv:smp: Add busy-wait loop as fall back for CPU-Hotplug

From: "Gautham R. Shenoy" Currently, the powernv cpu-offline function assumes that platform idle states such as stop on POWER9, winkle/sleep/nap on POWER8 are always available. On POWER8, it picks nap as the default state if other deep idle states like sleep/winkle are

[v3 PATCH 0/4] powernv:idle: Fixes for CPU-Hotplug on POWER DD1.0

From: "Gautham R. Shenoy" Hi, This is the third version of the patchset containing the fixes to make CPU-Hotplug working on correctly on POWER9 DD1 systems. The earlier versions can be found here: [v2] : https://lkml.org/lkml/2017/3/20/555 [v1] :

Re: [PATCH 1/3] drivers/of/base.c: Add of_property_read_u64_index

On Tue, Mar 21, 2017 at 10:49 PM, Alistair Popple wrote: > There is of_property_read_u32_index but no u64 variant. This patch > adds one similar to the u32 version for u64. > > Signed-off-by: Alistair Popple > --- > drivers/of/base.c | 31

Re: Optimised memset64/memset32 for powerpc

On Wed, Mar 22, 2017 at 08:26:12AM +1100, Benjamin Herrenschmidt wrote: > On Tue, 2017-03-21 at 06:29 -0700, Matthew Wilcox wrote: > > > > Well, those are the generic versions in the first patch: > > > > http://git.infradead.org/users/willy/linux-dax.git/commitdiff/538b977 > >

Re: Revert "powerpc/64: Disable use of radix under a hypervisor"

On Tue, 2017-03-21 at 01:38:02 UTC, Paul Mackerras wrote: > This reverts commit 3f91a89d424a79f8082525db5a375e438887bb3e. > > Now that we do have the machinery for using the radix MMU under a > hypervisor, the extra check and comment introduced in 3f91a89d424a are > no longer correct. The result

Re: gcc-plugins: update architecture list in documentation

On Mon, 2017-03-20 at 06:55:22 UTC, Andrew Donnellan wrote: > Commit 65c059bcaa73 ("powerpc: Enable support for GCC plugins") enabled GCC > plugins on powerpc, but neglected to update the architecture list in the > docs. Rectify this. > > Fixes: 65c059bcaa73 ("powerpc: Enable support for GCC

Re: [PATCH] powerpc: fix /proc/self/stack

Thadeu Lima de Souza Cascardo writes: > For the current task, the kernel stack would only tell the last time the > process was rescheduled, if ever. Use the current stack pointer for the > current task. You say "fix" in the subject, but is it a bug, or just an

Re: [PATCH] powerpc/powernv/cpuidle: Pass correct drv->cpumask for registration

Vaidyanathan Srinivasan writes: > * Michael Ellerman [2017-03-20 14:05:39]: >> Vaidyanathan Srinivasan writes: > >> > On powernv platform cpu_present could be less than cpu_possible >> > in cases where firmware detects

Re: [PATCH 1/2] powerpc/powernv: process interrupts from system reset wakeup

Nicholas Piggin writes: > When the CPU wakes from low power state, it begins at the system reset > interrupt with the exception that caused the wakeup encoded in SRR1. > > Today, powernv idle wakeup ignores the wakeup reason (except a special > case for HMI), and the regular

Re: [v2 PATCH 4/4] powernv: Recover correct PACA on wakeup from a stop on P9 DD1

On Wed, 22 Mar 2017 11:28:46 +0530 Gautham R Shenoy wrote: > On Tue, Mar 21, 2017 at 02:59:46AM +1000, Nicholas Piggin wrote: > > On Mon, 20 Mar 2017 21:24:18 +0530 > > "Gautham R. Shenoy" wrote: > > > > > From: "Gautham R. Shenoy"