[PATCH v4 11/11] VAS: Define copy/paste interfaces

Define interfaces (wrappers) to the 'copy' and 'paste' instructions (which are new in PowerISA 3.0). These are intended to be used to by NX driver(s) to submit Coprocessor Request Blocks (CRBs) to the NX hardware engines. Signed-off-by: Sukadev Bhattiprolu ---

[PATCH v4 09/11] VAS: Define vas_win_close() interface

Define the vas_win_close() interface which should be used to close a send or receive windows. While the hardware configurations required to open send and receive windows differ, the configuration to close a window is the same for both. So we use a single interface to close the window.

[PATCH v4 10/11] VAS: Define vas_tx_win_open()

Define an interface to open a VAS send window. This interface is intended to be used the Nest Accelerator (NX) driver(s) to open a send window and use it to submit compression/encryption requests to a VAS receive window. The receive window, identified by the [vasid, cop] parameters, must already

[PATCH v4 06/11] VAS: Define helpers to init window context

Define helpers to initialize window context registers of the VAS hardware. These will be used in follow-on patches when opening/closing VAS windows. Signed-off-by: Sukadev Bhattiprolu --- Changelog[v4] - Michael Neuling] Use ilog2(), radix_enabled() helpers;

[PATCH v4 07/11] VAS: Define helpers to alloc/free windows

Define helpers to allocate/free VAS window objects. These will be used in follow-on patches when opening/closing windows. Signed-off-by: Sukadev Bhattiprolu --- arch/powerpc/platforms/powernv/vas-window.c | 63 - 1 file changed, 62

[PATCH v4 04/11] VAS: Define vas_init() and vas_exit()

Implement vas_init() and vas_exit() functions for a new VAS module. This VAS module is essentially a library for other device drivers and kernel users of the NX coprocessors like NX-842 and NX-GZIP. In the future this will be extended to add support for user space to access the NX coprocessors.

[PATCH v4 08/11] VAS: Define vas_rx_win_open() interface

Define the vas_rx_win_open() interface. This interface is intended to be used by the Nest Accelerator (NX) driver(s) to setup receive windows for one or more NX engines (which implement compression/encryption algorithms in the hardware). Follow-on patches will provide an interface to close the

[PATCH v4 05/11] VAS: Define helpers for access MMIO regions

Define some helper functions to access the MMIO regions. We use these in a follow-on patches to read/write VAS hardware registers. These helpers are also used to later issue 'paste' instructions to submit requests to the NX hardware engines. Signed-off-by: Sukadev Bhattiprolu

[PATCH v4 03/11] Move GET_FIELD/SET_FIELD to vas.h

Move the GET_FIELD and SET_FIELD macros to vas.h as VAS and other users of VAS, including NX-842 can use those macros. There is a lot of related code between the VAS/NX kernel drivers and skiboot. For consistency switch the order of parameters in SET_FIELD to match the order in skiboot.

[PATCH v4 02/11] VAS: Define macros, register fields and structures

Define macros for the VAS hardware registers and bit-fields as well as couple of data structures needed by the VAS driver. Signed-off-by: Sukadev Bhattiprolu --- Changelog[v4] - [Michael Neuling] Move VAS code to arch/powerpc; Reorg vas.h and

[PATCH v4 00/11] Enable VAS

Power9 introduces a hardware subsystem referred to as the Virtual Accelerator Switchboard (VAS). VAS allows kernel subsystems and user space processes to directly access the Nest Accelerator (NX) engines which implement compression and encryption algorithms in the hardware. NX has been in Power

[PATCH v4 01/11] Add Power9 PVR

Add Power9 PVR Signed-off-by: Sukadev Bhattiprolu --- arch/powerpc/include/asm/reg.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h index fc879fd..7a45ff7 100644 --- a/arch/powerpc/include/asm/reg.h

Re: [RFC PATCH 2/5] soc/fsl/qbman: Use shared-dma-pool for QMan private memory allocations

Robin Murphy writes: > Hi Roy, > > On 29/03/17 22:13, Roy Pledge wrote: >> Use the shared-memory-pool mechanism for frame queue descriptor and >> packed frame descriptor record area allocations. > > Thanks for persevering with this - in my opinion it's now looking like > it

[PATCH] powerpc: Avoid taking a data miss on every userspace instruction miss

From: Anton Blanchard Early on in do_page_fault() we call store_updates_sp(), regardless of the type of exception. For an instruction miss this doesn't make sense, because we only use this information to detect if a data miss is the result of a stack expansion instruction or

Re: [PATCH] powerpc/time: set ->min_delta_ticks and ->max_delta_ticks

Nicolai Stange writes: > In preparation for making the clockevents core NTP correction aware, > all clockevent device drivers must set ->min_delta_ticks and > ->max_delta_ticks rather than ->min_delta_ns and ->max_delta_ns: a > clockevent device's rate is going to change

[PATCH 2/2] powerpc/mm: add phys addr to linux page table dump

The current page table dumper scans the linux page tables and coalesces mappings with adjacent virtual addresses and similar PTE flags. This behaviour is somewhat broken when you consider the IOREMAP space where entirely unrelated mappings will appear to be contiguous. This patch modifies the

[PATCH 1/2] powerpc/mm: fix up pgtable dump flags

On Book3s we have two PTE flags used to mark cache-inhibited mappings: _PAGE_TOLERANT and _PAGE_NON_IDEMPOTENT. Currently the kernel page table dumper only looks at the generic _PAGE_NO_CACHE which is defined to be _PAGE_TOLERANT. This patch modifies the dumper so both flags are shown in the dump.

Re: [PATCH v4 2/3] powerpc/xmon: drop the nobt option from xmon plus minor fixes

On Wed, Mar 22, 2017 at 04:27:50PM -0300, Guilherme G. Piccoli wrote: > The xmon parameter nobt was added long time ago, by commit 26c8af5f01df > ("[POWERPC] print backtrace when entering xmon"). The problem that time > was that during a crash in a machine with USB keyboard, xmon wouldn't >

[PATCH] powerpc/powernv: utilising darn instruction for get_random_seed on p9

Currently ppc_md.get_random_seed uses the powernv_get_random_long function. A guest calling this function would have to go through the hypervisor. The 'darn' instruction, introduced in power 9, allows us to bypass this by directly obtaining a value from the mmio region. This patch adds an

Re: [PATCH v9 2/3] PCI: Add a macro to set default alignment for all PCI devices

On Mon, Mar 27, 2017 at 09:25:50PM +1100, Benjamin Herrenschmidt wrote: > On Mon, 2017-03-27 at 21:17 +1100, Michael Ellerman wrote: > > > If so, is it acceptable to force that kernel to user 64K alignment > > > even > > > when it's running on non-PowerNV systems? > > > > Probably, but I'm not

Re: [PATCH v3 01/10] VAS: Define macros, register fields and structures

Sukadev Bhattiprolu [suka...@linux.vnet.ibm.com] wrote: > Michael Neuling [mi...@neuling.org] wrote: > > On Thu, 2017-03-16 at 20:33 -0700, Sukadev Bhattiprolu wrote: > > > Define macros for the VAS hardware registers and bit-fields as well > > > as couple of data structures needed by the VAS

[PATCH] powerpc/time: set ->min_delta_ticks and ->max_delta_ticks

In preparation for making the clockevents core NTP correction aware, all clockevent device drivers must set ->min_delta_ticks and ->max_delta_ticks rather than ->min_delta_ns and ->max_delta_ns: a clockevent device's rate is going to change dynamically and thus, the ratio of ns to ticks ceases to

Re: [PATCH v4] powernv/sensor: Handle OPAL_WRONG_STATE error return

Hi Michael, Any feedback/outlook with this patch ? Regards, Vipin On Friday 10 March 2017 05:27 PM, Vipin K Parashar wrote: OPAL returns OPAL_WRONG_STATE upon failing to provide sensor data due to core sleeping/offline. Added check in opal_get_sensor_data() for sensor read failure with

Re: [PATCH] crypto: vmx: Remove dubiously licensed crypto code

On 2017-03-29 20:08, Tyrel Datwyler wrote: On 03/29/2017 08:13 AM, Michal Suchánek wrote: On Wed, 29 Mar 2017 16:51:35 +0200 Greg Kroah-Hartman wrote: On Wed, Mar 29, 2017 at 02:56:39PM +0200, Michal Suchanek wrote: While reviewing commit 11c6e16ee13a ("crypto:

Re: [RFC PATCH 2/5] soc/fsl/qbman: Use shared-dma-pool for QMan private memory allocations

Hi Roy, On 29/03/17 22:13, Roy Pledge wrote: > Use the shared-memory-pool mechanism for frame queue descriptor and > packed frame descriptor record area allocations. Thanks for persevering with this - in my opinion it's now looking like it was worth the effort :) AFAICS the ioremap_wc() that

[PATCH] tty/hvc_console: fix console lock ordering with spinlock

hvc_remove() takes a spin lock first then acquires the console semaphore. This situation can easily lead to a deadlock scenario where we call scheduler with spin lock held. Signed-off-by: Denis Kirjanov --- drivers/tty/hvc/hvc_console.c | 4 ++-- 1 file changed, 2

Re: [PATCH V3 0/7] cxl: Add support for Coherent Accelerator Interface Architecture 2.0

Le 30/03/2017 à 06:44, Andrew Donnellan a écrit : On 29/03/17 02:14, Christophe Lombard wrote: This series adds support for a cxl card which supports the Coherent Accelerator Interface Architecture 2.0. It requires IBM Power9 system and the Power Service Layer, version 9. The PSL provides the

[PATCH] dpaa_eth: use AVOIDBLOCK for Tx confirmation queues

The AVOIDBLOCK flag determines the Tx confirmation queues processing to be redirected to any available CPU when the current one is slow in processing them. This may result in a higher Tx confirmation interrupt count but may reduce pressure on a certain CPU that with the previous setting would

[PATCH] fsl/fman: take into account all RGMII modes

Accept the internal delay RGMII variants. Signed-off-by: Madalin Bucur --- drivers/net/ethernet/freescale/fman/fman_dtsec.c | 8 +++- drivers/net/ethernet/freescale/fman/fman_memac.c | 5 - 2 files changed, 11 insertions(+), 2 deletions(-) diff --git

[PATCH] powerpc/powernv: Fix opal entry/exit MSR_RI coverage

There are some windows in opal entry/exit that can not recover from a re-entrant interrupt (e.g., machine check) due to using SRR registers, but they currently do not have MSR_RI clear. These were found by machine check injection coverage tests using the powerpc system simulator (Mambo).

[PATCH v6 19/19] powerpc/mm: Enable mappings above 128TB

From: "Aneesh Kumar K.V" Not all user space application is ready to handle wide addresses. It's known that at least some JIT compilers use higher bits in pointers to encode their information. It collides with valid pointers with 512TB addresses and leads to

[PATCH v6 18/19] powerpc/mm: Switch some TASK_SIZE checks to use mm_context addr_limit

From: "Aneesh Kumar K.V" Signed-off-by: Aneesh Kumar K.V Signed-off-by: Michael Ellerman --- arch/powerpc/mm/hugetlbpage-radix.c | 4 ++-- arch/powerpc/mm/mmap.c | 12 ++--

[PATCH v6 17/19] powerpc/pseries: Skip using reserved virtual address range

From: "Aneesh Kumar K.V" Now that we use all the available virtual address range, we need to make sure we don't generate VSID such that it overlaps with the reserved vsid range. Reserved vsid range include the virtual address range used by the adjunct partition

[PATCH v6 16/19] powerpc/mm/hash: Store addr_limit in PACA

From: "Aneesh Kumar K.V" We optmize the slice page size array copy to paca by copying only the range based on addr_limit. This will require us to not look at page size array beyond addr_limit in PACA on slb fault. To enable that copy task size to paca which will

[PATCH v6 15/19] powerpc/mm: Add addr_limit to mm_context and use it to derive max slice index

From: "Aneesh Kumar K.V" In the followup patch, we will increase the slice array size to handle 512TB range, but will limit the max addr to 128TB. Avoid doing unnecessary computation and avoid doing slice mask related operation above address limit.

[PATCH v6 14/19] powerpc/mm/hash: Increase VA range to 128TB

From: "Aneesh Kumar K.V" We update the hash linux page table layout such that we can support 512TB. But we limit the TASK_SIZE to 128TB. We can switch to 128TB by default without conditional because that is the max virtual address supported by other

[PATCH v6 13/19] powerpc/mm/hash: Convert mask to unsigned long

From: "Aneesh Kumar K.V" This doesn't have any functional change. But helps in avoiding mistakes in case the shift bit changes Signed-off-by: Aneesh Kumar K.V Signed-off-by: Michael Ellerman ---

[PATCH v6 12/19] powerpc/mm/hash: Support 68 bit VA

From: "Aneesh Kumar K.V" Inorder to support large effective address range (512TB), we want to increase the virtual address bits to 68. But we do have platforms like p4 and p5 that can only do 65 bit VA. We support those platforms by limiting context bits on them

[PATCH v6 11/19] powerpc/mm/hash: Check for non-kernel address in get_kernel_vsid()

get_kernel_vsid() has a very stern comment saying that it's only valid for kernel addresses, but there's nothing in the code to enforce that. Rather than hoping our callers are well behaved, add a check and return a VSID of 0 (invalid). Signed-off-by: Michael Ellerman ---

[PATCH v6 10/19] powerpc/mm/hash: Use context ids 1-4 for the kernel

From: "Aneesh Kumar K.V" Currently we use the top 4 context ids (0x7fffc-0x7) for the kernel. Kernel VSIDs are built using these top context values and effective the segement ID. In subsequent patches we want to increase the max effective address to 512TB. We

[PATCH v6 09/19] powerpc/mm: Split radix vs hash mm context initialisation

Complete the split of the radix vs hash mm context initialisation. This is mostly code movement, with the exception that we now limit the context allocation to PRTB_ENTRIES - 1 on radix. Signed-off-by: Michael Ellerman --- arch/powerpc/include/asm/book3s/64/mmu.h | 2 +

[PATCH v6 08/19] powerpc/mm/hash: Pull hash constants into hash__alloc_context_id()

The min and max context id values used in alloc_context_id() are currently the right values for use on hash, and happen to also be safe for use on radix. But we need to change that in a subsequent patch, so make the min/max ids parameters and pull the hash values into hsah__alloc_context_id().

[PATCH v6 07/19] powerpc/mm/hash: Abstract context id allocation for KVM

KVM wants to be able to allocate an MMU context id, which it does currently by calling __init_new_context(). We're about to rework that code, so provide a wrapper for KVM so it can not worry about the details. Signed-off-by: Michael Ellerman ---

[PATCH v6 06/19] powerpc/mm/slice: Update slice mask printing to use bitmap printing.

From: "Aneesh Kumar K.V" We now get output like below which is much better. [0.935306] good_mask low_slice: 0-15 [0.935360] good_mask high_slice: 0-511 Compared to [0.953414] good_mask: - 1. I also fixed an

[PATCH v6 05/19] powerpc/mm/slice: Move slice_mask struct definition to slice.c

From: "Aneesh Kumar K.V" This structure definition need not be in a header since this is used only by slice.c file. So move it to slice.c. This also allow us to use SLICE_NUM_HIGH instead of 64. I also switch the low_slices type to u64 from u16. This doesn't

[PATCH v6 04/19] powerpc/mm: Remove checks that TASK_SIZE_USER64 is too small

From: "Aneesh Kumar K.V" Remove the checks that TASK_SIZE_USER64 is smaller than H_PGTABLE_RANGE and USER_VSID_RANGE. In a following patch we will deliberately add support for a TASK_SIZE smaller than both ranges, so this will no longer be an error condition.

[PATCH v6 03/19] powerpc/mm: Move copy_mm_to_paca to paca.c

From: "Aneesh Kumar K.V" We also update the function arg to struct mm_struct. Move this so that function finds the definition of struct mm_struct. No functional change in this patch. Signed-off-by: Aneesh Kumar K.V

[PATCH v6 02/19] powerpc/mm/slice: Update the function prototype

From: "Aneesh Kumar K.V" This avoid copying the slice_mask struct as function return value Signed-off-by: Aneesh Kumar K.V Signed-off-by: Michael Ellerman --- arch/powerpc/mm/slice.c | 62

[PATCH v6 01/19] powerpc/mm/slice: Convert slice_mask high slice to a bitmap

From: "Aneesh Kumar K.V" In followup patch we want to increase the va range which will result in us requiring high_slices to have more than 64 bits. To enable this convert high_slices to bitmap. We keep the number bits same in this patch and later change that to

[PATCH] powerpc/powernv/ioda2: Add __printf format/argument verification

Fix fallout too. Signed-off-by: Joe Perches --- arch/powerpc/platforms/powernv/pci-ioda.c | 31 --- arch/powerpc/platforms/powernv/pci.h | 2 ++ 2 files changed, 18 insertions(+), 15 deletions(-) diff --git

Re: [v3 PATCH 2/4] powernv:smp: Add busy-wait loop as fall back for CPU-Hotplug

On Mon, Mar 27, 2017 at 10:43:44PM +1100, Michael Ellerman wrote: > "Gautham R. Shenoy" writes: > > > diff --git a/arch/powerpc/platforms/powernv/idle.c > > b/arch/powerpc/platforms/powernv/idle.c > > index 419edff..f335e0f 100644 > > ---

Re: [PATCH 1/2] powerpc: string: implement optimized memset variants

On 2017/03/29 10:36PM, Michael Ellerman wrote: > "Naveen N. Rao" writes: > > I also tested zram today with the command shared by Wilcox: > > > > without patch: 1.493782568 seconds time elapsed( +- 0.08% ) > > with patch: 1.408457577 seconds

Re: [PATCH 2/2] powerpc/book3s: Display task info for MCE error in user mode.

On 03/30/2017 05:39 AM, Nicholas Piggin wrote: > On Tue, 28 Mar 2017 19:15:28 +0530 > Mahesh J Salgaonkar wrote: > >> From: Mahesh Salgaonkar >> >> For MCE that hit while in use mode MSR(HV=1,PR=1), print the task info on the >> console MCE