[PATCH 1/2] powerpc/tracing: Trace TLBIE(L)

Just a quick patch to trace tlbie(l)'s. The idea being that it can be enabled when we suspect corruption or when we need to see if we are doing the right thing during flush. I think the format can be enhanced to make it nicer (expand the RB/RS/IS/L cases in more detail if we ever need that level

[PATCH v2] ppc64/kprobe: Fix oops when kprobed on 'stdu' instruction

If we set a kprobe on a 'stdu' instruction on powerpc64, we see a kernel OOPS: [ 1275.165932] Bad kernel stack pointer cd93c840 at c0009868 [ 1275.166378] Oops: Bad kernel stack pointer, sig: 6 [#1] ... GPR00: c01fcd93cb30 cd93c840 c15c5e00 cd93c840

Re: EEH error in doing DMA with PEX 8619

On Tue, Apr 11, 2017 at 12:15:10PM +1000, Benjamin Herrenschmidt wrote: >On Mon, 2017-04-10 at 19:04 -0700, IanJiang wrote: >> Thanks for your replay. >> >> I fixed my test according your suggestion. The CPU physical addresses (0x >> 1f9e40 and 0x 1f82c0) converted with virt_to_phys() are

[RFC][PATCH] powerpc/syscalls/trace: Fix mmap in syscalls_trace

This patch uses SYSCALL_DEFINE6 for sys_mmap and sys_mmap2 so that the meta-data associated with these syscalls is visible to the syscall tracer. In the absence of this generic syscalls (defined outside arch) like munmap,etc. are visible in available_events, syscall_enter_mmap and

Re: [PATCH] ibmveth: Support to enable LSO/CSO for Trunk VEA.

Re-sending as my earlier response had some HTML subparts. Let me give some background before I answer your queries. In IBM PowerVM environment, ibmveth driver supports largesend and checksum offload today, but only for virtual ethernet adapters (VEA) which are not configured in "Trunk mode".

Re: clear_page, copy_page address align question?

On Tue, Apr 11, 2017 at 01:12:24PM +1000, Benjamin Herrenschmidt wrote: > On Tue, 2017-04-11 at 12:08 +0900, Minchan Kim wrote: > > Hello, > > > > When I tested zram in ppc64, I got random corruption. > > With investigation, it seems clear_page corrupted the memory. > > I passed 64K

Re: clear_page, copy_page address align question?

On Tue, 2017-04-11 at 12:08 +0900, Minchan Kim wrote: > Hello, > > When I tested zram in ppc64, I got random corruption. > With investigation, it seems clear_page corrupted the memory. > I passed 64K kmalloced(kmalloc(PAGE_SIZE)) address to clear_page > and turned on slub debug so address is not

clear_page, copy_page address align question?

Hello, When I tested zram in ppc64, I got random corruption. With investigation, it seems clear_page corrupted the memory. I passed 64K kmalloced(kmalloc(PAGE_SIZE)) address to clear_page and turned on slub debug so address is not aligned with PAGE_SIZE. Is it a valid usecase that non-PAGE_SIZE

[PATCH v3 5/5] perf report: Show branch type in callchain entry

Show branch type in callchain entry. The branch type is printed with other LBR information (such as cycles/abort/...). One example: perf report --branch-history --stdio --no-children --23.54%--main div.c:42 (CROSS_2M RET cycles:2) compute_flag div.c:28 (RET cycles:2)

[PATCH v3 4/5] perf report: Show branch type statistics for stdio mode

Show the branch type statistics at the end of perf report --stdio. For example: perf report --stdio JCC forward: 27.8% JCC backward: 9.7% CROSS_4K: 0.0% CROSS_2M: 14.3% JCC: 37.6% JMP: 0.0% IND_JMP: 6.5% CALL: 26.6% RET: 29.3%

[PATCH v3 3/5] perf record: Create a new option save_type in --branch-filter

The option indicates the kernel to save branch type during sampling. One example: perf record -g --branch-filter any,save_type Signed-off-by: Jin Yao --- tools/perf/Documentation/perf-record.txt | 1 + tools/perf/util/parse-branch-options.c | 1 + 2 files changed, 2

[PATCH v3 2/5] perf/x86/intel: Record branch type

Perf already has support for disassembling the branch instruction and using the branch type for filtering. The patch just records the branch type in perf_branch_entry. Before recording, the patch converts the x86 branch classification to common branch classification. Signed-off-by: Jin Yao

[PATCH v3 1/5] perf/core: Define the common branch type classification

It is often useful to know the branch types while analyzing branch data. For example, a call is very different from a conditional branch. Currently we have to look it up in binary while the binary may later not be available and even the binary is available but user has to take some time. It is

[PATCH v3 0/5] perf report: Show branch type

v3: --- 1. Move the JCC forward/backward and cross page computing from kernel to userspace. 2. Use lookup table to replace original switch/case processing. Changed: perf/core: Define the common branch type classification perf/x86/intel: Record branch type perf report: Show branch type

Re: EEH error in doing DMA with PEX 8619

On Mon, 2017-04-10 at 19:04 -0700, IanJiang wrote: > Thanks for your replay. > > I fixed my test according your suggestion. The CPU physical addresses (0x > 1f9e40 and 0x 1f82c0) converted with virt_to_phys() are used , > instead of DMA addresses, or BUS physical addresses (0x 60a0

Re: EEH error in doing DMA with PEX 8619

Thanks for your replay. I fixed my test according your suggestion. The CPU physical addresses (0x 1f9e40 and 0x 1f82c0) converted with virt_to_phys() are used , instead of DMA addresses, or BUS physical addresses (0x 60a0 and 0x 60c0). However, EEH still reports error. Memory

[PATCH v3 6/6] powerpc/perf: Add Power8 mem_access event to sysfs

Patch add "mem_access" event to sysfs. This as-is not a raw event supported by Power8 pmu. Instead, it is formed based on raw event encoding specificed in isa207-common.h. Primary PMU event used here is PM_MRK_INST_CMPL. This event tracks only the completed marked instructions. Random sampling

[PATCH v3 5/6] powerpc/perf: Support to export SIERs bit in Power9

Patch to export SIER bits to userspace via perf_mem_data_src and perf_sample_data struct. Signed-off-by: Madhavan Srinivasan --- arch/powerpc/perf/power9-pmu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/powerpc/perf/power9-pmu.c

[PATCH v3 4/6] powerpc/perf: Support to export SIERs bit in Power8

Patch to export SIER bits to userspace via perf_mem_data_src and perf_sample_data struct. Signed-off-by: Sukadev Bhattiprolu Signed-off-by: Madhavan Srinivasan --- arch/powerpc/perf/power8-pmu.c | 2 ++ 1 file changed, 2 insertions(+) diff

[PATCH v3 1/6] powerpc/perf: Define big-endian version of perf_mem_data_src

From: Sukadev Bhattiprolu perf_mem_data_src is an union that is initialized via the ->val field and accessed via the bitmap fields. For this to work on big endian platforms (Which is broken now), we also need a big-endian represenation of perf_mem_data_src. i.e, in a

[PATCH v3 3/6] powerpc/perf: Support to export MMCRA[TEC*] field to userspace

Threshold feature when used with MMCRA [Threshold Event Counter Event], MMCRA[Threshold Start event] and MMCRA[Threshold End event] will update MMCRA[Threashold Event Counter Exponent] and MMCRA[Threshold Event Counter Multiplier] with the corresponding threshold event count values. Patch to

[PATCH v3 2/6] powerpc/perf: Export memory hierarchy info to user space

The LDST field and DATA_SRC in SIER identifies the memory hierarchy level (eg: L1, L2 etc), from which a data-cache miss for a marked instruction was satisfied. Use the 'perf_mem_data_src' object to export this hierarchy level to user space. Signed-off-by: Sukadev Bhattiprolu

[PATCH v3 0/6] powerpc/perf: Export memory hierarchy level

Power8/Power9 Perforence Monitoring Unit (PMU) supports different sampling modes (SM) such as Random Instruction Sampling (RIS), Random Load/Store Facility Sampling (RLS) and Random Branch Sampling (RBS). Sample mode RLS updates Sampled Instruction Event Register [SIER] bits with memory hierarchy

Re: powerpc/powernv: Fix powernv Kconfig dependencies

On Mon, 2017-04-10 at 05:24:35 UTC, Alistair Popple wrote: > The patch to introduce address translation services for Nvlink2 uses > MMU notifiers. However usage of MMU notifiers requires a Kconfig > option which is not selected by default on powerpc so add it to the > powernv Kconfig. > >

Re: powerpc/mm: Remove reduntant initmem information from log

On Fri, 2017-04-07 at 06:53:11 UTC, Anshuman Khandual wrote: > Generic core VM already prints these information in the log > buffer, hence there is no need for a second print. This just > removes the second print from arch powerpc NUMA init path. > > Before the patch: > > $dmesg | grep "Initmem"

Re: [V4] powerpc/hugetlb: Add ABI defines for supported HugeTLB page sizes

On Fri, 2017-04-07 at 03:55:39 UTC, Anshuman Khandual wrote: > This just adds user space exported ABI definitions for 2MB, 16MB, 1GB, > 16GB non default huge page sizes to be used with mmap() system call. > > Signed-off-by: Anshuman Khandual Applied to powerpc next,

Re: [v2] powerpc: Make sparsemem the default on 64-bit Book3S

On Wed, 2017-04-05 at 06:10:48 UTC, Michael Ellerman wrote: > Make sparsemem the default on all 64-bit Book3S platforms. It already is > for pseries and ps3, and we need to enable it for powernv because on > POWER9 memory between chips is discontiguous. > > For the other platforms sparsemem

Re: powerpc/nohash: Fix use of mmu_has_feature() in setup_initial_memory_limit()

On Mon, 2017-04-03 at 02:05:55 UTC, Michael Ellerman wrote: > setup_initial_memory_limit() is called from early_init_devtree(), which > runs prior to feature patching. If the kernel is built with > CONFIG_JUMP_LABEL=y > and CONFIG_JUMP_LABEL_FEATURE_CHECKS=y then we will potentially get the >

Re: [2/2] powerpc/mm/radix: Remove unnecessary ptesync

On Sat, 2017-04-01 at 14:41:48 UTC, "Aneesh Kumar K.V" wrote: > For a tlbiel with pid, we need to issue tlbiel with set number encoded. We > don't need to do ptesync for each of those. Instead we need one for the entire > tlbiel pid operation. > > Signed-off-by: Benjamin Herrenschmidt

Re: [1/2] powerpc/mm/radix: Don't do page walk cache flush when doing full mm flush

On Sat, 2017-04-01 at 14:41:47 UTC, "Aneesh Kumar K.V" wrote: > For fullmm tlb flush, we do a flush with RIC_FLUSH_ALL which will invalidate > all > related caches (radix__tlb_flush()). Hence the pwc flush is not needed. > > Signed-off-by: Aneesh Kumar K.V >

[PATCH 2/2] powerpc: Remove unnecessary includes of asm/debug.h

These files don't seem to have any need for asm/debug.h, now that all it includes are the debugger hooks and breakpoint definitions. Signed-off-by: Michael Ellerman --- arch/powerpc/kernel/fadump.c | 1 - arch/powerpc/kernel/irq.c| 1 -

[PATCH 1/2] powerpc: Create asm/debugfs.h and move powerpc_debugfs_root there

powerpc_debugfs_root is the dentry representing the root of the "powerpc" directory tree in debugfs. Currently it sits in asm/debug.h, a long with some other things that have "debug" in the name, but are otherwise unrelated. Pull it out into a separate header, which also includes

Re: [PATCH] ppc64/kprobe: Fix oops when kprobed on 'stdu' instruction

Hi Ravi, > If we set a kprobe on a 'stdu' instruction on powerpc64, we see a > kernel OOPS: Ouch! We should mark this for stable. Anton

Re: EEH error in doing DMA with PEX 8619

On Mon, Apr 10, 2017 at 05:22:33AM -0700, IanJiang wrote: >Hi all! > >I am porting PLX driver for PEX 8619 to a power8 machine with CentOS-7.3. >The PEX 8619 is used as an NTB (Non-Transparent Bridge). > >First, two DMA buffer are allocated with dma_alloc_coherent() and the >physical address are:

Re: [PATCH] ibmveth: Support to enable LSO/CSO for Trunk VEA.

Let me give some background before I answer your queries. In IBM PowerVM environment, ibmveth driver supports largesend and checksum offload today, but only for virtual ethernet adapters (VEA) which are *not *configured in "Trunk mode". In trunk mode, one cannot enable checksum and largesend

Freescale mpc8315 IRQ0 setup

Dear mailing list, i found out on our platform with freescale mpc8315 SOC that in linux kernel code the setup of IRQ0 which we use is not correct. One should be able to use falling EDGE interrupt capabilities like on IRQ1-IRQ7. These setups are fixed in "arch/powerpc/sysdev/ipic.c" The internal

Re: WARN @lib/refcount.c:128 during hot unplug of I/O adapter.

On 04/06/2017 09:04 PM, Michael Ellerman wrote: > Tyrel Datwyler writes: > >> On 04/06/2017 03:27 AM, Sachin Sant wrote: >>> On a POWER8 LPAR running 4.11.0-rc5, a hot unplug operation on >>> any I/O adapter results in the following warning >>> >>> This problem has

Re: [PATCH v3] powerpc: mm: support ARCH_MMAP_RND_BITS

Hi Michael, On Wed, Mar 29, 2017 at 1:15 AM, Bhupesh Sharma wrote: > powerpc arch_mmap_rnd() currently uses hard-coded values - (23-PAGE_SHIFT) for > 32-bit and (30-PAGE_SHIFT) for 64-bit, to generate the random offset > for the mmap base address for a ASLR ELF. > > This

Re: [PATCH V4 6/7] cxl: Isolate few psl8 specific calls

Le 07/04/2017 à 16:11, Christophe Lombard a écrit : Point out the specific Coherent Accelerator Interface Architecture, level 1, registers. Code and functions specific to PSL8 (CAIA1) must be framed. Signed-off-by: Christophe Lombard --- There are a few changes

Re: [PATCH V4 5/7] cxl: Rename some psl8 specific functions

Le 07/04/2017 à 16:11, Christophe Lombard a écrit : Rename a few functions, changing the '_psl' suffix to '_psl8', to make clear that the implementation is psl8 specific. Those functions will have an equivalent implementation for the psl9 in a later patch. Signed-off-by: Christophe Lombard

Re: [PATCH V4 4/7] cxl: Update implementation service layer

Le 07/04/2017 à 16:11, Christophe Lombard a écrit : The service layer API (in cxl.h) lists some low-level functions whose implementation is different on PSL8, PSL9 and XSL: - Init implementation for the adapter and the afu. - Invalidate TLB/SLB. - Attach process for dedicated/directed models. -

Re: [PATCH V4 3/7] cxl: Keep track of mm struct associated with a context

Le 07/04/2017 à 16:11, Christophe Lombard a écrit : The mm_struct corresponding to the current task is acquired each time an interrupt is raised. So to simplify the code, we only get the mm_struct when attaching an AFU context to the process. The mm_count reference is increased to ensure that

Re: [PATCH V4 2/7] cxl: Remove unused values in bare-metal environment.

Le 07/04/2017 à 16:11, Christophe Lombard a écrit : The two previously fields pid and tid, located in the structure cxl_irq_info, are only used in the guest environment. To avoid confusion, it's not necessary to fill the fields in the bare-metal environment. Pid_tid is now renamed to

Re: [PATCH V4 1/7] cxl: Read vsec perst load image

Le 07/04/2017 à 16:11, Christophe Lombard a écrit : This bit is used to cause a flash image load for programmable CAIA-compliant implementation. If this bit is set to ‘0’, a power cycle of the adapter is required to load a programmable CAIA-com- pliant implementation from flash. This field

Re: [PATCH] ppc64/kprobe: Fix oops when kprobed on 'stdu' instruction

Excerpts from Ravi Bangoria's message of April 10, 2017 20:50: If we set a kprobe on a 'stdu' instruction on powerpc64, we see a kernel OOPS: [ 1275.165932] Bad kernel stack pointer cd93c840 at c0009868 [ 1275.166378] Oops: Bad kernel stack pointer, sig: 6 [#1] ... GPR00:

Re: [PATCH v5 01/15] stacktrace/x86: add function for detecting reliable stack traces

On Mon 2017-02-13 19:42:28, Josh Poimboeuf wrote: > For live patching and possibly other use cases, a stack trace is only > useful if it can be assured that it's completely reliable. Add a new > save_stack_trace_tsk_reliable() function to achieve that. > > Note that if the target task isn't the

[PATCH] ppc64/kprobe: Fix oops when kprobed on 'stdu' instruction

If we set a kprobe on a 'stdu' instruction on powerpc64, we see a kernel OOPS: [ 1275.165932] Bad kernel stack pointer cd93c840 at c0009868 [ 1275.166378] Oops: Bad kernel stack pointer, sig: 6 [#1] ... GPR00: c01fcd93cb30 cd93c840 c15c5e00 cd93c840

Re: [PATCH 2/3] of/fdt: introduce of_scan_flat_dt_subnodes and of_get_flat_dt_phandle

On Mon, Apr 10, 2017 at 12:43 AM, Nicholas Piggin wrote: > On Thu, 6 Apr 2017 09:09:41 -0500 > Rob Herring wrote: > >> On Wed, Apr 5, 2017 at 7:38 PM, Nicholas Piggin wrote: >> > Given that it's quite a small addition to of/fdt code,

EEH error in doing DMA with PEX 8619

Hi all! I am porting PLX driver for PEX 8619 to a power8 machine with CentOS-7.3. The PEX 8619 is used as an NTB (Non-Transparent Bridge). First, two DMA buffer are allocated with dma_alloc_coherent() and the physical address are: src: 0x _6060 dst: 0x _6080 Then, a DMA

[PATCH v10 4/4] PCI: Don't extend device's size when using default alignment for all devices

Currently we reassign the alignment by extending resources' size in pci_reassigndev_resource_alignment(). This could potentially break some drivers when the driver uses the size to locate register whose length is related to the size. Some examples as below: - misc/Hpilo.c: off =

[PATCH v10 3/4] powerpc/powernv: Override pcibios_default_alignment() to force PCI devices to be page aligned

This overrides pcibios_default_alignment() to set default alignment to PAGE_SIZE for all PCI devices on PowerNV platform. Thus sub-page BARs would not share a page and could be mapped into guest when VFIO passthrough them. Signed-off-by: Yongji Xie ---

[PATCH v10 2/4] PCI: Add pcibios_default_alignment() for arch-specific alignment control

When VFIO passes through a PCI device to a guest, it does not allow the guest to mmap BARs that are smaller than PAGE_SIZE unless it can reserve the rest of the page (see vfio_pci_probe_mmaps()). This is because a page might contain several small BARs for unrelated devices and a guest should not

[PATCH v10 1/4] PCI: A fix for caculating bridge window's size and alignment

In case that one device's alignment is greater than its size, we may get an incorrect size and alignment for its bus's memory window in pbus_size_mem(). This patch fixes this case. Signed-off-by: Yongji Xie --- drivers/pci/setup-bus.c |4 ++-- 1 file changed, 2

[PATCH v10 0/4] PCI: Introduce a way to enforce all MMIO BARs not to share PAGE_SIZE

This series introduces a way for PCI resource allocator to force MMIO BARs not to share PAGE_SIZE. This would make sense to VFIO driver. Because current VFIO implementation disallows to mmap sub-page(size < PAGE_SIZE) MMIO BARs which may share the same page with other BARs for security reasons.

Re: [PATCH] powerpc/powernv: Fix powernv Kconfig dependencies

On 04/10/2017 10:54 AM, Alistair Popple wrote: > The patch to introduce address translation services for Nvlink2 uses > MMU notifiers. However usage of MMU notifiers requires a Kconfig > option which is not selected by default on powerpc so add it to the > powernv Kconfig. We would also need this

Re: [PATCH v2] powerpc/eeh: Avoid use after free in eeh_handle_special_event()

On 10/04/17 17:11, Russell Currey wrote: > eeh_handle_special_event() is called when an EEH event is detected but > can't be narrowed down to a specific PE. This function looks through > every PE to find one in an erroneous state, then calls the regular event > handler eeh_handle_normal_event()

Re: kselftest:lost_exception_test failure with 4.11.0-rc5

> On 07-Apr-2017, at 6:06 PM, Michael Ellerman wrote: > > Sachin Sant writes: > >> I have run into few instances where the lost_exception_test from >> powerpc kselftest fails with SIGABRT. Following o/p is against >> 4.11.0-rc5. The failure is

Re: [PATCH v2] powerpc/eeh: Avoid use after free in eeh_handle_special_event()

On 10/04/17 17:11, Russell Currey wrote: eeh_handle_special_event() is called when an EEH event is detected but can't be narrowed down to a specific PE. This function looks through every PE to find one in an erroneous state, then calls the regular event handler eeh_handle_normal_event() once it

Re: [PATCH 3/3] powerpc/64s: cpufeatures: add initial implementation for cpufeatures

On Wed, 5 Apr 2017 22:37:06 +1000 Nicholas Piggin wrote: > The /cpus/features dt binding describes architected CPU features along > with some compatibility, privilege, and enablement properties that allow > flexibility with discovering and enabling capabilities. > > Presence

[PATCH v2] powerpc/eeh: Avoid use after free in eeh_handle_special_event()

eeh_handle_special_event() is called when an EEH event is detected but can't be narrowed down to a specific PE. This function looks through every PE to find one in an erroneous state, then calls the regular event handler eeh_handle_normal_event() once it knows which PE has an error. However, if

Re: [PATCH V4 4/7] cxl: Update implementation service layer

On 08/04/17 00:11, Christophe Lombard wrote: The service layer API (in cxl.h) lists some low-level functions whose implementation is different on PSL8, PSL9 and XSL: - Init implementation for the adapter and the afu. - Invalidate TLB/SLB. - Attach process for dedicated/directed models. -

Re: [v2] raid6/altivec: Add vpermxor implementation for raid6 Q syndrome

Daniel Axtens writes: > Hi Matt, > > Thanks for answering my questions and doing those fixes. > > >> Bugs fixed: >> - A small bug in pq.h regarding a missing and mismatched >>ifdef statement >> - Fixed test/Makefile to correctly build test on ppc >> > > I think

[PATCH v2 3/3] powerpc/xive: Extra sanity checks on cpu numbers

When targetting interrupts we do various manipulations of cpu numbers and CPU masks. This adds some sanity checking to ensure we don't break assumptions and manpulate cpu numbers that are out of bounds of the various cpumasks. Signed-off-by: Benjamin Herrenschmidt ---

[PATCH v2 2/3] powerpx/xive: Fix irq target selection returning out of bounds cpu#

xive_pick_irq_target() first tries to construct a mask that is the intersection of the requested affinity, online CPUs, and the group of CPUs that are on the same chip as the interrupt source. If that resulting mask is empty, we were incorrectly returning nr_cpu_ids as a target. Signed-off-by:

[PATCH v2 1/3] powerpc/xive: Don't call cpu_online() on an invalid CPU number

If the interrupt didn't have a selected target yet, we could call cpu_online() and do other cpumask tests with cpu #-1 which would result in random outcomes. Signed-off-by: Benjamin Herrenschmidt --- arch/powerpc/sysdev/xive/common.c | 3 ++- 1 file changed, 2

[PATCH 2/3] powerpx/xive: Fix irq target selection returning out of bounds cpu#

xive_pick_irq_target() first tries to construct a mask that is the intersection of the requested affinity, online CPUs, and the group of CPUs that are on the same chip as the interrupt source. If that resulting mask is empty, we were incorrectly returning nr_cpu_ids as a target. Signed-off-by:

[PATCH 3/3] powerpc/xive: Extra sanity checks on cpu numbers

When targetting interrupts we do various manipulations of cpu numbers and CPU masks. This adds some sanity checking to ensure we don't break assumptions and manpulate cpu numbers that are out of bounds of the various cpumasks. Signed-off-by: Benjamin Herrenschmidt ---

[PATCH 1/3] powerpc/xive: Don't call cpu_online() on an invalid CPU number

If the interrupt didn't have a selected target yet, we could call cpu_online() and do other cpumask tests with cpu #-1 which would result in random outcomes. Signed-off-by: Benjamin Herrenschmidt --- arch/powerpc/sysdev/xive/common.c | 3 ++- 1 file changed, 2

Re: [PATCH V4 5/7] cxl: Rename some psl8 specific functions

On 08/04/17 00:11, Christophe Lombard wrote: Rename a few functions, changing the '_psl' suffix to '_psl8', to make clear that the implementation is psl8 specific. Those functions will have an equivalent implementation for the psl9 in a later patch. Signed-off-by: Christophe Lombard

[PATCH] powerpc/powernv/pci: Reduce spam when dumping PEST

Dumping the PE State Tables (PEST) can be highly verbose if a number of PEs are affected, especially in the case where the whole PHB is frozen and 255 lines get printed. Check for duplicates when dumping the PEST to reduce useless output. For example: PE[f8] A/B: 9726