Re: Widespread crashes in -next, bisected to 'mm: drop HASH_ADAPT'

[Michael Ellerman]

Guenter Roeck  writes:

> Hi,
>
> my qemu tests of next-20170519 show the following results:
>   total: 122 pass: 30 fail: 92
>
> I won't bother listing all of the failures; they are available at
> http://kerneltests.org/builders. I bisected one (openrisc, because
> it gives me some console output before dying). It points to
> 'mm: drop HASH_ADAPT' as the culprit. Bisect log is attached.
>
> A quick glance suggests that 64 bit kernels pass and 32 bit kernels fail.
> 32-bit x86 images fail and should provide an easy test case.

Yep, 32-bit PPC is also broken. Bisects to this commit.

cheers

Re: [PATCH] powerpc/64: Use tick accounting by default

[Anton Blanchard]

Hi Michael,

> > ppc64 is the only architecture that turns on
> > VIRT_CPU_ACCOUNTING_NATIVE by default. The overhead of this option
> > is extremely high - a context switch microbenchmark using
> > sched_yield() is almost 20% slower.  
> 
> Running on what? It should all be nop'ed out unless you're on a
> platform that needs it (SPLPAR).

POWERNV native. We don't nop out all the vtime_account_* gunk do we? It
is all those functions that are a large part of the problem.

> > To get finer grained user/hardirq/softirq statitics, the
> > IRQ_TIME_ACCOUNTING option can be used instead, which has much lower
> > overhead.  
> 
> Can it? We don't select HAVE_IRQ_TIME_ACCOUNTING, so AFAICS it can't
> be enabled.

I have a separate patch to enable it.

> Doesn't dropping this mean we never count stolen time?

Perhaps. Do we have any applications left that care?

Anton

Re: [PATCH] powerpc/64: Use tick accounting by default

[Nicholas Piggin]

On Mon, 22 May 2017 14:15:57 +1000
Michael Ellerman  wrote:

> Anton Blanchard  writes:
> 
> > From: Anton Blanchard 
> >
> > ppc64 is the only architecture that turns on VIRT_CPU_ACCOUNTING_NATIVE
> > by default. The overhead of this option is extremely high - a context
> > switch microbenchmark using sched_yield() is almost 20% slower.  
> 
> Running on what? It should all be nop'ed out unless you're on a platform
> that needs it (SPLPAR).

Not ACCOUNT_CPU_USER_ENTRY/EXIT, which adds a fair cost to kernel
entry/exit (my notes say ~70 cycles on getppid() out of 3-4 hundred).

> 
> > To get finer grained user/hardirq/softirq statitics, the
> > IRQ_TIME_ACCOUNTING option can be used instead, which has much lower
> > overhead.  
> 
> Can it? We don't select HAVE_IRQ_TIME_ACCOUNTING, so AFAICS it can't be
> enabled.
> 
> Doesn't dropping this mean we never count stolen time?
> 
> cheers

Re: [PATCH 2/2] powerpc: Make feature-fixup tests fortify-safe

[Andrew Donnellan]

On 22/05/17 11:32, Daniel Axtens wrote:

Testing the fortified string functions[1] would cause a kernel
panic on boot in test_feature_fixups() due to a buffer overflow
in memcmp.

This boils down to things like this:

  extern unsigned int ftr_fixup_test1;
  extern unsigned int ftr_fixup_test1_orig;

  check(memcmp(_fixup_test1, _fixup_test1_orig, size) == 0);

We know that these are asm labels so it is safe to read up to
'size' bytes at those addresses.

However, because we have passed the address of a single unsigned
int to memcmp, the compiler believes the underlying object is in
fact a single unsigned int. So if size > sizeof(unsigned int),
there will be a panic at runtime.

We can fix this by changing the types: instead of calling the asm
labels unsigned ints, call them unsigned int[]s. Therefore the
size isn't incorrectly determined at compile time and we get a
regular unsafe memcmp and no panic.

[1] http://openwall.com/lists/kernel-hardening/2017/05/09/2

Suggested-by: Michael Ellerman 
Cc: Kees Cook 
Cc: Daniel Micay 
Signed-off-by: Daniel Axtens 


With this patch on top of Kees' fortify branch, my Tuleta boots 
powernv_defconfig baremetal with no obvious regressions.


Tested-by: Andrew Donnellan 

Patch looks sane enough too.

Reviewed-by: Andrew Donnellan 


--
Andrew Donnellan  OzLabs, ADL Canberra
andrew.donnel...@au1.ibm.com  IBM Australia Limited

Re: [PATCH 1/2] powerpc: Don't fortify prom_init

[Andrew Donnellan]

On 22/05/17 11:32, Daniel Axtens wrote:

prom_init is a bit special; in theory it should be able to be
linked separately to the kernel. To keep this from getting too
complex, the symbols that prom_init.c uses are checked.

Fortification adds symbols, and it gets quite messy as it includes
things like panic(). So just don't fortify prom_init.c for now.

Cc: Kees Cook 
Cc: Daniel Micay 
Signed-off-by: Daniel Axtens 


Reviewed-by: Andrew Donnellan 

--
Andrew Donnellan  OzLabs, ADL Canberra
andrew.donnel...@au1.ibm.com  IBM Australia Limited

Re: [PATCH] KVM: PPC: hypervisor large decrementer support

[Oliver O'Halloran]

Just FYI, this was written over a year ago and never tested since it
pre-dated KVM support on P9. It's possible the real mode KVM bits have
grown an extra decremented usages since then. If so they will probably
need updating to use the GET_DEC() macro.

On Mon, May 22, 2017 at 1:55 PM, Oliver O'Halloran  wrote:
> Power ISAv3 extends the width of the decrementer register from 32 bits.
> The enlarged register width is implementation dependent, but reads from
> these registers are automatically sign extended to produce a 64 bit
> output when operating in large mode. The HDEC always operates in large
> mode while the DEC register can be operated in 32bit mode or large mode
> depending on the setting of the LPCR.LD bit.
>
> Currently the hypervisor assumes that reads from the DEC and HDEC
> register produce a 32 bit result which it sign extends to 64 bits using
> the extsw instruction. This behaviour can result in the guest DEC
> register value being corrupted by the hypervisor when the guest is
> operating in LD mode since the results of the extsw instruction only
> depends on the value of bit 31 in the register to be sign extended.
>
> This patch adds the GET_DEC() and GET_HDEC() assembly macros for reading
> from the decrementer registers. These macros will return the current
> decrementer value as a 64 bit quantity regardless of the Host CPU or
> guest decrementer operating mode. Additionally this patch corrects
> several uses of decrementer values that assume a 32 bit register width.
>
> Signed-off-by: Oliver O'Halloran 
> Cc: Paul Mackerras 
> Cc: Michael Neuling 
> ---
>  arch/powerpc/include/asm/exception-64s.h | 29 
>  arch/powerpc/include/asm/kvm_host.h  |  2 +-
>  arch/powerpc/include/asm/kvm_ppc.h   |  2 +-
>  arch/powerpc/include/uapi/asm/kvm.h  |  2 +-
>  arch/powerpc/kvm/book3s_hv_interrupts.S  |  3 +--
>  arch/powerpc/kvm/book3s_hv_rmhandlers.S  | 38 
> ++--
>  arch/powerpc/kvm/emulate.c   |  6 ++---
>  7 files changed, 57 insertions(+), 25 deletions(-)
>
> diff --git a/arch/powerpc/include/asm/exception-64s.h 
> b/arch/powerpc/include/asm/exception-64s.h
> index 93ae809fe5ea..4fa303bf6d5b 100644
> --- a/arch/powerpc/include/asm/exception-64s.h
> +++ b/arch/powerpc/include/asm/exception-64s.h
> @@ -545,4 +545,33 @@ END_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP)
>  #define FINISH_NAP
>  #endif
>
> +/*
> + * On ISAv3 processors the DEC register can be extended from 32 bits to 64 by
> + * setting the LD flag the LPCR. The decrementer value is a signed quantity 
> so
> + * sign exension is required when operating in 32 bit mode. The GET_DEC() and
> + * GET_HDEC() handle this sign extension and yield a 64 bit result 
> independent
> + * of the LD mode.
> + *
> + * NB: It's possible run with LD mode disabled on ISAv3 so GET_DEC() does not
> + * use a CPU_FEATURE section. A feature section is used for GET_HDEC 
> because
> + * it has no mode bit. It is always 64 bits for ISAv3 processors.
> + */
> +
> +#define IS_LD_ENABLED(reg) \
> +   mfspr  reg,SPRN_LPCR;  \
> +   andis. reg,reg,(LPCR_LD >> 16);
> +
> +#define GET_DEC(reg)   \
> +   IS_LD_ENABLED(reg);\
> +   mfspr reg, SPRN_DEC;   \
> +   bne 99f;   \
> +   extsw reg, reg;\
> +99:
> +
> +#define GET_HDEC(reg) \
> +   mfspr reg, SPRN_HDEC;   \
> +BEGIN_FTR_SECTION   \
> +   extsw reg, reg; \
> +END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300)
> +
>  #endif /* _ASM_POWERPC_EXCEPTION_H */
> diff --git a/arch/powerpc/include/asm/kvm_host.h 
> b/arch/powerpc/include/asm/kvm_host.h
> index ec35af34a3fb..ddea233e2cce 100644
> --- a/arch/powerpc/include/asm/kvm_host.h
> +++ b/arch/powerpc/include/asm/kvm_host.h
> @@ -520,7 +520,7 @@ struct kvm_vcpu_arch {
> ulong mcsrr0;
> ulong mcsrr1;
> ulong mcsr;
> -   u32 dec;
> +   u64 dec;
>  #ifdef CONFIG_BOOKE
> u32 decar;
>  #endif
> diff --git a/arch/powerpc/include/asm/kvm_ppc.h 
> b/arch/powerpc/include/asm/kvm_ppc.h
> index 2544edabe7f3..4de0102930e9 100644
> --- a/arch/powerpc/include/asm/kvm_ppc.h
> +++ b/arch/powerpc/include/asm/kvm_ppc.h
> @@ -94,7 +94,7 @@ extern int kvmppc_emulate_instruction(struct kvm_run *run,
>  extern int kvmppc_emulate_loadstore(struct kvm_vcpu *vcpu);
>  extern int kvmppc_emulate_mmio(struct kvm_run *run, struct kvm_vcpu *vcpu);
>  extern void kvmppc_emulate_dec(struct kvm_vcpu *vcpu);
> -extern u32 kvmppc_get_dec(struct kvm_vcpu *vcpu, u64 tb);
> +extern u64 kvmppc_get_dec(struct kvm_vcpu *vcpu, u64 tb);
>  extern void kvmppc_decrementer_func(struct kvm_vcpu *vcpu);
>  extern int kvmppc_sanity_check(struct kvm_vcpu *vcpu);
>  extern int kvmppc_subarch_vcpu_init(struct kvm_vcpu *vcpu);
> diff --git 

Re: [PATCH] powerpc/64: Use tick accounting by default

[Michael Ellerman]

Anton Blanchard  writes:

> From: Anton Blanchard 
>
> ppc64 is the only architecture that turns on VIRT_CPU_ACCOUNTING_NATIVE
> by default. The overhead of this option is extremely high - a context
> switch microbenchmark using sched_yield() is almost 20% slower.

Running on what? It should all be nop'ed out unless you're on a platform
that needs it (SPLPAR).

> To get finer grained user/hardirq/softirq statitics, the
> IRQ_TIME_ACCOUNTING option can be used instead, which has much lower
> overhead.

Can it? We don't select HAVE_IRQ_TIME_ACCOUNTING, so AFAICS it can't be
enabled.

Doesn't dropping this mean we never count stolen time?

cheers

Re: [RFC][PATCH] powerpc/64s: stop using r14 register

[Michael Ellerman]

Nicholas Piggin  writes:

> On Mon, 22 May 2017 08:09:19 +1000
> Benjamin Herrenschmidt  wrote:
>
>> On Mon, 2017-05-22 at 00:00 +1000, Nicholas Piggin wrote:
>> > I'd like to take over the r14 register for use as a per-cpu kernel
>> > register similar to the way r13 is used for the paca.  
>> 
>> Why not use r13 instead ? We don't need to access the PACA that often
>> from C code, I thought we could flip them...
>
> It ended up being a bit too tricky to do it that way. We can't get
> directly to per-CPU data from the per-cpu data offset in exception
> entry code for a number of reasons. So we end up having to load the
> paca first.
>
> I looked at swapping r13 from paca to per-cpu offset at the same
> time the stack is set up, so paca is used for early save areas then
> per-cpu is used in C code. In practice it ended up getting too
> tricky and fragile dealing with nested interrupts, machine checks,
> etc.
>
> I think it's something we might slowly work towards (consolidating
> back to one fixed register), but as things are it didn't work well.

Yep, agree 100%.

We've talked about flipping r13 for 10 years, rather than spending
another 10 this is a good way to evolve things in the right direction.

cheers

[PATCH] KVM: PPC: hypervisor large decrementer support

[Oliver O'Halloran]

Power ISAv3 extends the width of the decrementer register from 32 bits.
The enlarged register width is implementation dependent, but reads from
these registers are automatically sign extended to produce a 64 bit
output when operating in large mode. The HDEC always operates in large
mode while the DEC register can be operated in 32bit mode or large mode
depending on the setting of the LPCR.LD bit.

Currently the hypervisor assumes that reads from the DEC and HDEC
register produce a 32 bit result which it sign extends to 64 bits using
the extsw instruction. This behaviour can result in the guest DEC
register value being corrupted by the hypervisor when the guest is
operating in LD mode since the results of the extsw instruction only
depends on the value of bit 31 in the register to be sign extended.

This patch adds the GET_DEC() and GET_HDEC() assembly macros for reading
from the decrementer registers. These macros will return the current
decrementer value as a 64 bit quantity regardless of the Host CPU or
guest decrementer operating mode. Additionally this patch corrects
several uses of decrementer values that assume a 32 bit register width.

Signed-off-by: Oliver O'Halloran 
Cc: Paul Mackerras 
Cc: Michael Neuling 
---
 arch/powerpc/include/asm/exception-64s.h | 29 
 arch/powerpc/include/asm/kvm_host.h  |  2 +-
 arch/powerpc/include/asm/kvm_ppc.h   |  2 +-
 arch/powerpc/include/uapi/asm/kvm.h  |  2 +-
 arch/powerpc/kvm/book3s_hv_interrupts.S  |  3 +--
 arch/powerpc/kvm/book3s_hv_rmhandlers.S  | 38 ++--
 arch/powerpc/kvm/emulate.c   |  6 ++---
 7 files changed, 57 insertions(+), 25 deletions(-)

diff --git a/arch/powerpc/include/asm/exception-64s.h 
b/arch/powerpc/include/asm/exception-64s.h
index 93ae809fe5ea..4fa303bf6d5b 100644
--- a/arch/powerpc/include/asm/exception-64s.h
+++ b/arch/powerpc/include/asm/exception-64s.h
@@ -545,4 +545,33 @@ END_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP)
 #define FINISH_NAP
 #endif
 
+/*
+ * On ISAv3 processors the DEC register can be extended from 32 bits to 64 by
+ * setting the LD flag the LPCR. The decrementer value is a signed quantity so
+ * sign exension is required when operating in 32 bit mode. The GET_DEC() and
+ * GET_HDEC() handle this sign extension and yield a 64 bit result independent
+ * of the LD mode.
+ *
+ * NB: It's possible run with LD mode disabled on ISAv3 so GET_DEC() does not
+ * use a CPU_FEATURE section. A feature section is used for GET_HDEC 
because
+ * it has no mode bit. It is always 64 bits for ISAv3 processors.
+ */
+
+#define IS_LD_ENABLED(reg) \
+   mfspr  reg,SPRN_LPCR;  \
+   andis. reg,reg,(LPCR_LD >> 16);
+
+#define GET_DEC(reg)   \
+   IS_LD_ENABLED(reg);\
+   mfspr reg, SPRN_DEC;   \
+   bne 99f;   \
+   extsw reg, reg;\
+99:
+
+#define GET_HDEC(reg) \
+   mfspr reg, SPRN_HDEC;   \
+BEGIN_FTR_SECTION   \
+   extsw reg, reg; \
+END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300)
+
 #endif /* _ASM_POWERPC_EXCEPTION_H */
diff --git a/arch/powerpc/include/asm/kvm_host.h 
b/arch/powerpc/include/asm/kvm_host.h
index ec35af34a3fb..ddea233e2cce 100644
--- a/arch/powerpc/include/asm/kvm_host.h
+++ b/arch/powerpc/include/asm/kvm_host.h
@@ -520,7 +520,7 @@ struct kvm_vcpu_arch {
ulong mcsrr0;
ulong mcsrr1;
ulong mcsr;
-   u32 dec;
+   u64 dec;
 #ifdef CONFIG_BOOKE
u32 decar;
 #endif
diff --git a/arch/powerpc/include/asm/kvm_ppc.h 
b/arch/powerpc/include/asm/kvm_ppc.h
index 2544edabe7f3..4de0102930e9 100644
--- a/arch/powerpc/include/asm/kvm_ppc.h
+++ b/arch/powerpc/include/asm/kvm_ppc.h
@@ -94,7 +94,7 @@ extern int kvmppc_emulate_instruction(struct kvm_run *run,
 extern int kvmppc_emulate_loadstore(struct kvm_vcpu *vcpu);
 extern int kvmppc_emulate_mmio(struct kvm_run *run, struct kvm_vcpu *vcpu);
 extern void kvmppc_emulate_dec(struct kvm_vcpu *vcpu);
-extern u32 kvmppc_get_dec(struct kvm_vcpu *vcpu, u64 tb);
+extern u64 kvmppc_get_dec(struct kvm_vcpu *vcpu, u64 tb);
 extern void kvmppc_decrementer_func(struct kvm_vcpu *vcpu);
 extern int kvmppc_sanity_check(struct kvm_vcpu *vcpu);
 extern int kvmppc_subarch_vcpu_init(struct kvm_vcpu *vcpu);
diff --git a/arch/powerpc/include/uapi/asm/kvm.h 
b/arch/powerpc/include/uapi/asm/kvm.h
index c93cf35ce379..2dd92e841127 100644
--- a/arch/powerpc/include/uapi/asm/kvm.h
+++ b/arch/powerpc/include/uapi/asm/kvm.h
@@ -215,7 +215,7 @@ struct kvm_sregs {
__u32 tsr;  /* KVM_SREGS_E_UPDATE_TSR */
__u32 tcr;
__u32 decar;
-   __u32 dec;  /* KVM_SREGS_E_UPDATE_DEC */
+   __u64 dec;  /* KVM_SREGS_E_UPDATE_DEC */
 
/*
  

[PATCH 0/2] powerpc: fortify support

[Daniel Axtens]

This series provides arch-specific support for Daniel Micay's
fortified string functions on powerpc.

Fortified string functions provied some compile and run time bounds
checking on commonly used string functions.

It's cool - currently it picks up a lot of random things so it will
require some more work across the tree, but hopefully it will
eventually hit mainline. These patches make powerpc ready for when it
does.

They've been tested on pseries.

I think patch 1 should probably go through Kees to line up with the
fortify patch itself, but patch 2 can apply to powerpc as is. But up
to you, mpe.

Regards,
Daniel

Daniel Axtens (2):
  powerpc: Don't fortify prom_init
  powerpc: Make feature-fixup tests fortify-safe

 arch/powerpc/kernel/prom_init.c   |   3 +
 arch/powerpc/lib/feature-fixups.c | 180 +++---
 2 files changed, 93 insertions(+), 90 deletions(-)

-- 
2.11.0

[PATCH 2/2] powerpc: Make feature-fixup tests fortify-safe

[Daniel Axtens]

Testing the fortified string functions[1] would cause a kernel
panic on boot in test_feature_fixups() due to a buffer overflow
in memcmp.

This boils down to things like this:

  extern unsigned int ftr_fixup_test1;
  extern unsigned int ftr_fixup_test1_orig;

  check(memcmp(_fixup_test1, _fixup_test1_orig, size) == 0);

We know that these are asm labels so it is safe to read up to
'size' bytes at those addresses.

However, because we have passed the address of a single unsigned
int to memcmp, the compiler believes the underlying object is in
fact a single unsigned int. So if size > sizeof(unsigned int),
there will be a panic at runtime.

We can fix this by changing the types: instead of calling the asm
labels unsigned ints, call them unsigned int[]s. Therefore the
size isn't incorrectly determined at compile time and we get a
regular unsafe memcmp and no panic.

[1] http://openwall.com/lists/kernel-hardening/2017/05/09/2

Suggested-by: Michael Ellerman 
Cc: Kees Cook 
Cc: Daniel Micay 
Signed-off-by: Daniel Axtens 
---
 arch/powerpc/lib/feature-fixups.c | 180 +++---
 1 file changed, 90 insertions(+), 90 deletions(-)

diff --git a/arch/powerpc/lib/feature-fixups.c 
b/arch/powerpc/lib/feature-fixups.c
index f3917705c686..41cf5ae273cf 100644
--- a/arch/powerpc/lib/feature-fixups.c
+++ b/arch/powerpc/lib/feature-fixups.c
@@ -233,192 +233,192 @@ static long calc_offset(struct fixup_entry *entry, 
unsigned int *p)
 
 static void test_basic_patching(void)
 {
-   extern unsigned int ftr_fixup_test1;
-   extern unsigned int end_ftr_fixup_test1;
-   extern unsigned int ftr_fixup_test1_orig;
-   extern unsigned int ftr_fixup_test1_expected;
-   int size = _ftr_fixup_test1 - _fixup_test1;
+   extern unsigned int ftr_fixup_test1[];
+   extern unsigned int end_ftr_fixup_test1[];
+   extern unsigned int ftr_fixup_test1_orig[];
+   extern unsigned int ftr_fixup_test1_expected[];
+   int size = end_ftr_fixup_test1 - ftr_fixup_test1;
 
fixup.value = fixup.mask = 8;
-   fixup.start_off = calc_offset(, _fixup_test1 + 1);
-   fixup.end_off = calc_offset(, _fixup_test1 + 2);
+   fixup.start_off = calc_offset(, ftr_fixup_test1 + 1);
+   fixup.end_off = calc_offset(, ftr_fixup_test1 + 2);
fixup.alt_start_off = fixup.alt_end_off = 0;
 
/* Sanity check */
-   check(memcmp(_fixup_test1, _fixup_test1_orig, size) == 0);
+   check(memcmp(ftr_fixup_test1, ftr_fixup_test1_orig, size) == 0);
 
/* Check we don't patch if the value matches */
patch_feature_section(8, );
-   check(memcmp(_fixup_test1, _fixup_test1_orig, size) == 0);
+   check(memcmp(ftr_fixup_test1, ftr_fixup_test1_orig, size) == 0);
 
/* Check we do patch if the value doesn't match */
patch_feature_section(0, );
-   check(memcmp(_fixup_test1, _fixup_test1_expected, size) == 0);
+   check(memcmp(ftr_fixup_test1, ftr_fixup_test1_expected, size) == 0);
 
/* Check we do patch if the mask doesn't match */
-   memcpy(_fixup_test1, _fixup_test1_orig, size);
-   check(memcmp(_fixup_test1, _fixup_test1_orig, size) == 0);
+   memcpy(ftr_fixup_test1, ftr_fixup_test1_orig, size);
+   check(memcmp(ftr_fixup_test1, ftr_fixup_test1_orig, size) == 0);
patch_feature_section(~8, );
-   check(memcmp(_fixup_test1, _fixup_test1_expected, size) == 0);
+   check(memcmp(ftr_fixup_test1, ftr_fixup_test1_expected, size) == 0);
 }
 
 static void test_alternative_patching(void)
 {
-   extern unsigned int ftr_fixup_test2;
-   extern unsigned int end_ftr_fixup_test2;
-   extern unsigned int ftr_fixup_test2_orig;
-   extern unsigned int ftr_fixup_test2_alt;
-   extern unsigned int ftr_fixup_test2_expected;
-   int size = _ftr_fixup_test2 - _fixup_test2;
+   extern unsigned int ftr_fixup_test2[];
+   extern unsigned int end_ftr_fixup_test2[];
+   extern unsigned int ftr_fixup_test2_orig[];
+   extern unsigned int ftr_fixup_test2_alt[];
+   extern unsigned int ftr_fixup_test2_expected[];
+   int size = end_ftr_fixup_test2 - ftr_fixup_test2;
 
fixup.value = fixup.mask = 0xF;
-   fixup.start_off = calc_offset(, _fixup_test2 + 1);
-   fixup.end_off = calc_offset(, _fixup_test2 + 2);
-   fixup.alt_start_off = calc_offset(, _fixup_test2_alt);
-   fixup.alt_end_off = calc_offset(, _fixup_test2_alt + 1);
+   fixup.start_off = calc_offset(, ftr_fixup_test2 + 1);
+   fixup.end_off = calc_offset(, ftr_fixup_test2 + 2);
+   fixup.alt_start_off = calc_offset(, ftr_fixup_test2_alt);
+   fixup.alt_end_off = calc_offset(, ftr_fixup_test2_alt + 1);
 
/* Sanity check */
-   check(memcmp(_fixup_test2, _fixup_test2_orig, size) == 0);
+   check(memcmp(ftr_fixup_test2, ftr_fixup_test2_orig, size) == 0);
 
/* Check we don't patch 

[PATCH 1/2] powerpc: Don't fortify prom_init

[Daniel Axtens]

prom_init is a bit special; in theory it should be able to be
linked separately to the kernel. To keep this from getting too
complex, the symbols that prom_init.c uses are checked.

Fortification adds symbols, and it gets quite messy as it includes
things like panic(). So just don't fortify prom_init.c for now.

Cc: Kees Cook 
Cc: Daniel Micay 
Signed-off-by: Daniel Axtens 

---

This will need to go in before the main fortify support, but it
doesn't make any sense in the absence of fortify. I think it would
make most sense for Kees to queue this up with the main fortify patch,
with an Ack from mpe?

---
 arch/powerpc/kernel/prom_init.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/powerpc/kernel/prom_init.c b/arch/powerpc/kernel/prom_init.c
index dd8a04f3053a..613f79f03877 100644
--- a/arch/powerpc/kernel/prom_init.c
+++ b/arch/powerpc/kernel/prom_init.c
@@ -15,6 +15,9 @@
 
 #undef DEBUG_PROM
 
+/* we cannot use FORTIFY as it brings in new symbols */
+#define __NO_FORTIFY
+
 #include 
 #include 
 #include 
-- 
2.11.0

Re: [RFC][PATCH] powerpc/64s: stop using r14 register

[Nicholas Piggin]

On Mon, 22 May 2017 08:09:19 +1000
Benjamin Herrenschmidt  wrote:

> On Mon, 2017-05-22 at 00:00 +1000, Nicholas Piggin wrote:
> > I'd like to take over the r14 register for use as a per-cpu kernel
> > register similar to the way r13 is used for the paca.  
> 
> Why not use r13 instead ? We don't need to access the PACA that often
> from C code, I thought we could flip them...

It ended up being a bit too tricky to do it that way. We can't get
directly to per-CPU data from the per-cpu data offset in exception
entry code for a number of reasons. So we end up having to load the
paca first.

I looked at swapping r13 from paca to per-cpu offset at the same
time the stack is set up, so paca is used for early save areas then
per-cpu is used in C code. In practice it ended up getting too
tricky and fragile dealing with nested interrupts, machine checks,
etc.

I think it's something we might slowly work towards (consolidating
back to one fixed register), but as things are it didn't work well.

It's easy to drop the fixed r14 in future if we can. None of the
incidental asm users of r14 were complicating them by moving them
to another register.

Thanks,
Nick

Re: [PATCH] powerpc: add PPC_FEATURE userspace bits for SCV and DARN instructions

[Benjamin Herrenschmidt]

On Sat, 2017-05-20 at 14:29 +1000, Nicholas Piggin wrote:
> Providing "scv" support to userspace requires kernel support, so it
> must be advertised as independently to the base ISA 3 instruction set.
> 
> The darn instruction relies on firmware enablement, so it has been
> decided to split this out from the core ISA 3 feature as well.
> 
> Signed-off-by: Nicholas Piggin 

Acked-by: Benjamin Herrenschmidt 

> ---
> These uapi changes have been agreed by powerpc toolchain and firmware
> teams. I believe this completes our anticipated requirements for user
> feature advertisement for ISA v3.0B.
> 
>  arch/powerpc/include/uapi/asm/cputable.h | 2 ++
>  arch/powerpc/kernel/cputable.c   | 3 ++-
>  2 files changed, 4 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/powerpc/include/uapi/asm/cputable.h 
> b/arch/powerpc/include/uapi/asm/cputable.h
> index 3e7ce86d5c13..4d877144f377 100644
> --- a/arch/powerpc/include/uapi/asm/cputable.h
> +++ b/arch/powerpc/include/uapi/asm/cputable.h
> @@ -46,6 +46,8 @@
>  #define PPC_FEATURE2_HTM_NOSC0x0100
>  #define PPC_FEATURE2_ARCH_3_00   0x0080 /* ISA 3.00 */
>  #define PPC_FEATURE2_HAS_IEEE128 0x0040 /* VSX IEEE Binary Float 
> 128-bit */
> +#define PPC_FEATURE2_DARN0x0020 /* darn random number insn */
> +#define PPC_FEATURE2_SCV 0x0010 /* scv syscall */
>  
>  /*
>   * IMPORTANT!
> diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c
> index 9b3e88b1a9c8..6f849832a669 100644
> --- a/arch/powerpc/kernel/cputable.c
> +++ b/arch/powerpc/kernel/cputable.c
> @@ -124,7 +124,8 @@ extern void __restore_cpu_e6500(void);
>  #define COMMON_USER_POWER9   COMMON_USER_POWER8
>  #define COMMON_USER2_POWER9  (COMMON_USER2_POWER8 | \
>PPC_FEATURE2_ARCH_3_00 | \
> -  PPC_FEATURE2_HAS_IEEE128)
> +  PPC_FEATURE2_HAS_IEEE128 | \
> +  PPC_FEATURE2_DARN )
>  
>  #ifdef CONFIG_PPC_BOOK3E_64
>  #define COMMON_USER_BOOKE(COMMON_USER_PPC64 | PPC_FEATURE_BOOKE)

Re: [RFC][PATCH] powerpc/64s: stop using r14 register

[Benjamin Herrenschmidt]

On Mon, 2017-05-22 at 00:00 +1000, Nicholas Piggin wrote:
> I'd like to take over the r14 register for use as a per-cpu kernel
> register similar to the way r13 is used for the paca.

Why not use r13 instead ? We don't need to access the PACA that often
from C code, I thought we could flip them...

> r14 being the last non-volatile register gcc allocates, appears with
> about 0.5% the frequency as r31 in (static) instructions. I haven't
> counted dynamically how many extra spills and fills that removing it
> causes, but I should. My guess is the memory ops saved by using
> it as a per-cpu variable will significantly outweigh the cost of
> losing it as a general use register.
> 
> This part of the patch is pretty mechanical. A couple of places (prom)
> still have to use it, and I haven't quite understood the KVM code yet.
> 
> Question is whether this approach seems okay, and whether we should do
> the same for 64e.
> 
> Thanks,
> Nick
> 
> ---
>  arch/powerpc/Makefile  |   1 +
>  arch/powerpc/crypto/md5-asm.S  |  40 +++
>  arch/powerpc/crypto/sha1-powerpc-asm.S |  10 +-
>  arch/powerpc/include/asm/ppc_asm.h |  21 +++-
>  arch/powerpc/kernel/asm-offsets.c  |   4 +-
>  arch/powerpc/kernel/entry_32.S |   4 +-
>  arch/powerpc/kernel/entry_64.S |  46 
>  arch/powerpc/kernel/exceptions-64s.S   |   3 +-
>  arch/powerpc/kernel/head_64.S  |   8 +-
>  arch/powerpc/kernel/idle_book3s.S  |  88 +++---
>  arch/powerpc/kernel/process.c  |   4 +-
>  arch/powerpc/kernel/tm.S   |  30 ++---
>  arch/powerpc/kernel/trace/ftrace_64_mprofile.S |   4 +-
>  arch/powerpc/kvm/book3s_hv_interrupts.S|   5 +-
>  arch/powerpc/lib/checksum_64.S |  66 +--
>  arch/powerpc/lib/copypage_power7.S |  32 +++---
>  arch/powerpc/lib/copyuser_power7.S | 152 
> -
>  arch/powerpc/lib/crtsavres.S   |   3 +
>  arch/powerpc/lib/memcpy_power7.S   |  80 ++---
>  arch/powerpc/net/bpf_jit32.h   |  12 +-
>  arch/powerpc/net/bpf_jit_asm.S |   4 +-
>  21 files changed, 321 insertions(+), 296 deletions(-)
> 
> diff --git a/arch/powerpc/Makefile b/arch/powerpc/Makefile
> index bc4791aecd03..4c3492851fab 100644
> --- a/arch/powerpc/Makefile
> +++ b/arch/powerpc/Makefile
> @@ -137,6 +137,7 @@ endif
>  
>  CFLAGS-$(CONFIG_PPC64)   += $(call cc-option,-mcmodel=medium,$(call 
> cc-option,-mminimal-toc))
>  CFLAGS-$(CONFIG_PPC64)   += $(call 
> cc-option,-mno-pointers-to-nested-functions)
> +CFLAGS-$(CONFIG_PPC64)   += -ffixed-r13 -ffixed-r14
>  CFLAGS-$(CONFIG_PPC32)   := -ffixed-r2 $(MULTIPLEWORD)
>  
>  ifeq ($(CONFIG_PPC_BOOK3S_64),y)
> diff --git a/arch/powerpc/crypto/md5-asm.S b/arch/powerpc/crypto/md5-asm.S
> index 10cdf5bceebb..99e41af88e19 100644
> --- a/arch/powerpc/crypto/md5-asm.S
> +++ b/arch/powerpc/crypto/md5-asm.S
> @@ -25,31 +25,31 @@
>  #define rW02 r10
>  #define rW03 r11
>  #define rW04 r12
> -#define rW05 r14
> -#define rW06 r15
> -#define rW07 r16
> -#define rW08 r17
> -#define rW09 r18
> -#define rW10 r19
> -#define rW11 r20
> -#define rW12 r21
> -#define rW13 r22
> -#define rW14 r23
> -#define rW15 r24
> -
> -#define rT0  r25
> -#define rT1  r26
> +#define rW05 r15
> +#define rW06 r16
> +#define rW07 r17
> +#define rW08 r18
> +#define rW09 r19
> +#define rW10 r20
> +#define rW11 r21
> +#define rW12 r22
> +#define rW13 r23
> +#define rW14 r24
> +#define rW15 r25
> +
> +#define rT0  r26
> +#define rT1  r27
>  
>  #define INITIALIZE \
>   PPC_STLU r1,-INT_FRAME_SIZE(r1); \
> - SAVE_8GPRS(14, r1); /* push registers onto stack*/ \
> - SAVE_4GPRS(22, r1);\
> - SAVE_GPR(26, r1)
> + SAVE_8GPRS(15, r1); /* push registers onto stack*/ \
> + SAVE_4GPRS(23, r1);\
> + SAVE_GPR(27, r1)
>  
>  #define FINALIZE \
> - REST_8GPRS(14, r1); /* pop registers from stack */ \
> - REST_4GPRS(22, r1);\
> - REST_GPR(26, r1);  \
> + REST_8GPRS(15, r1); /* pop registers from stack */ \
> + REST_4GPRS(23, r1);\
> + REST_GPR(27, r1);  \
>   addir1,r1,INT_FRAME_SIZE;
>  
>  #ifdef __BIG_ENDIAN__
> diff --git a/arch/powerpc/crypto/sha1-powerpc-asm.S 
> b/arch/powerpc/crypto/sha1-powerpc-asm.S
> index 82ddc9bdfeb1..56bc6ac942c6 100644
> --- a/arch/powerpc/crypto/sha1-powerpc-asm.S
> +++ b/arch/powerpc/crypto/sha1-powerpc-asm.S
> @@ -41,10 +41,10 @@
>   or  r6,r6,r0;   \
>   add 

Re: [PATCH 2/9] timers: provide a "modern" variant of timers

[Al Viro]

On Sun, May 21, 2017 at 07:57:53PM +0200, Thomas Gleixner wrote:
> On Thu, 18 May 2017, Christoph Hellwig wrote:
> > On Thu, May 18, 2017 at 10:24:48AM +0200, Christoph Hellwig wrote:
> > > > b) give the union a name (breaks any reference to timer_list->func in C 
> > > > code):
> > > > 
> > > >  +   union {
> > > >  +   void(*func)(struct timer_list *timer);
> > > >  +   void(*function)(unsigned long);
> > > >  +   } u;
> > > 
> > > I'll look into that, as it seems a lot safer, and places outside
> > > the timer code shouldn't really touch it (although I bet they do,
> > > so more fixes for this series..)
> > 
> > Meh.  All the old init_timer users set function directly, so
> > I guess we need to use the other approach.
> 
> There is another possibility. Create a coccinelle script which wraps all
> 
>   timer.function = f;
>   timer->function = f;
> 
> assignements into a helper timer_set_function(timer, func) and ask Linus to
> run it right before the next -rc. That handles everything in tree and the
> few new instances in next can be addressed with patches sent to the
> maintainers.

FWIW, there was another possible approach - I toyed with that several years
ago, but it didn't go anywhere.  Namely, make timer.function take void *
*and* turn the setup part into setup(timer, callback, argument), verifying
that
* callback(argument) will be acceptable expression for C typechecking
* callback returns void
* argument is a pointer type
then cast callback to void (*)(void *) and argument to void *.  That way
we get rid of any boilerplate in callbacks and get sane typechecking...

Re: RFC: better timer interface

[Thomas Gleixner]

On Sun, 21 May 2017, Thomas Gleixner wrote:
> On Tue, 16 May 2017, Arnd Bergmann wrote:
> > On Tue, May 16, 2017 at 5:51 PM, Christoph Hellwig  wrote:
> > > Yes, that sounds useful to me as well.  As you said it's an independent
> > > but somewhat related change.  I can add it to my series, but I'll
> > > need a suggestions for a good and short name.  That already was the
> > > hardest part for the setup side :)
> > 
> > If we keep the unusual *_timer() naming (rather than timer_*() as hrtimer
> > has), we could use one of
> > 
> > a) start_timer(struct timer_list *timer, unsigned long ms);
> > b) restart_timer(struct timer_list *timer, unsigned long ms);
> > c) mod_timer_ms(struct timer_list *timer, unsigned long ms);
> > mod_timer_sec(struct timer_list *timer, unsigned long sec);
> 
> Please make new functions prefixed with timer_ and get rid of that old
> interface completely. It's horrible.
>  
> timer_init()
> timer_start(timer, ms, abs)

I'm not even sure, whether we need absolute timer wheel timers at
all, because most use cases are relative to now.

But it's easy enough to provide them. All we need for that is something
like

unsigned long time_msec;

which gets incremented every tick by the appropriate amount of
milliseconds.

Having that would also allow to replace all the

   end = jiffies + msec_to_jiffies(xxx);

   while (time_before(jiffies, end))
 

constructs with a milliseconds based machinery. So we can remove all
*_to_jiffies() interfaces over time.

Thanks,

tglx

Re: [PATCH 2/9] timers: provide a "modern" variant of timers

[Thomas Gleixner]

On Thu, 18 May 2017, Christoph Hellwig wrote:
> On Thu, May 18, 2017 at 10:24:48AM +0200, Christoph Hellwig wrote:
> > > b) give the union a name (breaks any reference to timer_list->func in C 
> > > code):
> > > 
> > >  +   union {
> > >  +   void(*func)(struct timer_list *timer);
> > >  +   void(*function)(unsigned long);
> > >  +   } u;
> > 
> > I'll look into that, as it seems a lot safer, and places outside
> > the timer code shouldn't really touch it (although I bet they do,
> > so more fixes for this series..)
> 
> Meh.  All the old init_timer users set function directly, so
> I guess we need to use the other approach.

There is another possibility. Create a coccinelle script which wraps all

  timer.function = f;
  timer->function = f;

assignements into a helper timer_set_function(timer, func) and ask Linus to
run it right before the next -rc. That handles everything in tree and the
few new instances in next can be addressed with patches sent to the
maintainers.

Thanks,

tglx




  

Re: [PATCH net-next v2] ibmveth: Support to enable LSO/CSO for Trunk VEA.

[David Miller]

From: Sivakumar Krishnasamy 
Date: Fri, 19 May 2017 05:30:38 -0400

 ...
> Signed-off-by: Sivakumar Krishnasamy 

Applied, thanks for the more detailed commit message.

Re: RFC: better timer interface

[Thomas Gleixner]

On Tue, 16 May 2017, Arnd Bergmann wrote:
> On Tue, May 16, 2017 at 5:51 PM, Christoph Hellwig  wrote:
> > Yes, that sounds useful to me as well.  As you said it's an independent
> > but somewhat related change.  I can add it to my series, but I'll
> > need a suggestions for a good and short name.  That already was the
> > hardest part for the setup side :)
> 
> If we keep the unusual *_timer() naming (rather than timer_*() as hrtimer
> has), we could use one of
> 
> a) start_timer(struct timer_list *timer, unsigned long ms);
> b) restart_timer(struct timer_list *timer, unsigned long ms);
> c) mod_timer_ms(struct timer_list *timer, unsigned long ms);
> mod_timer_sec(struct timer_list *timer, unsigned long sec);

Please make new functions prefixed with timer_ and get rid of that old
interface completely. It's horrible.
 
timer_init()
timer_start(timer, ms, abs)
timer_start_on(timer, ms, abs, cpu)
timer_cancel(timer, sync)

Is all what's required to make up a new milliseconds based interface.

We really do not need all that mod/restart/ whatever variants. Where is the
point of those?

Thanks,

tglx

[RFC][PATCH] powerpc/64s: stop using r14 register

[Nicholas Piggin]

I'd like to take over the r14 register for use as a per-cpu kernel
register similar to the way r13 is used for the paca.

r14 being the last non-volatile register gcc allocates, appears with
about 0.5% the frequency as r31 in (static) instructions. I haven't
counted dynamically how many extra spills and fills that removing it
causes, but I should. My guess is the memory ops saved by using
it as a per-cpu variable will significantly outweigh the cost of
losing it as a general use register.

This part of the patch is pretty mechanical. A couple of places (prom)
still have to use it, and I haven't quite understood the KVM code yet.

Question is whether this approach seems okay, and whether we should do
the same for 64e.

Thanks,
Nick

---
 arch/powerpc/Makefile  |   1 +
 arch/powerpc/crypto/md5-asm.S  |  40 +++
 arch/powerpc/crypto/sha1-powerpc-asm.S |  10 +-
 arch/powerpc/include/asm/ppc_asm.h |  21 +++-
 arch/powerpc/kernel/asm-offsets.c  |   4 +-
 arch/powerpc/kernel/entry_32.S |   4 +-
 arch/powerpc/kernel/entry_64.S |  46 
 arch/powerpc/kernel/exceptions-64s.S   |   3 +-
 arch/powerpc/kernel/head_64.S  |   8 +-
 arch/powerpc/kernel/idle_book3s.S  |  88 +++---
 arch/powerpc/kernel/process.c  |   4 +-
 arch/powerpc/kernel/tm.S   |  30 ++---
 arch/powerpc/kernel/trace/ftrace_64_mprofile.S |   4 +-
 arch/powerpc/kvm/book3s_hv_interrupts.S|   5 +-
 arch/powerpc/lib/checksum_64.S |  66 +--
 arch/powerpc/lib/copypage_power7.S |  32 +++---
 arch/powerpc/lib/copyuser_power7.S | 152 -
 arch/powerpc/lib/crtsavres.S   |   3 +
 arch/powerpc/lib/memcpy_power7.S   |  80 ++---
 arch/powerpc/net/bpf_jit32.h   |  12 +-
 arch/powerpc/net/bpf_jit_asm.S |   4 +-
 21 files changed, 321 insertions(+), 296 deletions(-)

diff --git a/arch/powerpc/Makefile b/arch/powerpc/Makefile
index bc4791aecd03..4c3492851fab 100644
--- a/arch/powerpc/Makefile
+++ b/arch/powerpc/Makefile
@@ -137,6 +137,7 @@ endif
 
 CFLAGS-$(CONFIG_PPC64) += $(call cc-option,-mcmodel=medium,$(call 
cc-option,-mminimal-toc))
 CFLAGS-$(CONFIG_PPC64) += $(call cc-option,-mno-pointers-to-nested-functions)
+CFLAGS-$(CONFIG_PPC64) += -ffixed-r13 -ffixed-r14
 CFLAGS-$(CONFIG_PPC32) := -ffixed-r2 $(MULTIPLEWORD)
 
 ifeq ($(CONFIG_PPC_BOOK3S_64),y)
diff --git a/arch/powerpc/crypto/md5-asm.S b/arch/powerpc/crypto/md5-asm.S
index 10cdf5bceebb..99e41af88e19 100644
--- a/arch/powerpc/crypto/md5-asm.S
+++ b/arch/powerpc/crypto/md5-asm.S
@@ -25,31 +25,31 @@
 #define rW02   r10
 #define rW03   r11
 #define rW04   r12
-#define rW05   r14
-#define rW06   r15
-#define rW07   r16
-#define rW08   r17
-#define rW09   r18
-#define rW10   r19
-#define rW11   r20
-#define rW12   r21
-#define rW13   r22
-#define rW14   r23
-#define rW15   r24
-
-#define rT0r25
-#define rT1r26
+#define rW05   r15
+#define rW06   r16
+#define rW07   r17
+#define rW08   r18
+#define rW09   r19
+#define rW10   r20
+#define rW11   r21
+#define rW12   r22
+#define rW13   r23
+#define rW14   r24
+#define rW15   r25
+
+#define rT0r26
+#define rT1r27
 
 #define INITIALIZE \
PPC_STLU r1,-INT_FRAME_SIZE(r1); \
-   SAVE_8GPRS(14, r1); /* push registers onto stack*/ \
-   SAVE_4GPRS(22, r1);\
-   SAVE_GPR(26, r1)
+   SAVE_8GPRS(15, r1); /* push registers onto stack*/ \
+   SAVE_4GPRS(23, r1);\
+   SAVE_GPR(27, r1)
 
 #define FINALIZE \
-   REST_8GPRS(14, r1); /* pop registers from stack */ \
-   REST_4GPRS(22, r1);\
-   REST_GPR(26, r1);  \
+   REST_8GPRS(15, r1); /* pop registers from stack */ \
+   REST_4GPRS(23, r1);\
+   REST_GPR(27, r1);  \
addir1,r1,INT_FRAME_SIZE;
 
 #ifdef __BIG_ENDIAN__
diff --git a/arch/powerpc/crypto/sha1-powerpc-asm.S 
b/arch/powerpc/crypto/sha1-powerpc-asm.S
index 82ddc9bdfeb1..56bc6ac942c6 100644
--- a/arch/powerpc/crypto/sha1-powerpc-asm.S
+++ b/arch/powerpc/crypto/sha1-powerpc-asm.S
@@ -41,10 +41,10 @@
or  r6,r6,r0;   \
add r0,RE(t),r15;   \
add RT(t),RT(t),r6; \
-   add r14,r0,W(t);\
+   add r6,r0,W(t); \
LWZ(W((t)+4),((t)+4)*4,r4); \
rotlwi  RB(t),RB(t),30; \
-   add RT(t),RT(t),r14
+   add RT(t),RT(t),r6
 
 #define 

[PATCH 9/9] powerpc/64s: paca EX_CTR is not used with !RELOCATABLE, remove it

[Nicholas Piggin]

Signed-off-by: Nicholas Piggin 
---
 arch/powerpc/include/asm/exception-64s.h | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/arch/powerpc/include/asm/exception-64s.h 
b/arch/powerpc/include/asm/exception-64s.h
index aaee57f0e5ad..3b768cb668e7 100644
--- a/arch/powerpc/include/asm/exception-64s.h
+++ b/arch/powerpc/include/asm/exception-64s.h
@@ -36,9 +36,12 @@
 #define EX_CCR 52
 #define EX_CFAR56
 #define EX_PPR 64
+#if defined(CONFIG_RELOCATABLE)
 #define EX_CTR 72
-
 #define EX_SIZE10  /* size in u64 units */
+#else
+#define EX_SIZE9   /* size in u64 units */
+#endif
 
 /*
  * EX_LR is only used in EXSLB and where it does not overlap with EX_DAR
-- 
2.11.0

[PATCH 8/9] powerpc/64s: paca EX_R3 can be merged with EX_DAR

[Nicholas Piggin]

EX_R3 is used only for a small section of the bad stack handler.
Merge it with EX_DAR.

Signed-off-by: Nicholas Piggin 
---
 arch/powerpc/include/asm/exception-64s.h | 16 +++-
 1 file changed, 11 insertions(+), 5 deletions(-)

diff --git a/arch/powerpc/include/asm/exception-64s.h 
b/arch/powerpc/include/asm/exception-64s.h
index ba03db14e1e8..aaee57f0e5ad 100644
--- a/arch/powerpc/include/asm/exception-64s.h
+++ b/arch/powerpc/include/asm/exception-64s.h
@@ -34,12 +34,11 @@
 #define EX_DAR 40
 #define EX_DSISR   48
 #define EX_CCR 52
-#define EX_R3  56
-#define EX_CFAR64
-#define EX_PPR 72
-#define EX_CTR 80
+#define EX_CFAR56
+#define EX_PPR 64
+#define EX_CTR 72
 
-#define EX_SIZE11  /* size in u64 units */
+#define EX_SIZE10  /* size in u64 units */
 
 /*
  * EX_LR is only used in EXSLB and where it does not overlap with EX_DAR
@@ -49,6 +48,13 @@
  */
 #define EX_LR  EX_DAR
 
+/*
+ * EX_R3 is only used by the bad_stack handler. bad_stack reloads and
+ * saves DAR from SPRN_DAR, and EX_DAR is not used. So EX_R3 can overlap
+ * with EX_DAR.
+ */
+#define EX_R3  EX_DAR
+
 #ifdef __ASSEMBLY__
 
 /*
-- 
2.11.0

[PATCH 7/9] powerpc/64s: paca EX_LR can be merged with EX_DAR

[Nicholas Piggin]

EX_LR is used only for a small section of the SLB miss handler.
Merge it with EX_DAR.

Signed-off-by: Nicholas Piggin 
---
 arch/powerpc/include/asm/exception-64s.h | 17 -
 1 file changed, 12 insertions(+), 5 deletions(-)

diff --git a/arch/powerpc/include/asm/exception-64s.h 
b/arch/powerpc/include/asm/exception-64s.h
index e1103dc9d8e8..ba03db14e1e8 100644
--- a/arch/powerpc/include/asm/exception-64s.h
+++ b/arch/powerpc/include/asm/exception-64s.h
@@ -35,12 +35,19 @@
 #define EX_DSISR   48
 #define EX_CCR 52
 #define EX_R3  56
-#define EX_LR  64
-#define EX_CFAR72
-#define EX_PPR 80  /* SMT thread status register (priority) */
-#define EX_CTR 88
+#define EX_CFAR64
+#define EX_PPR 72
+#define EX_CTR 80
 
-#define EX_SIZE12  /* size in u64 units */
+#define EX_SIZE11  /* size in u64 units */
+
+/*
+ * EX_LR is only used in EXSLB and where it does not overlap with EX_DAR
+ * EX_CCR similarly with DSISR, but being 4 byte registers there is a hole
+ * in the save area so it's not necessary to overlap them. Could be used
+ * for future savings though if another 4 byte register was to be saved.
+ */
+#define EX_LR  EX_DAR
 
 #ifdef __ASSEMBLY__
 
-- 
2.11.0

[PATCH 6/9] powerpc/64s: paca EX_SRR0 is unused, remove it

[Nicholas Piggin]

Signed-off-by: Nicholas Piggin 
---
 arch/powerpc/include/asm/exception-64s.h | 21 ++---
 1 file changed, 10 insertions(+), 11 deletions(-)

diff --git a/arch/powerpc/include/asm/exception-64s.h 
b/arch/powerpc/include/asm/exception-64s.h
index 3edcad24684f..e1103dc9d8e8 100644
--- a/arch/powerpc/include/asm/exception-64s.h
+++ b/arch/powerpc/include/asm/exception-64s.h
@@ -31,17 +31,16 @@
 #define EX_R11 16
 #define EX_R12 24
 #define EX_R13 32
-#define EX_SRR040
-#define EX_DAR 48
-#define EX_DSISR   56
-#define EX_CCR 60
-#define EX_R3  64
-#define EX_LR  72
-#define EX_CFAR80
-#define EX_PPR 88  /* SMT thread status register (priority) */
-#define EX_CTR 96
-
-#define EX_SIZE13  /* size in u64 units */
+#define EX_DAR 40
+#define EX_DSISR   48
+#define EX_CCR 52
+#define EX_R3  56
+#define EX_LR  64
+#define EX_CFAR72
+#define EX_PPR 80  /* SMT thread status register (priority) */
+#define EX_CTR 88
+
+#define EX_SIZE12  /* size in u64 units */
 
 #ifdef __ASSEMBLY__
 
-- 
2.11.0

[PATCH 5/9] powerpc/64s: paca add EX_SIZE definition for exception save areas

[Nicholas Piggin]

Signed-off-by: Nicholas Piggin 
---
 arch/powerpc/include/asm/exception-64s.h | 30 +++---
 arch/powerpc/include/asm/paca.h  | 12 
 2 files changed, 27 insertions(+), 15 deletions(-)

diff --git a/arch/powerpc/include/asm/exception-64s.h 
b/arch/powerpc/include/asm/exception-64s.h
index 183d73b6ed99..3edcad24684f 100644
--- a/arch/powerpc/include/asm/exception-64s.h
+++ b/arch/powerpc/include/asm/exception-64s.h
@@ -24,18 +24,8 @@
  *  as published by the Free Software Foundation; either version
  *  2 of the License, or (at your option) any later version.
  */
-/*
- * The following macros define the code that appears as
- * the prologue to each of the exception handlers.  They
- * are split into two parts to allow a single kernel binary
- * to be used for pSeries and iSeries.
- *
- * We make as much of the exception code common between native
- * exception handlers (including pSeries LPAR) and iSeries LPAR
- * implementations as possible.
- */
-#include 
 
+/* PACA save area offsets (exgen, exmc, etc) */
 #define EX_R9  0
 #define EX_R10 8
 #define EX_R11 16
@@ -51,6 +41,22 @@
 #define EX_PPR 88  /* SMT thread status register (priority) */
 #define EX_CTR 96
 
+#define EX_SIZE13  /* size in u64 units */
+
+#ifdef __ASSEMBLY__
+
+/*
+ * The following macros define the code that appears as
+ * the prologue to each of the exception handlers.  They
+ * are split into two parts to allow a single kernel binary
+ * to be used for pSeries and iSeries.
+ *
+ * We make as much of the exception code common between native
+ * exception handlers (including pSeries LPAR) and iSeries LPAR
+ * implementations as possible.
+ */
+#include 
+
 #ifdef CONFIG_RELOCATABLE
 #define __EXCEPTION_RELON_PROLOG_PSERIES_1(label, h)   \
mfspr   r11,SPRN_##h##SRR0; /* save SRR0 */ \
@@ -608,4 +614,6 @@ END_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP)
 #define FINISH_NAP
 #endif
 
+#endif /*__ASSEMBLY__ */
+
 #endif /* _ASM_POWERPC_EXCEPTION_H */
diff --git a/arch/powerpc/include/asm/paca.h b/arch/powerpc/include/asm/paca.h
index 1c09f8fe2ee8..8ea0907975a4 100644
--- a/arch/powerpc/include/asm/paca.h
+++ b/arch/powerpc/include/asm/paca.h
@@ -21,7 +21,11 @@
 #include 
 #include 
 #include 
+#ifdef CONFIG_PPC_BOOK3E
 #include 
+#else
+#include 
+#endif
 #ifdef CONFIG_KVM_BOOK3S_64_HANDLER
 #include 
 #endif
@@ -98,8 +102,8 @@ struct paca_struct {
 * Now, starting in cacheline 2, the exception save areas
 */
/* used for most interrupts/exceptions */
-   u64 exgen[13] __attribute__((aligned(0x80)));
-   u64 exslb[13];  /* used for SLB/segment table misses
+   u64 exgen[EX_SIZE] __attribute__((aligned(0x80)));
+   u64 exslb[EX_SIZE]; /* used for SLB/segment table misses
 * on the linear mapping */
/* SLB related definitions */
u16 vmalloc_sllp;
@@ -181,8 +185,8 @@ struct paca_struct {
 
 #ifdef CONFIG_PPC_STD_MMU_64
/* Non-maskable exceptions that are not performance critical */
-   u64 exnmi[13];  /* used for system reset (nmi) */
-   u64 exmc[13];   /* used for machine checks */
+   u64 exnmi[EX_SIZE]; /* used for system reset (nmi) */
+   u64 exmc[EX_SIZE];  /* used for machine checks */
 #endif
 #ifdef CONFIG_PPC_BOOK3S_64
/* Exclusive stacks for system reset and machine check exception. */
-- 
2.11.0

[PATCH 4/9] powerpc/64s: SLB miss handler avoid r3 save/restore

[Nicholas Piggin]

The SLB miss handler uses r3 for the faulting address but r12 is
mostly able to be freed up to save r3 in. It just requires SRR1
be reloaded again on error.

It would be more conventional to use r12 for SRR1 (and use r11 to
save r3), but slb_allocate_realmode clobbers r11 and not r12.

Signed-off-by: Nicholas Piggin 
---
 arch/powerpc/kernel/exceptions-64s.S | 34 ++
 1 file changed, 18 insertions(+), 16 deletions(-)

diff --git a/arch/powerpc/kernel/exceptions-64s.S 
b/arch/powerpc/kernel/exceptions-64s.S
index 486e205cc762..6ba4c4c6ae69 100644
--- a/arch/powerpc/kernel/exceptions-64s.S
+++ b/arch/powerpc/kernel/exceptions-64s.S
@@ -507,9 +507,9 @@ EXC_REAL_BEGIN(data_access_slb, 0x380, 0x80)
SET_SCRATCH0(r13)
EXCEPTION_PROLOG_0(PACA_EXSLB)
EXCEPTION_PROLOG_1(PACA_EXSLB, KVMTEST_PR, 0x380)
-   std r3,PACA_EXSLB+EX_R3(r13)
+   mr  r12,r3  /* save r3 */
mfspr   r3,SPRN_DAR
-   mfspr   r12,SPRN_SRR1
+   mfspr   r11,SPRN_SRR1
crset   4*cr6+eq
 #ifndef CONFIG_RELOCATABLE
b   slb_miss_realmode
@@ -530,9 +530,9 @@ EXC_VIRT_BEGIN(data_access_slb, 0x4380, 0x80)
SET_SCRATCH0(r13)
EXCEPTION_PROLOG_0(PACA_EXSLB)
EXCEPTION_PROLOG_1(PACA_EXSLB, NOTEST, 0x380)
-   std r3,PACA_EXSLB+EX_R3(r13)
+   mr  r12,r3  /* save r3 */
mfspr   r3,SPRN_DAR
-   mfspr   r12,SPRN_SRR1
+   mfspr   r11,SPRN_SRR1
crset   4*cr6+eq
 #ifndef CONFIG_RELOCATABLE
b   slb_miss_realmode
@@ -575,9 +575,9 @@ EXC_REAL_BEGIN(instruction_access_slb, 0x480, 0x80)
SET_SCRATCH0(r13)
EXCEPTION_PROLOG_0(PACA_EXSLB)
EXCEPTION_PROLOG_1(PACA_EXSLB, KVMTEST_PR, 0x480)
-   std r3,PACA_EXSLB+EX_R3(r13)
+   mr  r12,r3  /* save r3 */
mfspr   r3,SPRN_SRR0/* SRR0 is faulting address */
-   mfspr   r12,SPRN_SRR1
+   mfspr   r11,SPRN_SRR1
crclr   4*cr6+eq
 #ifndef CONFIG_RELOCATABLE
b   slb_miss_realmode
@@ -593,9 +593,9 @@ EXC_VIRT_BEGIN(instruction_access_slb, 0x4480, 0x80)
SET_SCRATCH0(r13)
EXCEPTION_PROLOG_0(PACA_EXSLB)
EXCEPTION_PROLOG_1(PACA_EXSLB, NOTEST, 0x480)
-   std r3,PACA_EXSLB+EX_R3(r13)
+   mr  r12,r3  /* save r3 */
mfspr   r3,SPRN_SRR0/* SRR0 is faulting address */
-   mfspr   r12,SPRN_SRR1
+   mfspr   r11,SPRN_SRR1
crclr   4*cr6+eq
 #ifndef CONFIG_RELOCATABLE
b   slb_miss_realmode
@@ -613,10 +613,10 @@ TRAMP_KVM(PACA_EXSLB, 0x480)
 EXC_COMMON_BEGIN(slb_miss_realmode)
/*
 * r13 points to the PACA, r9 contains the saved CR,
-* r12 contain the saved SRR1, SRR0 is still ready for return
+* r12 contains the saved r3,
+* r11 contain the saved SRR1, SRR0 is still ready for return
 * r3 has the faulting address
 * r9 - r13 are saved in paca->exslb.
-* r3 is saved in paca->slb_r3
 * cr6.eq is set for a D-SLB miss, clear for a I-SLB miss
 * We assume we aren't going to take any exceptions during this
 * procedure.
@@ -625,6 +625,9 @@ EXC_COMMON_BEGIN(slb_miss_realmode)
stw r9,PACA_EXSLB+EX_CCR(r13)   /* save CR in exc. frame */
std r10,PACA_EXSLB+EX_LR(r13)   /* save LR */
 
+   andi.   r11,r11,MSR_RI  /* check for unrecoverable exception */
+   beq-2f
+
crset   4*cr0+eq
 #ifdef CONFIG_PPC_STD_MMU_64
 BEGIN_MMU_FTR_SECTION
@@ -638,9 +641,6 @@ END_MMU_FTR_SECTION_IFCLR(MMU_FTR_TYPE_RADIX)
 
beq-8f  /* if bad address, make full stack frame */
 
-   andi.   r10,r12,MSR_RI  /* check for unrecoverable exception */
-   beq-2f
-
/* All done -- return from exception. */
 
 .machine   push
@@ -652,7 +652,7 @@ END_MMU_FTR_SECTION_IFCLR(MMU_FTR_TYPE_RADIX)
 
RESTORE_CTR(r9, PACA_EXSLB)
RESTORE_PPR_PACA(PACA_EXSLB, r9)
-   ld  r3,PACA_EXSLB+EX_R3(r13)
+   mr  r3,r12
ld  r9,PACA_EXSLB+EX_R9(r13)
ld  r10,PACA_EXSLB+EX_R10(r13)
ld  r11,PACA_EXSLB+EX_R11(r13)
@@ -662,8 +662,9 @@ END_MMU_FTR_SECTION_IFCLR(MMU_FTR_TYPE_RADIX)
b   .   /* prevent speculative execution */
 
 2: std r3,PACA_EXSLB+EX_DAR(r13)
-   ld  r3,PACA_EXSLB+EX_R3(r13)
+   mr  r3,r12
mfspr   r11,SPRN_SRR0
+   mfspr   r12,SPRN_SRR1
LOAD_HANDLER(r10,unrecov_slb)
mtspr   SPRN_SRR0,r10
ld  r10,PACAKMSR(r13)
@@ -672,8 +673,9 @@ END_MMU_FTR_SECTION_IFCLR(MMU_FTR_TYPE_RADIX)
b   .
 
 8: std r3,PACA_EXSLB+EX_DAR(r13)
-   ld  r3,PACA_EXSLB+EX_R3(r13)
+   mr  r3,r12
mfspr   r11,SPRN_SRR0
+   mfspr   r12,SPRN_SRR1
LOAD_HANDLER(r10,bad_addr_slb)
mtspr   SPRN_SRR0,r10
ld  r10,PACAKMSR(r13)
-- 
2.11.0

[PATCH 3/9] powerpc/64s: SLB miss already has CTR saved for relocatable kernel

[Nicholas Piggin]

The EXCEPTION_PROLOG_1 used by SLB miss already saves CTR when the
kernel is built with CONFIG_RELOCATABLE. So it does not have to be
saved and reloaded when branching to slb_miss_realmode. It can be
restored from the PACA as usual.

Signed-off-by: Nicholas Piggin 
---
 arch/powerpc/kernel/exceptions-64s.S | 13 +
 1 file changed, 5 insertions(+), 8 deletions(-)

diff --git a/arch/powerpc/kernel/exceptions-64s.S 
b/arch/powerpc/kernel/exceptions-64s.S
index a4a71bce35d6..486e205cc762 100644
--- a/arch/powerpc/kernel/exceptions-64s.S
+++ b/arch/powerpc/kernel/exceptions-64s.S
@@ -519,7 +519,7 @@ EXC_REAL_BEGIN(data_access_slb, 0x380, 0x80)
 * because the distance from here to there depends on where
 * the kernel ends up being put.
 */
-   mfctr   r11
+   /* CTR is saved if RELOCATABLE */
LOAD_HANDLER(r10, slb_miss_realmode)
mtctr   r10
bctr
@@ -542,7 +542,7 @@ EXC_VIRT_BEGIN(data_access_slb, 0x4380, 0x80)
 * because the distance from here to there depends on where
 * the kernel ends up being put.
 */
-   mfctr   r11
+   /* CTR is saved if RELOCATABLE */
LOAD_HANDLER(r10, slb_miss_realmode)
mtctr   r10
bctr
@@ -582,7 +582,7 @@ EXC_REAL_BEGIN(instruction_access_slb, 0x480, 0x80)
 #ifndef CONFIG_RELOCATABLE
b   slb_miss_realmode
 #else
-   mfctr   r11
+   /* CTR is saved if RELOCATABLE */
LOAD_HANDLER(r10, slb_miss_realmode)
mtctr   r10
bctr
@@ -600,7 +600,7 @@ EXC_VIRT_BEGIN(instruction_access_slb, 0x4480, 0x80)
 #ifndef CONFIG_RELOCATABLE
b   slb_miss_realmode
 #else
-   mfctr   r11
+   /* CTR is saved if RELOCATABLE */
LOAD_HANDLER(r10, slb_miss_realmode)
mtctr   r10
bctr
@@ -622,10 +622,6 @@ EXC_COMMON_BEGIN(slb_miss_realmode)
 * procedure.
 */
mflrr10
-#ifdef CONFIG_RELOCATABLE
-   mtctr   r11
-#endif
-
stw r9,PACA_EXSLB+EX_CCR(r13)   /* save CR in exc. frame */
std r10,PACA_EXSLB+EX_LR(r13)   /* save LR */
 
@@ -654,6 +650,7 @@ END_MMU_FTR_SECTION_IFCLR(MMU_FTR_TYPE_RADIX)
mtcrf   0x01,r9 /* slb_allocate uses cr0 and cr7 */
 .machine   pop
 
+   RESTORE_CTR(r9, PACA_EXSLB)
RESTORE_PPR_PACA(PACA_EXSLB, r9)
ld  r3,PACA_EXSLB+EX_R3(r13)
ld  r9,PACA_EXSLB+EX_R9(r13)
-- 
2.11.0

[PATCH 2/9] powerpc/64s: SLB miss handler avoid saving faulting address into EX_DAR

[Nicholas Piggin]

The EX_DAR save area is only used in exceptional cases. With r3 no
longer clobbered by slb_allocate_realmode, saving faulting address to
EX_DAR can be deferred to those cases.

Signed-off-by: Nicholas Piggin 
---
 arch/powerpc/kernel/exceptions-64s.S | 13 -
 1 file changed, 8 insertions(+), 5 deletions(-)

diff --git a/arch/powerpc/kernel/exceptions-64s.S 
b/arch/powerpc/kernel/exceptions-64s.S
index ae418b85c17c..a4a71bce35d6 100644
--- a/arch/powerpc/kernel/exceptions-64s.S
+++ b/arch/powerpc/kernel/exceptions-64s.S
@@ -628,7 +628,6 @@ EXC_COMMON_BEGIN(slb_miss_realmode)
 
stw r9,PACA_EXSLB+EX_CCR(r13)   /* save CR in exc. frame */
std r10,PACA_EXSLB+EX_LR(r13)   /* save LR */
-   std r3,PACA_EXSLB+EX_DAR(r13)
 
crset   4*cr0+eq
 #ifdef CONFIG_PPC_STD_MMU_64
@@ -638,11 +637,10 @@ END_MMU_FTR_SECTION_IFCLR(MMU_FTR_TYPE_RADIX)
 #endif
 
ld  r10,PACA_EXSLB+EX_LR(r13)
-   ld  r3,PACA_EXSLB+EX_R3(r13)
lwz r9,PACA_EXSLB+EX_CCR(r13)   /* get saved CR */
mtlrr10
 
-   beq 8f  /* if bad address, make full stack frame */
+   beq-8f  /* if bad address, make full stack frame */
 
andi.   r10,r12,MSR_RI  /* check for unrecoverable exception */
beq-2f
@@ -657,6 +655,7 @@ END_MMU_FTR_SECTION_IFCLR(MMU_FTR_TYPE_RADIX)
 .machine   pop
 
RESTORE_PPR_PACA(PACA_EXSLB, r9)
+   ld  r3,PACA_EXSLB+EX_R3(r13)
ld  r9,PACA_EXSLB+EX_R9(r13)
ld  r10,PACA_EXSLB+EX_R10(r13)
ld  r11,PACA_EXSLB+EX_R11(r13)
@@ -665,7 +664,9 @@ END_MMU_FTR_SECTION_IFCLR(MMU_FTR_TYPE_RADIX)
rfid
b   .   /* prevent speculative execution */
 
-2: mfspr   r11,SPRN_SRR0
+2: std r3,PACA_EXSLB+EX_DAR(r13)
+   ld  r3,PACA_EXSLB+EX_R3(r13)
+   mfspr   r11,SPRN_SRR0
LOAD_HANDLER(r10,unrecov_slb)
mtspr   SPRN_SRR0,r10
ld  r10,PACAKMSR(r13)
@@ -673,7 +674,9 @@ END_MMU_FTR_SECTION_IFCLR(MMU_FTR_TYPE_RADIX)
rfid
b   .
 
-8: mfspr   r11,SPRN_SRR0
+8: std r3,PACA_EXSLB+EX_DAR(r13)
+   ld  r3,PACA_EXSLB+EX_R3(r13)
+   mfspr   r11,SPRN_SRR0
LOAD_HANDLER(r10,bad_addr_slb)
mtspr   SPRN_SRR0,r10
ld  r10,PACAKMSR(r13)
-- 
2.11.0

[PATCH 1/9] powerpc/64s: slb_allocate_realmode() preserve r3

[Nicholas Piggin]

One fewer registers clobbered by this function means the SLB miss
handler can save one fewer.

Signed-off-by: Nicholas Piggin 
---
 arch/powerpc/mm/slb_low.S | 24 ++--
 1 file changed, 14 insertions(+), 10 deletions(-)

diff --git a/arch/powerpc/mm/slb_low.S b/arch/powerpc/mm/slb_low.S
index 1519617aab36..9869b44a04dc 100644
--- a/arch/powerpc/mm/slb_low.S
+++ b/arch/powerpc/mm/slb_low.S
@@ -70,6 +70,7 @@ ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_68_BIT_VA)
  * Create an SLB entry for the given EA (user or kernel).
  * r3 = faulting address, r13 = PACA
  * r9, r10, r11 are clobbered by this function
+ * r3 is preserved.
  * No other registers are examined or changed.
  */
 _GLOBAL(slb_allocate_realmode)
@@ -235,6 +236,9 @@ END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
 * dont have any LRU information to help us choose a slot.
 */
 
+   mr  r9,r3
+
+   /* slb_finish_load_1T continues here. r9=EA with non-ESID bits clear */
 7: ld  r10,PACASTABRR(r13)
addir10,r10,1
/* This gets soft patched on boot. */
@@ -249,10 +253,10 @@ slb_compare_rr_to_size:
std r10,PACASTABRR(r13)
 
 3:
-   rldimi  r3,r10,0,36 /* r3= EA[0:35] | entry */
-   orisr10,r3,SLB_ESID_V@h /* r3 |= SLB_ESID_V */
+   rldimi  r9,r10,0,36 /* r9  = EA[0:35] | entry */
+   orisr10,r9,SLB_ESID_V@h /* r10 = r9 | SLB_ESID_V */
 
-   /* r3 = ESID data, r11 = VSID data */
+   /* r9 = ESID data, r11 = VSID data */
 
/*
 * No need for an isync before or after this slbmte. The exception
@@ -265,21 +269,21 @@ slb_compare_rr_to_size:
bgelr   cr7
 
/* Update the slb cache */
-   lhz r3,PACASLBCACHEPTR(r13) /* offset = paca->slb_cache_ptr */
-   cmpldi  r3,SLB_CACHE_ENTRIES
+   lhz r9,PACASLBCACHEPTR(r13) /* offset = paca->slb_cache_ptr */
+   cmpldi  r9,SLB_CACHE_ENTRIES
bge 1f
 
/* still room in the slb cache */
-   sldir11,r3,2/* r11 = offset * sizeof(u32) */
+   sldir11,r9,2/* r11 = offset * sizeof(u32) */
srdir10,r10,28  /* get the 36 bits of the ESID */
add r11,r11,r13 /* r11 = (u32 *)paca + offset */
stw r10,PACASLBCACHE(r11)   /* paca->slb_cache[offset] = esid */
-   addir3,r3,1 /* offset++ */
+   addir9,r9,1 /* offset++ */
b   2f
 1: /* offset >= SLB_CACHE_ENTRIES */
-   li  r3,SLB_CACHE_ENTRIES+1
+   li  r9,SLB_CACHE_ENTRIES+1
 2:
-   sth r3,PACASLBCACHEPTR(r13) /* paca->slb_cache_ptr = offset */
+   sth r9,PACASLBCACHEPTR(r13) /* paca->slb_cache_ptr = offset */
crclr   4*cr0+eq/* set result to "success" */
blr
 
@@ -301,7 +305,7 @@ slb_compare_rr_to_size:
rldimi  r11,r10,SLB_VSID_SSIZE_SHIFT,0  /* insert segment size */
 
/* r3 = EA, r11 = VSID data */
-   clrrdi  r3,r3,SID_SHIFT_1T  /* clear out non-ESID bits */
+   clrrdi  r9,r3,SID_SHIFT_1T  /* clear out non-ESID bits */
b   7b
 
 
-- 
2.11.0

[PATCH 0/9] Reduce PACA save areas

[Nicholas Piggin]

I want to save another register in the PACA, so I had a look at
what we might cut from it first. 3-4 fields are reasonably easy
to remove.

Nicholas Piggin (9):
  powerpc/64s: slb_allocate_realmode() preserve r3
  powerpc/64s: SLB miss handler avoid saving faulting address into
EX_DAR
  powerpc/64s: SLB miss already has CTR saved for relocatable kernel
  powerpc/64s: SLB miss handler avoid r3 save/restore
  powerpc/64s: paca add EX_SIZE definition for exception save areas
  powerpc/64s: paca EX_SRR0 is unused, remove it
  powerpc/64s: paca EX_LR can be merged with EX_DAR
  powerpc/64s: paca EX_R3 can be merged with EX_DAR
  powerpc/64s: paca EX_CTR is not used with !RELOCATABLE, remove it

 arch/powerpc/include/asm/exception-64s.h | 53 ++-
 arch/powerpc/include/asm/paca.h  | 12 ---
 arch/powerpc/kernel/exceptions-64s.S | 54 +---
 arch/powerpc/mm/slb_low.S| 24 --
 4 files changed, 88 insertions(+), 55 deletions(-)

-- 
2.11.0

Re: [PATCH 2/9] timers: provide a "modern" variant of timers

[Arnd Bergmann]

On Sun, May 21, 2017 at 9:00 AM, Christoph Hellwig  wrote:
> On Thu, May 18, 2017 at 10:57:31AM +0200, Arnd Bergmann wrote:
>> How expensive would it be to add another field to timer_list and
>> just have both pointers?
>
> That would add 4/8 bytes to every structure containing a timer,
> so I'd rather avoid it if possible.

I didn't expect too many timers to be in allocated structures at the same
time on most systems, but I haven't researched this at all.

We should probably update the comment about the cacheline alignment
though: when most users embed the timer_list in some other structure,
it's not valid at all, and forcing timer_list to be cacheline aligned would
waste way more space than an extra field.

>  But one option might be to inflict this onto users of outdated compilers
> and use the union for modern ones.

Good idea, this sounds better than the alternatives at least. The
remaining users of those old compilers certainly don't care that much
about micro-optimizing the kernel anyway.

   Arnd

Re: [PATCH 2/9] timers: provide a "modern" variant of timers

[Christoph Hellwig]

On Thu, May 18, 2017 at 10:57:31AM +0200, Arnd Bergmann wrote:
> How expensive would it be to add another field to timer_list and
> just have both pointers?

That would add 4/8 bytes to every structure containing a timer,
so I'd rather avoid it if possible.  But one option might be to
inflict this onto users of outdated compilers and use the union
for modern ones.

Re: [PATCH 2/9] timers: provide a "modern" variant of timers

['Christoph Hellwig']

On Fri, May 19, 2017 at 10:48:51AM +, David Laight wrote:
> From: Christoph Hellwig
> > Sent: 16 May 2017 12:48
> >
> > The new callback gets a pointer to the timer_list itself, which can
> > then be used to get the containing structure using container_of
> > instead of casting from and to unsigned long all the time.
> 
> What about sensible drivers that put some other value in the 'data'
> field?

They will add the equivalent of the data field into the containing
structure of the timer.  Just like we do for all other kernel interfaces
using the container_of patter, which includes just about every
primitive designed in the last 15 years.