From: Yongji Xie
Any IODA host bridge have the capability of IRQ remapping.
So we set PCI_BUS_FLAGS_MSI_REMAP when this kind of host birdge
is detected.
Signed-off-by: Yongji Xie
Signed-off-by: Alexey Kardashevskiy
---
Here is a patchset which Yongji was working on before
leaving IBM LTC. Since we still want to have this functionality
in the kernel (DPDK is the first user), here is a rebase
on the current upstream.
Current vfio-pci implementation disallows to mmap the page
containing MSI-X table in case that
From: Yongji Xie
This patch tries to expose MSI-X tables to userspace if hardware
enables interrupt remapping which can ensure that a given PCI
device can only shoot the MSIs assigned for it. So we could
never worry that userspace driver can hurt other devices by
writing to
From: Yongji Xie
We introduce a new pci_bus_flags, PCI_BUS_FLAGS_MSI_REMAP
which indicates interrupts of all devices on the bus are
managed by the hardware enabling IRQ remapping(intel naming).
When the capability is enabled, a given PCI device can only
shoot the MSIs
Ouch, this is a wrong one, please ignore. I'll repost in a sec.
On 15/06/17 15:06, Alexey Kardashevskiy wrote:
> Here is a patchset which Yongji was working on before
> leaving IBM LTC. Since we still want to have this functionality
> in the kernel (DPDK is the first user), here is a rebase
> on
From: Yongji Xie
This patch tries to expose MSI-X tables to userspace if hardware
enables interrupt remapping which can ensure that a given PCI
device can only shoot the MSIs assigned for it. So we could
never worry that userspace driver can hurt other devices by
From: Yongji Xie
Any IODA host bridge have the capability of IRQ remapping.
So we set PCI_BUS_FLAGS_MSI_REMAP when this kind of host birdge
is detected.
Signed-off-by: Yongji Xie
Reviewed-by: Alexey Kardashevskiy
From: Yongji Xie
We introduce a new pci_bus_flags, PCI_BUS_FLAGS_MSI_REMAP
which indicates interrupts of all devices on the bus are
managed by the hardware enabling IRQ remapping(intel naming).
When the capability is enabled, a given PCI device can only
shoot the MSIs
Here is a patchset which Yongji was working on before
leaving IBM LTC. Since we still want to have this functionality
in the kernel (DPDK is the first user), here is a rebase
on the current upstream.
Current vfio-pci implementation disallows to mmap the page
containing MSI-X table in case that
Hi Anton,
On Thu, Jun 15, 2017 at 09:46:38AM +1000, Anton Blanchard wrote:
> The mcrf emulation code was looking at the CR fields in the reverse
> order. It also relied on reserved fields being zero which is somewhat
> fragile, so fix that too.
It masked out the reserved bits. I find the new
The P9 PVR bits 12-15 don't indicate a revision but instead different
chip configurations. From BookIV we have:
Bits Configuration
0 :Scale out 12 cores
1 :Scale out 24 cores
2 :Scale up 12 cores
3 :Scale up 24 cores
DD1 doesn't use this but DD2 does.
On 14/06/17 14:47, Alistair Popple wrote:
> "4c3b89e powerpc/powernv: Add sanity checks to pnv_pci_get_{gpu|npu}_dev"
> introduced explicit warnings in pnv_pci_get_npu_dev() when a PCIe device
> has no associated device-tree node. However not all PCIe devices have an
> of_node and
On 14/06/17 21:04, Michael Ellerman wrote:
> Alexey Kardashevskiy writes:
>
>> When trapped on WARN_ON(), report_bug() is expected to return
>> BUG_TRAP_TYPE_WARN so the caller could increment NIP by 4 and continue.
>> The __builtin_constant_p() path of the PPC's WARN_ON() calls
From: Anton Blanchard
>From POWER4 onwards, mfocrf() only places the specified CR field into
the destination GPR, and the rest of it is set to 0. The PowerPC AS
from version 3.0 now requires this behaviour.
The emulation code currently puts the entire CR into the destination
From: Anton Blanchard
The mcrf emulation code was looking at the CR fields in the reverse
order. It also relied on reserved fields being zero which is somewhat
fragile, so fix that too.
Cc: sta...@vger.kernel.org
Signed-off-by: Anton Blanchard
---
On Wed, Jun 14, 2017 at 09:40:18AM +0200, Christophe LEROY wrote:
>
>
> Le 13/06/2017 à 09:37, Heiko Schocher a écrit :
> >Hello Christophe,
> >
> >Am 13.06.2017 um 07:40 schrieb Christophe LEROY:
> >>
> >>
> >>Le 13/06/2017 à 07:26, Christophe LEROY a écrit :
> >>>There was for long time no
Hello Suka,
Thanks for your review!
Sukadev Bhattiprolu writes:
> Thiago Jung Bauermann [bauer...@linux.vnet.ibm.com] wrote:
>> @@ -166,9 +174,12 @@ DEFINE_PER_CPU(struct hv_24x7_hw, hv_24x7_hw);
>> DEFINE_PER_CPU(char, hv_24x7_reqb[H24x7_DATA_BUFFER_SIZE])
Le 13/06/2017 à 17:41, Christophe Lombard a écrit :
A previous set of patches "cxl: Add support for Coherent Accelerator
Interface Architecture 2.0" has introduced a new support for the CAPI
cards. These patches have been tested on Simulation environment and
quite a bit of them have been
This helper is used to detect if a uprobe'd function has returned
through a setjmp/longjmp, rather than branching to the LR that was
updated previously by us. This fixes a SIGSEGV that gets generated when
programs use setjmp/longjmp with uretprobes.
We use the arm64 model
On Wed, 2017-06-14 at 14:44 +1000, Michael Ellerman wrote:
> Benjamin Herrenschmidt writes:
>
> > Architecturally we should apply a 0x400 offset for these. Not doing
> > it will break future HW implementations.
>
> Can you elaborate a bit?
>
> You're changing a write
Le 14/06/2017 à 07:01, Michael Ellerman a écrit :
Christophe Lombard writes:
A previous set of patches "cxl: Add support for Coherent Accelerator
Interface Architecture 2.0" has introduced a new support for the CAPI
cards.
Which commit is that?
cheers
Here are
On Wed, 14 Jun 2017 21:38:36 +1000
Michael Ellerman wrote:
> Nicholas Piggin writes:
>
> > The CTRL register is read-only except bit 63 which is the run latch
> > control. This means it can be updated with a mtspr rather than
> > mfspr/mtspr.
>
>
On 2017/06/14 04:41PM, Michael Ellerman wrote:
> "Aneesh Kumar K.V" writes:
> > On Wednesday 14 June 2017 10:41 AM, Naveen N. Rao wrote:
> >> On 2017/06/14 08:38AM, Aneesh Kumar K.V wrote:
> >>> "Naveen N. Rao" writes:
> diff
Hello:
On 06/14/2017 12:27 AM, Balbir Singh wrote:
> On Wed, Jun 14, 2017 at 3:25 PM, Balbir Singh wrote:
>>
>>
>> On Wed, Jun 14, 2017 at 8:21 AM, Michael Bringmann
>> wrote:
>>>
>>> On a related note, we are discussing the addition of 2 new
Hello Christophe,
Am 14.06.2017 um 09:40 schrieb Christophe LEROY:
Le 13/06/2017 à 09:37, Heiko Schocher a écrit :
Hello Christophe,
Am 13.06.2017 um 07:40 schrieb Christophe LEROY:
Le 13/06/2017 à 07:26, Christophe LEROY a écrit :
There was for long time no activity in the 8xx area.
We
This patch exports a in-kernel 'library' API which can be called by
other drivers to help interacting with an IBM XSL on a POWER9 system.
The XSL (Translation Service Layer) is a stripped down version of the
PSL (Power Service Layer) used in some cards such as the Mellanox CX5.
Like the PSL, it
Nicholas Piggin writes:
> diff --git a/kernel/sched/core.c b/kernel/sched/core.c
> index 803c3bc274c4..1f0688ad09d7 100644
> --- a/kernel/sched/core.c
> +++ b/kernel/sched/core.c
> @@ -2875,6 +2875,12 @@ context_switch(struct rq *rq, struct task_struct *prev,
>
Nicholas Piggin writes:
> On Wed, 14 Jun 2017 21:40:52 +1000
> Michael Ellerman wrote:
>
>> Nicholas Piggin writes:
>>
>> > local_irq_enable can cause interrupts to be taken which could
>> > take significant amount of processing time.
A memory barrier is not required after the task wakes up,
only if we clear the polling flag before waking. The case
where we have work to do is the important one, so optimise
for it.
Reviewed-by: Vaidyanathan Srinivasan
Signed-off-by: Nicholas Piggin
Ensure these don't get put into bouncing cachelines.
Reviewed-by: Vaidyanathan Srinivasan
Reviewed-by: Gautham R. Shenoy
Signed-off-by: Nicholas Piggin
---
drivers/cpuidle/cpuidle-powernv.c | 10 +-
local_irq_enable can cause interrupts to be taken which could
take significant amount of processing time. The idle process
should set its polling flag before this, so another process that
wakes it during this time will not have to send an IPI.
Expand the TIF_POLLING_NRFLAG coverage to as large as
Hi,
These are a few small improvements that came from doing an
optimisation pass over powerpc cpu idle paths.
Michael reminded me to cc the cpuidle maintainers. I think he
will take the patches through the powerpc tree, but any suggestion
or ack or nack would be welcome.
Thanks,
Nick
Nicholas
Hi Thiago,
On Wed, 2017-06-07 at 22:49 -0300, Thiago Jung Bauermann wrote:
> This patch introduces the modsig keyword to the IMA policy syntax to
> specify that a given hook should expect the file to have the IMA signature
> appended to it. Here is how it can be used in a rule:
>
> appraise
On Wed, 14 Jun 2017 21:40:52 +1000
Michael Ellerman wrote:
> Nicholas Piggin writes:
>
> > local_irq_enable can cause interrupts to be taken which could
> > take significant amount of processing time. The idle process
> > should set its polling flag
On Mon, Jun 12, 2017 at 01:34:05PM -0500, Thor Thayer wrote:
> On 06/06/2017 06:54 PM, Chris Packham wrote:
> > Use of_address_to_resource() and resource_size() instead of manually
> > parsing the "reg" property from the "memory" node(s).
> >
> > Signed-off-by: Chris Packham
Davide Caratti writes:
> On Tue, 2017-06-13 at 20:49 +1000, Michael Ellerman wrote:
>> Davide Caratti writes:
>>
>> > NF_CT_PROTO_{SCTP,UDPLITE,DCCP} can't be set to 'm' anymore, since they
>> > have been redefined as 'bool': fix defconfig for
Nicholas Piggin writes:
> local_irq_enable can cause interrupts to be taken which could
> take significant amount of processing time. The idle process
> should set its polling flag before this, so another process that
> wakes it during this time will not have to send an IPI.
>
Nicholas Piggin writes:
> The CTRL register is read-only except bit 63 which is the run latch
> control. This means it can be updated with a mtspr rather than
> mfspr/mtspr.
Turns out this doesn't work on Cell.
There's an extra field in there:
Thread enable bits
Nicholas Piggin writes:
> On Tue, 13 Jun 2017 23:05:47 +1000
> Nicholas Piggin wrote:
>
>> diff --git a/arch/powerpc/include/asm/hw_irq.h
>> b/arch/powerpc/include/asm/hw_irq.h
>> index f06112cf8734..8366bdc69988 100644
>> ---
Alexey Kardashevskiy writes:
> When trapped on WARN_ON(), report_bug() is expected to return
> BUG_TRAP_TYPE_WARN so the caller could increment NIP by 4 and continue.
> The __builtin_constant_p() path of the PPC's WARN_ON() calls (indirectly)
> __WARN_FLAGS() which has
Anshuman Khandual writes:
> On 06/14/2017 12:12 AM, Naveen N. Rao wrote:
>> On P9, trying to use data breakpoints throws the splat shown below (*).
>> This is because the check for a data breakpoint in DSISR is in
>> do_hash_page(). Move this check to
Christoph Hellwig writes:
> DMA_ERROR_CODE is going to go away, so don't rely on it. Instead
> define a ->mapping_error method for all IOMMU based dma operation
> instances. The direct ops don't ever return an error and don't
> need a ->mapping_error method.
>
> Signed-off-by:
On Thu, Jun 08, 2017 at 03:25:28PM +0200, Christoph Hellwig wrote:
> DMA_ERROR_CODE is not a public API and will go away. Instead properly
> unwind based on the loop counter.
Acked-By: Vinod Koul
--
~Vinod
Le 13/06/2017 à 09:37, Heiko Schocher a écrit :
Hello Christophe,
Am 13.06.2017 um 07:40 schrieb Christophe LEROY:
Le 13/06/2017 à 07:26, Christophe LEROY a écrit :
There was for long time no activity in the 8xx area.
We need to go further and convert to Kconfig, but it
turned out, nobody
Masahiro Yamada writes:
> 2017-06-13 19:21 GMT+09:00 Michael Ellerman :
>> Masahiro Yamada writes:
>>>
>>> (+Anatolij Gustschin )
>>>
>>> Ping.
>>> I am not 100% sure who is responsible for this,
On Wed, Jun 14, 2017 at 10:43:30AM +0530, Aneesh Kumar K.V wrote:
>
>
> On Wednesday 14 June 2017 10:41 AM, Naveen N. Rao wrote:
> >Hi Aneesh,
> >
> >On 2017/06/14 08:38AM, Aneesh Kumar K.V wrote:
> >>"Naveen N. Rao" writes:
> >>
> >>>On P9, trying to use data
On Wednesday 14 June 2017 10:23 AM, Michael Ellerman wrote:
I don't get this, the arch should always be powerpc.
Right. Something else is fubar for that to happen, we should fix
whatever it is.
Agree, ARCH over-ruling by reading the underlying architecture will
not work, as the expectation is
"Aneesh Kumar K.V" writes:
> On Wednesday 14 June 2017 10:41 AM, Naveen N. Rao wrote:
>> On 2017/06/14 08:38AM, Aneesh Kumar K.V wrote:
>>> "Naveen N. Rao" writes:
diff --git a/arch/powerpc/kernel/exceptions-64s.S
On 06/14/2017 12:12 AM, Naveen N. Rao wrote:
> On P9, trying to use data breakpoints throws the splat shown below (*).
> This is because the check for a data breakpoint in DSISR is in
> do_hash_page(). Move this check to handle_page_fault() so as to catch
> data breakpoints in both hash and radix
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