Ram Pai writes:
> On Wed, Oct 18, 2017 at 02:42:56PM +1100, Balbir Singh wrote:
>> On Fri, 8 Sep 2017 15:44:57 -0700
>> Ram Pai wrote:
>>
>> > powerpc has hardware support to disable execute on a pkey.
>> > This patch enables the ability to create execute-disabled
>> > keys.
>> >
>> > Signed-
Ram Pai writes:
+
> +#define mm_set_pkey_is_allocated(mm, pkey) \
> + (mm_pkey_allocation_map(mm) & pkey_alloc_mask(pkey))
> +
> static inline bool mm_pkey_is_allocated(struct mm_struct *mm, int pkey)
> {
> - return (pkey == 0);
> + /* a reserved key is never considered as 'expli
Ram Pai writes:
> Introduce helper functions that can initialize the bits in the AMR,
> IAMR and UAMOR register; the bits that correspond to the given pkey.
>
> Signed-off-by: Ram Pai
> ---
> arch/powerpc/include/asm/pkeys.h |1 +
> arch/powerpc/mm/pkeys.c | 46
> ++
Nathan Fontenot writes:
> diff --git a/arch/powerpc/mm/drmem.c b/arch/powerpc/mm/drmem.c
> new file mode 100644
> index ..8ad7cf36b2c4
> --- /dev/null
> +++ b/arch/powerpc/mm/drmem.c
> @@ -0,0 +1,84 @@
> +/*
> + * Dynamic reconfiguration memory support
> + *
> + * Copyright 2017 IBM C
Ram Pai writes:
> powerpc has hardware support to disable execute on a pkey.
> This patch enables the ability to create execute-disabled
> keys.
Can you summarize here how this works? Access to IAMR is
privileged so how will keys framework work with IAMR?
-aneesh
On 10/24/2017 12:52 AM, Ram Pai wrote:
On Thu, Sep 14, 2017 at 06:13:57PM +1000, Benjamin Herrenschmidt wrote:
On Fri, 2017-09-08 at 15:44 -0700, Ram Pai wrote:
The second part of the PTE will hold
(H_PAGE_F_SECOND|H_PAGE_F_GIX) at bit 60,61,62,63.
NOTE: None of the bits in the secondary PTE
Hi all,
Could anybody review this patchset and take action on them? Thank you!
Best Regards
Qiang Zhao
> -Original Message-
> From: Zhao Qiang [mailto:qiang.z...@nxp.com]
> Sent: Monday, August 07, 2017 11:07 AM
> To: t...@linutronix.de
> Cc: o...@buserror.net; Xiaobo Xie ; linux-
> ker.
On Mon, Oct 23, 2017 at 02:22:44PM +0530, Aneesh Kumar K.V wrote:
> Benjamin Herrenschmidt writes:
>
> > On Fri, 2017-09-08 at 15:44 -0700, Ram Pai wrote:
> >> The second part of the PTE will hold
> >> (H_PAGE_F_SECOND|H_PAGE_F_GIX) at bit 60,61,62,63.
> >> NOTE: None of the bits in the secondary
-spinloop-when-possible/20171023-173012
base: https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git next
config: powerpc-iss476-smp_defconfig (attached as .config)
compiler: powerpc-linux-gnu-gcc (Debian 6.1.1-9) 6.1.1 20160705
reproduce:
wget
https://raw.githubusercontent.com/intel
On Thu, Sep 14, 2017 at 06:11:32PM +1000, Benjamin Herrenschmidt wrote:
> On Thu, 2017-09-14 at 14:38 +1000, Balbir Singh wrote:
> > On Fri, 8 Sep 2017 15:44:50 -0700
> > Ram Pai wrote:
> >
> > > powerpc needs an additional vma bit to support 32 keys.
> > > Till the additional vma bit lands in i
-spinloop-when-possible/20171023-173012
base: https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git next
config: powerpc-ge_imp3a_defconfig (attached as .config)
compiler: powerpc-linux-gnu-gcc (Debian 6.1.1-9) 6.1.1 20160705
reproduce:
wget
https://raw.githubusercontent.com/intel
On Sat, Oct 21, 2017 at 11:47:03AM -0400, Jerome Glisse wrote:
> On Sat, Oct 21, 2017 at 04:54:40PM +1100, Balbir Singh wrote:
> > On Thu, 2017-10-19 at 12:58 -0400, Jerome Glisse wrote:
> > > On Thu, Oct 19, 2017 at 09:53:11PM +1100, Balbir Singh wrote:
> > > > On Thu, Oct 19, 2017 at 2:28 PM, Jer
> [3.537780] lpar: Attempting to resize HPT to shift 21
> [3.539251] Unable to resize hash page table to target order 21: -1
> [3.541079] Unable to create mapping for hot added memory
> 0xc0002100..0xc00021000400: -2
> For #1 above please check if your qemu supports H_RES
On Thu, Sep 14, 2017 at 06:13:57PM +1000, Benjamin Herrenschmidt wrote:
> On Fri, 2017-09-08 at 15:44 -0700, Ram Pai wrote:
> > The second part of the PTE will hold
> > (H_PAGE_F_SECOND|H_PAGE_F_GIX) at bit 60,61,62,63.
> > NOTE: None of the bits in the secondary PTE were not used
> > by 64k-HPTE b
On Mon, Oct 23, 2017 at 03:13:45PM +0530, Aneesh Kumar K.V wrote:
> Balbir Singh writes:
>
> > On Fri, 8 Sep 2017 15:44:54 -0700
> > Ram Pai wrote:
> >
> >> cleanup the bits corresponding to a key in the AMR, and IAMR
> >> register, when the key is newly allocated/activated or is freed.
> >> We
On Mon, Oct 23, 2017 at 03:13:33PM +0530, Aneesh Kumar K.V wrote:
> Ram Pai writes:
>
> > cleanup the bits corresponding to a key in the AMR, and IAMR
> > register, when the key is newly allocated/activated or is freed.
> > We dont want some residual bits cause the hardware enforce
> > unintended
On Mon, Oct 23, 2017 at 03:11:28PM +0530, Aneesh Kumar K.V wrote:
> Ram Pai writes:
>
> > Total 32 keys are available on power7 and above. However
> > pkey 0,1 are reserved. So effectively we have 30 pkeys.
>
> When you say reserved, reserved by whom? Is that part of ISA or PAPR ?
> Also do yo
On Mon, Oct 23, 2017 at 02:58:55PM +0530, Aneesh Kumar K.V wrote:
> "Aneesh Kumar K.V" writes:
>
> > Ram Pai writes:
> >
> >> powerpc needs an additional vma bit to support 32 keys.
> >> Till the additional vma bit lands in include/linux/mm.h
> >> we have to define it in powerpc specific heade
On Mon, Oct 23, 2017 at 02:55:51PM +0530, Aneesh Kumar K.V wrote:
> Ram Pai writes:
>
> > powerpc needs an additional vma bit to support 32 keys.
> > Till the additional vma bit lands in include/linux/mm.h
> > we have to define it in powerpc specific header file.
> > This is needed to get pkey
Use safer string manipulation functions when dealing with a
user-provided string in kprobe_lookup_name().
Reported-by: David Laight
Signed-off-by: Naveen N. Rao
---
arch/powerpc/kernel/kprobes.c | 47 ++-
1 file changed, 20 insertions(+), 27 deletions(-)
Commit 3cdfcbfd32b9d ("powerpc: Change analyse_instr so it doesn't
modify *regs") introduced emulate_update_regs() to perform part of what
emulate_step() was doing earlier. However, this function was not added
to the kprobes blacklist. Add it so as to prevent it from being probed.
Signed-off-by: N
Per Documentation/kprobes.txt, we don't necessarily need to disable
interrupts before invoking the kprobe handlers. Masami submitted
similar changes for x86 via commit a19b2e3d783964 ("kprobes/x86: Remove
IRQ disabling from ftrace-based/optimized kprobes"). Do the same for
powerpc.
Signed-off-by:
Per Documentation/kprobes.txt, probe handlers need to be invoked with
preemption disabled. Update optimized_callback() to do so. Also move
get_kprobe_ctlblk() invocation post preemption disable, since it
accesses pre-cpu data.
This was not an issue so far since optprobes wasn't selected if
CONFIG_
On Mon, Oct 23, 2017 at 02:17:39PM +0530, Aneesh Kumar K.V wrote:
> Michael Ellerman writes:
>
> > Ram Pai writes:
> >
> >> diff --git a/arch/powerpc/mm/hash64_64k.c b/arch/powerpc/mm/hash64_64k.c
> >> index 1a68cb1..c6c5559 100644
> >> --- a/arch/powerpc/mm/hash64_64k.c
> >> +++ b/arch/powerpc/
To: linuxppc-dev@lists.ozlabs.org
To: linux-ker...@vger.kernel.org
Cc: Michael Ellerman
Cc: Michael Bringmann
Cc: John Allen
Cc: Nathan Fontenot
Subject: [PATCH V3 2/2] pseries/initnodes: Ensure nodes initialized for hotplug
pseries/nodes: On pseries systems which allow 'hot-add' of CPU,
it ma
pseries/nodes: On pseries systems which allow 'hot-add' of CPU or
memory resources, it may occur that the new resources are to be
inserted into nodes that were not used for these resources at bootup.
In the kernel, any node that is used must be defined and initialized.
This patch ensures that suffi
pseries/nodes: Ensure enough nodes avail for operations
pseries/initnodes: Ensure nodes initialized for hotplug
Signed-off-by: Michael Bringmann
Michael Bringmann (2):
pseries/nodes: Ensure enough nodes avail for operations
pseries/initnodes: Ensure nodes initialized for hotplug
On Thu, Oct 19, 2017 at 04:58:23PM +, alexander.stef...@infineon.com wrote:
> > On Tue, Oct 17, 2017 at 11:50:05AM +, alexander.stef...@infineon.com
> > wrote:
> > > > > Replace the specification of data structures by pointer dereferences
> > > > > as the parameter for the operator "sizeof"
On Sat, Oct 21, 2017 at 11:58:47AM +1100, Michael Neuling wrote:
> On Fri, 2017-10-20 at 09:45 -0200, Breno Leitao wrote:
> > Mikey, Cyril,
> >
> > On Thu, Oct 12, 2017 at 09:17:16PM +1100, Michael Ellerman wrote:
> > > From: Cyril Bur
> > >
> > > Currently the kernel relies on firmware to infor
Ram Pai writes:
> Total 32 keys are available on power7 and above. However
> pkey 0,1 are reserved. So effectively we have 30 pkeys.
When you say reserved, reserved by whom? Is that part of ISA or PAPR ?
Also do you expect that to change. If not why all these indirection?
Can we have the mask
Ram Pai writes:
> powerpc needs an additional vma bit to support 32 keys.
> Till the additional vma bit lands in include/linux/mm.h
> we have to define it in powerpc specific header file.
> This is needed to get pkeys working on power.
>
> Signed-off-by: Ram Pai
> ---
> arch/powerpc/include/
Michael Ellerman writes:
> Ram Pai writes:
>
>> diff --git a/arch/powerpc/mm/hash64_64k.c b/arch/powerpc/mm/hash64_64k.c
>> index 1a68cb1..c6c5559 100644
>> --- a/arch/powerpc/mm/hash64_64k.c
>> +++ b/arch/powerpc/mm/hash64_64k.c
>> @@ -126,18 +113,13 @@ int __hash_page_4K(unsigned long ea, unsi
Balbir Singh writes:
> On Fri, 8 Sep 2017 15:44:54 -0700
> Ram Pai wrote:
>
>> cleanup the bits corresponding to a key in the AMR, and IAMR
>> register, when the key is newly allocated/activated or is freed.
>> We dont want some residual bits cause the hardware enforce
>> unintended behavior wh
Ram Pai writes:
> cleanup the bits corresponding to a key in the AMR, and IAMR
> register, when the key is newly allocated/activated or is freed.
> We dont want some residual bits cause the hardware enforce
> unintended behavior when the key is activated or freed.
>
> Signed-off-by: Ram Pai
> --
"Aneesh Kumar K.V" writes:
> Ram Pai writes:
>
>> powerpc needs an additional vma bit to support 32 keys.
>> Till the additional vma bit lands in include/linux/mm.h
>> we have to define it in powerpc specific header file.
>> This is needed to get pkeys working on power.
>>
>> Signed-off-by: R
Benjamin Herrenschmidt writes:
> On Fri, 2017-09-08 at 15:44 -0700, Ram Pai wrote:
>> The second part of the PTE will hold
>> (H_PAGE_F_SECOND|H_PAGE_F_GIX) at bit 60,61,62,63.
>> NOTE: None of the bits in the secondary PTE were not used
>> by 64k-HPTE backed PTE.
>
> Have you measured the perfor
On Mon, 2017-10-23 at 09:01 +, David Laight wrote:
> From: Michael Neuling
> > Sent: 21 October 2017 02:00
> > To: David Laight; 'Breno Leitao'; Michael Ellerman
> > Cc: stew...@linux.vnet.ibm.com; linuxppc-...@ozlabs.org; cyril...@gmail.com
> > Subject: Re: [PATCH 1/4] powerpc/tm: Add commandl
From: Michael Neuling
> Sent: 21 October 2017 02:00
> To: David Laight; 'Breno Leitao'; Michael Ellerman
> Cc: stew...@linux.vnet.ibm.com; linuxppc-...@ozlabs.org; cyril...@gmail.com
> Subject: Re: [PATCH 1/4] powerpc/tm: Add commandline option to disable
> hardware transactional memory
>
> On Fr
On (10/20/17 15:08), Petr Mladek wrote:
> On Thu 2017-10-19 15:42:35, Sergey Senozhatsky wrote:
> > Sorry for the delay and thanks for taking a look.
> >
> > I'll try to re-spin the patch set by the end of this week/early next
> > week.
> >
> >
> > On (10/04/17 13:53), Petr Mladek wrote:
> > [..
On Saturday 21 October 2017 06:29 AM, Balbir Singh wrote:
On Fri, 2017-10-20 at 14:07 +0200, Torsten Duwe wrote:
On Wed, Oct 18, 2017 at 11:47:35AM +0530, Kamalesh Babulal wrote:
Consider a trivial patch, supplied to kpatch tool for generating a
livepatch module:
--- a/fs/proc/meminfo.c
+++ b
The pcidev value stored in pci_dn is only used for NPU/NPU2
initialization. We can easily drop the cached pointer and
use an ancient helper - pci_get_domain_bus_and_slot() instead in order
to reduce complexity.
Signed-off-by: Alexey Kardashevskiy
---
arch/powerpc/include/asm/pci-bridge.h | 2
OPAL boot does not insert secondaries at 0x60 to wait at the secondary
hold spinloop. Instead they are started later, and inserted at
generic_secondary_smp_init(), which is after the secondary hold
spinloop.
Avoid waiting on this spinloop when booting with OPAL firmware. This
wait always times out
Use the NMI IPI rather than smp_call_function for smp_send_stop.
Have stopped CPUs hard disable interrupts rather than just soft
disable.
This function is used in crash/panic/shutdown paths to bring other
CPUs down as quickly and reliably as possible, and minimizing their
potential to cause troubl
Currently powernv reboot and shutdown requests just leave secondaries
to do their own things. This is undesirable because they can trigger
any number of watchdogs while waiting for reboot, but also we don't
know what else they might be doing, or they might be stuck somewhere
causing trouble.
The o
I've made this series only avoid the secondary spinloop on powernv.
pSeries is a little bit more complicated, some cases in kexec the
secondaries will be at 0x60. I haven't had time to get all that
sorted out for this merge window, so OPAL-only this time.
Nicholas Piggin (3):
powerpc/powernv: Al
Close the recoverability gap for OPAL calls by using FIXUP_ENDIAN_HV
in the return path.
Signed-off-by: Nicholas Piggin
---
arch/powerpc/platforms/powernv/opal-wrappers.S | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/platforms/powernv/opal-wrappers.S
b/arc
Add an HV variant of FIXUP_ENDIAN which uses HSRR[01] and does not
clear MSR[RI], which improves recoverability.
Signed-off-by: Nicholas Piggin
---
arch/powerpc/include/asm/ppc_asm.h | 22 ++
1 file changed, 22 insertions(+)
diff --git a/arch/powerpc/include/asm/ppc_asm.h
b
Signed-off-by: Nicholas Piggin
---
arch/powerpc/include/asm/ppc_asm.h | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/include/asm/ppc_asm.h
b/arch/powerpc/include/asm/ppc_asm.h
index 36f3e41c9fbe..d6b56aebe602 100644
--- a/arch/powerpc/include/asm/ppc_asm.h
Here's a few patches to improve recoverability for FIXUP_ENDIAN
on powernv. We should try to minimise SRR[01] (and MSR[RI]=0) usage
as much as possible. Whether that's by using HSRR or mtmsrd, it
usually results in faster and smaller code too.
There's a few other places we can improve, but I've ha
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