Hi all,
After merging the powerpc tree, today's linux-next build (powerpc64
allnoconfig) failed like this:
arch/powerpc/kernel/irq.o: In function `.replay_system_reset':
irq.c:(.text+0x10): undefined reference to `.ppc_save_regs'
Caused by commit
78adf6c214f0 ("powerpc/64s: Implement system r
On Tuesday 31 October 2017 07:49 PM, Naveen N . Rao wrote:
Hi Kamalesh,
Sorry for the late review. Overall, the patch looks good to me. So:
Acked-by: Naveen N. Rao
However, I have a few minor comments which can be addressed in a
subsequent patch.
Thanks for the review.
[...]
diff --git a/
You are welcome! :)
On Thu, Nov 02, 2017 at 01:44:07PM +1100, Cyril Bur wrote:
On Thu, 2017-11-02 at 10:19 +0800, kbuild test robot wrote:
Hi Cyril,
Thank you for the patch! Yet something to improve:
Once again robot, you have done brilliantly! You're 100% correct and
the last thing I want
There are two cases outside the normal address space management
where a CPU's local TLB is to be flushed:
1. Booting the kernel, in case something has left stale entries in
the TLB (e.g., kexec).
2. Machine check, to clean corrupted TLB entries.
CPU state restore from deep idle states a
On 11/01/2017 03:47 PM, Anshuman Khandual wrote:
> Deferred flushing can only be enabled on POWER9 DD2.0 processor onwards.
> Because prior versions of POWER9 and previous hash table based POWER
> processors will do TLB flushing in pte_get_and_clear() function itself
> which then prevents batching
On Thu, Nov 02, 2017 at 01:44:07PM +1100, Cyril Bur wrote:
> On Thu, 2017-11-02 at 10:19 +0800, kbuild test robot wrote:
> > Hi Cyril,
> >
> > Thank you for the patch! Yet something to improve:
> >
>
> Once again robot, you have done brilliantly! You're 100% correct and
> the last thing I want t
On Thu, 2 Nov 2017 08:49:49 +0530
Anshuman Khandual wrote:
> On 11/01/2017 07:09 PM, Nicholas Piggin wrote:
> > On Wed, 1 Nov 2017 17:35:51 +0530
> > Anshuman Khandual wrote:
> >
> >> On 10/31/2017 12:14 PM, Nicholas Piggin wrote:
> >>> Here's a random mix of performance improvements for ra
On 11/01/2017 07:09 PM, Nicholas Piggin wrote:
> On Wed, 1 Nov 2017 17:35:51 +0530
> Anshuman Khandual wrote:
>
>> On 10/31/2017 12:14 PM, Nicholas Piggin wrote:
>>> Here's a random mix of performance improvements for radix TLB flushing
>>> code. The main aims are to reduce the amount of translat
Lazy save and restore of FP/Altivec means that a userspace process can
be sent to userspace with FP or Altivec disabled and loaded only as
required (by way of an FP/Altivec unavailable exception). Transactional
Memory complicates this situation as a transaction could be started
without FP/Altivec b
After handling a transactional FP, Altivec or VSX unavailable exception.
The return to userspace code will detect that the TIF_RESTORE_TM bit is
set and call restore_tm_state(). restore_tm_state() will call
restore_math() to ensure that the correct facilities are loaded.
This means that all the lo
Lazy save and restore of FP/Altivec means that a userspace process can
be sent to userspace with FP or Altivec disabled and loaded only as
required (by way of an FP/Altivec unavailable exception). Transactional
Memory complicates this situation as a transaction could be started
without FP/Altivec b
Lazy save and restore of FP/Altivec means that a userspace process can
be sent to userspace with FP or Altivec disabled and loaded only as
required (by way of an FP/Altivec unavailable exception). Transactional
Memory complicates this situation as a transaction could be started
without FP/Altivec b
On Thu, 2017-11-02 at 10:19 +0800, kbuild test robot wrote:
> Hi Cyril,
>
> Thank you for the patch! Yet something to improve:
>
Once again robot, you have done brilliantly! You're 100% correct and
the last thing I want to do is break the build with
CONFIG_PPC_TRANSACTIONAL_MEM turned off.
Life
Hi Cyril,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on powerpc/next]
[also build test ERROR on v4.14-rc7 next-20171018]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci/linux/co
DD2.1 does not have to flush the ERAT after a state-loss idle. It also
does not have to save and restore MMCR0 (although it does have to save
restore in deep idle states, like other PMU registers).
Performance testing was done on a DD2.1 using only the stop0 idle state
(the shallowest state which
Cc: Michael Neuling
Signed-off-by: Nicholas Piggin
---
arch/powerpc/include/asm/cputable.h | 5 -
arch/powerpc/kernel/cputable.c | 20
arch/powerpc/kernel/dt_cpu_ftrs.c | 2 ++
3 files changed, 26 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/include/a
Chnages since v1:
- Change unnecessarily 'inverted else' conditions for the DD2.0
feature workarounds, noted by mpe.
- One of the cases was incorrect, removing the code in for DD2.0 and
leaving it in for 2.1. Performance is further slightly improved with
this case fixed.
Nicholas Piggin (
On Wed, 1 Nov 2017, Thomas Gleixner wrote:
> -Original Message-
> From: Thomas Gleixner [mailto:t...@linutronix.de]
> Sent: Thursday, November 02, 2017 1:10 AM
> To: Qiang Zhao
> Cc: Michael Ellerman ; Jason Cooper
> ; Marc Zyngier ;
> o...@buserror.net; linuxppc-dev@lists.ozlabs.org; X
On 01/11/17 05:19PM, Julien Thierry wrote:
> -Original Message-
> From: Julien Thierry [mailto:julien.thie...@arm.com]
> Sent: Wednesday, November 01, 2017 5:19 PM
> To: Qiang Zhao ; o...@buserror.net
> Cc: linuxppc-dev@lists.ozlabs.org; linux-arm-ker...@lists.infradead.org
> Subject: Re:
On Wed, 2017-11-01 at 15:23 -0400, Gustavo Romero wrote:
> Add a self test to check if FP/VEC/VSX registers are sane (restored
> correctly) after a FP/VEC/VSX unavailable exception is caught during a
> transaction.
>
> This test checks all possibilities in a thread regarding the combination
> of M
Hi all,
Today's linux-next merge of the powerpc tree got a conflict in:
arch/powerpc/mm/tlb-radix.c
between commit:
26e53d5ebe2e ("powerpc/64s/radix: Fix preempt imbalance in TLB flush")
from the powerpc-fixes tree and commit:
6773027205ea ("powerpc/mm/radix: Drop unneeded NULL check")
This patch implements and enables VDP support for the ibmvnic driver.
Moreover, it includes the implementation of suitable structs, signal
transmission/handling and functions which allows the retrival of firmware
information from the ibmvnic card.
Signed-off-by: Desnes A. Nunes do Rosario
Signe
This patch implements and enables VDP support for the ibmvnic driver. Moreover,
it includes the implementation of suitable structs, signal
transmission/handling and fuctions which allows the retrival of firmware
information from the ibmvnic card.
Co-Authored-By: Thomas Falcon
---
drivers/net/
Add a self test to check if FP/VEC/VSX registers are sane (restored
correctly) after a FP/VEC/VSX unavailable exception is caught during a
transaction.
This test checks all possibilities in a thread regarding the combination
of MSR.[FP|VEC] states in a thread and for each scenario raises a
FP/VEC/
pseries/nodes: On pseries systems which allow 'hot-add' of CPU,
it may occur that the new resources are to be inserted into nodes
that were not used for memory resources at bootup. Many different
configurations of PowerPC resources may need to be supported depending
upon the environment. This pat
pseries/nodes: On pseries systems which allow 'hot-add' of CPU or
memory resources, it may occur that the new resources are to be
inserted into nodes that were not used for these resources at bootup.
In the kernel, any node that is used must be defined and initialized.
This patch ensures that suffi
pseries/nodes: Ensure enough nodes avail for operations
pseries/initnodes: Ensure nodes initialized for hotplug
Signed-off-by: Michael Bringmann
Michael Bringmann (2):
pseries/nodes: Ensure enough nodes avail for operations
pseries/initnodes: Ensure nodes initialized for hotplug
---
Changes
On Tue, Oct 31, 2017 at 10:53 PM, Stephen Rothwell
wrote:
> Hi all,
>
> Today's linux-next merge of the tip tree got a conflict in:
>
> arch/powerpc/mm/numa.c
>
> between commit:
>
> cee5405da402 ("powerpc/hotplug: Improve responsiveness of hotplug change")
>
> from the powerpc tree and commi
> > diff --git a/drivers/net/ethernet/ibm/ibmvnic.c
> > b/drivers/net/ethernet/ibm/ibmvnic.c
> > index d0cff28..120f3c0 100644
> > --- a/drivers/net/ethernet/ibm/ibmvnic.c
> > +++ b/drivers/net/ethernet/ibm/ibmvnic.c
> > @@ -107,6 +107,9 @@ static union sub_crq *ibmvnic_next_scrq(struct
> > ibmvn
On Wed, 1 Nov 2017, Qiang Zhao wrote:
> Michael Ellerman wrote
> >
> > Qiang Zhao writes:
> >
> > > Hi all,
> > >
> > > Could anybody review this patchset and take action on them? Thank you!
> >
> > Who maintains this? I don't actually know, it's not powerpc code, or is it?
>
> Yes, it's not
On 11/01/2017 09:39 AM, Desnes Augusto Nunes do Rosario wrote:
> This patch implements and enables VDP support for the ibmvnic driver.
> Moreover, it includes the implementation of suitable structs, signal
> transmission/handling and fuctions which allows the retrival of firmware
> information f
On 11/01, Petr Mladek wrote:
>
> On Tue 2017-10-31 12:48:52, Miroslav Benes wrote:
> > + if (task->flags & PF_KTHREAD) {
> > + /*
> > +* Wake up a kthread which still has not been migrated.
> > +*/
> > + wake_up_p
On Tue 2017-10-31 12:48:52, Miroslav Benes wrote:
> Live patching consistency model is of LEAVE_PATCHED_SET and
> SWITCH_THREAD. This means that all tasks in the system have to be marked
> one by one as safe to call a new patched function. Safe means when a
> task is not (sleeping) in a set of patc
> +/*
> + * Sends a fake signal to all non-kthread tasks with TIF_PATCH_PENDING set.
> + * Kthreads with TIF_PATCH_PENDING set are woken up. Only admin can request
> this
> + * action currently.
> + */
> +void klp_force_signals(void)
> +{
> + struct task_struct *g, *task;
> +
> + pr_notic
On Wed, 1 Nov 2017 17:35:51 +0530
Anshuman Khandual wrote:
> On 10/31/2017 12:14 PM, Nicholas Piggin wrote:
> > Here's a random mix of performance improvements for radix TLB flushing
> > code. The main aims are to reduce the amount of translation that gets
> > invalidated, and to reduce global fl
On 10/31/2017 12:14 PM, Nicholas Piggin wrote:
> Here's a random mix of performance improvements for radix TLB flushing
> code. The main aims are to reduce the amount of translation that gets
> invalidated, and to reduce global flushes where we can do local.
>
> To that end, a parallel kernel comp
On Sun, Oct 29, 2017 at 05:51:06PM -0700, Ram Pai wrote:
> On Mon, Oct 30, 2017 at 09:04:17AM +1100, Paul Mackerras wrote:
> > On Sat, Oct 28, 2017 at 03:35:32PM -0700, Ram Pai wrote:
> > >
> > > I like the idea of not tracking the slots at all. It is something the
> > > guest should not be knowin
Deferred flushing can only be enabled on POWER9 DD2.0 processor onwards.
Because prior versions of POWER9 and previous hash table based POWER
processors will do TLB flushing in pte_get_and_clear() function itself
which then prevents batching and eventual flush completion later on.
Signed-off-by: A
The entire scheme of deferred TLB flush in reclaim path rests on the
fact that the cost to refill TLB entries is less than flushing out
individual entries by sending IPI to remote CPUs. But architecture
can have different ways to evaluate that. Hence apart from checking
TTU_BATCH_FLUSH in the TTU f
From: Anshuman Khandual
Batched TLB flush during reclaim path has been around for couple of years
now and been enabled on X86 platform. The idea is to batch multiple page
TLB invalidation requests together and flush all those CPUs completely
who might have the TLB cache for any of the unmapped pa
On Wednesday 01 November 2017 06:22 AM, Michael Ellerman wrote:
Anju T Sudhakar writes:
Call trace observed during boot:
What's the actual oops?
I could recreate this in mambo with CPUS=2 and THREAD=2
Here is the complete stack trace.
[ 0.045367] core_imc memory allocation for cpu 2 f
Hi Zhao,
I just noticed a small nit.
On 01/11/17 02:01, Zhao Qiang wrote:
QE was supported on PowerPC, and dependent on PPC,
Now it is supported on other platforms. so remove PPCisms.
Signed-off-by: Zhao Qiang
---
Changes for v2:
- na
Changes for v3:
- add NO_IRQ
Changes for v
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