Re: [PATCH 5/6] dma-mapping: support fsl-mc bus

On Tue, Mar 06, 2018 at 04:41:56AM +, Nipun Gupta wrote: > Sorry for asking a trivial question - looking into dma_configure() I see that > PCI is used in the start and the end of the API. > In the end part pci_put_host_bridge_device() is called. > So are two bus callbacks something like

[PATCH RFC 5/5] KVM: PPC: Book3S HV: Work around TEXASR bug in fake suspend mode

This works around a hardware bug in "Nimbus" POWER9 DD2.2 processors, where the contents of the TEXASR can get corrupted while a thread is in fake suspend state. The workaround is for the instruction emulation code to use the value saved at the most recent guest exit in real suspend mode. We

[PATCH RFC 0/5] powerpc & KVM: Work around POWER9 TM hardware bugs

POWER9 has some shortcomings in its implementation of transactional memory. Starting with v2.2 of the "Nimbus" chip, some changes have been made to the hardware which make it able to generate hypervisor interrupts in the situations where hardware needs the hypervisor to provide some assistance

[PATCH RFC 3/5] KVM: PPC: Book3S HV: Work around transactional memory bugs in POWER9

POWER9 has hardware bugs relating to transactional memory and thread reconfiguration (changes to hardware SMT mode). Specifically, the core does not have enough storage to store a complete checkpoint of all the architected state for all four threads. The DD2.2 version of POWER9 includes hardware

[PATCH RFC 1/5] powerpc: Add a CPU feature bit for TM bug workarounds on POWER9 v2.2

This adds a CPU feature bit which is set for POWER9 "Nimbus" DD2.2 processors which will be used to enable the hypervisor to assist hardware with the handling of checkpointed register values while the CPU is in suspend state, in order to work around hardware bugs. When the dt_cpu_ftrs subsystem

[PATCH RFC 2/5] powerpc/powernv: Provide a way to force a core into SMT4 mode

POWER9 processors up to and including "Nimbus" v2.2 have hardware bugs relating to transactional memory and thread reconfiguration. One of these bugs has a workaround which is to get the core into SMT4 state temporarily. This workaround is only needed when running bare-metal. This patch provides

[PATCH RFC 4/5] KVM: PPC: Book3S HV: Work around XER[SO] bug in fake suspend mode

From: Suraj Jitindar Singh This works around a hardware bug in "Nimbus" POWER9 DD2.2 processors, where a treclaim performed in fake suspend mode can cause subsequent reads from the XER register to return inconsistent values for the SO (summary overflow) bit. The

Re: [PATCH v3] powerpc/npu-dma.c: Fix deadlock in mmio_invalidate

Michael, This won't apply cleanly on top of Balbir's MMIO ATSD Flushing patch (https://patchwork.ozlabs.org/patch/848343/). I will resend a v4 which applies cleanly on top of that as the rebase/merge is non-trivial. - Alistair On Friday, 2 March 2018 4:18:45 PM AEDT Alistair Popple wrote: >

Re: [RFC PATCH 1/1] powerpc/ftrace: Exclude real mode code from

"Naveen N. Rao" writes: > We can't take a trap in most parts of real mode code. Instead of adding > the 'notrace' annotation to all C functions that can be invoked from > real mode, detect that we are in real mode on ftrace entry and return > back. > >

[PATCH 4/4] powerpc/xmon: Move empty plpar_set_ciabr() into plpar_wrappers.h

Now that plpar_wrappers.h has an #ifdef PSERIES we can move the empty version of plpar_set_ciabr() which xmon wants into there. Signed-off-by: Michael Ellerman --- arch/powerpc/include/asm/plpar_wrappers.h | 6 ++ arch/powerpc/xmon/xmon.c | 7 +-- 2

[PATCH 3/4] powerpc: Rename plapr routines to plpar

Back in 2013 we added some hypercall wrappers which misspelled "plpar" (P-series Logical PARtition) as "plapr". Visually they're hard to distinguish and it almost doesn't matter, but it is confusing when grepping to miss some calls because of the typo. They've also started spreading, so before

[PATCH 2/4] powerpc/pseries: Make plpar_wrappers.h safe to include when PSERIES=n

Currently plpar_wrappers.h is not safe to include when CONFIG_PPC_PSERIES=n, or at least it can be depending on other config options and so on. Fix that by wrapping the entire content in an ifdef. Signed-off-by: Michael Ellerman ---

[PATCH 1/4] powerpc/pseries: Move smp_query_cpu_stopped() etc. out of plpar_wrappers.h

smp_query_cpu_stopped() and related #defines are currently in plpar_wrappers.h. The function actually does an RTAS call, not an hcall, and basically has nothing to do with plpar_wrappers.h Move it into pseries.h, where it can easily be used by the only two callers in pseries/smp.c and

Re: [PATCH 1/2] powerpc/mm/keys: Move pte bits to correct headers

On 03/08/2018 01:58 AM, Ram Pai wrote: On Wed, Mar 07, 2018 at 07:06:44PM +0530, Aneesh Kumar K.V wrote: Memory keys are supported only with hash translation mode. Instead of #ifdef in generic code move the key related pte bits to respective headers Signed-off-by: Aneesh Kumar K.V

Re: [PATCH 00/14] numa aware allocation for pacas, stacks, pagetables

On Wed, 07 Mar 2018 21:50:04 +1100 Michael Ellerman wrote: > Nicholas Piggin writes: > > > This series allows numa aware allocations for various early data > > structures for radix. Hash still has a bolted SLB limitation that > > prevents at least pacas

Re: [PATCH] powerpc/powernv/mce: Don't silently restart the machine

Balbir Singh writes: > On MCE the current code will restart the machine with > ppc_md.restart(). This case was extremely unlikely since > prior to that a skiboot call is made and that resulted in > a checkstop for analysis. > > With newer skiboots, on P9 we don't checkstop

[PATCH] powerpc/powernv/mce: Don't silently restart the machine

On MCE the current code will restart the machine with ppc_md.restart(). This case was extremely unlikely since prior to that a skiboot call is made and that resulted in a checkstop for analysis. With newer skiboots, on P9 we don't checkstop the box by default, instead we return back to the kernel

Re: [RFC v2 1/3] hotplug/mobility: Apply assoc updates for Post Migration Topo

Accepted Tyrel's change to dlpar_cpu_readd_by_index. The amendment will be included in the next version of the RFC. Michael On 03/07/2018 01:32 PM, Tyrel Datwyler wrote: > On 02/26/2018 12:52 PM, Michael Bringmann wrote: >> hotplug/mobility: Recognize more changes to the associativity of >>

Re: [PATCH 1/6] Docs: dt: add fsl-mc iommu-parent device-tree binding

On Mon, Mar 05, 2018 at 07:59:21PM +0530, Nipun Gupta wrote: > The existing IOMMU bindings cannot be used to specify the relationship > between fsl-mc devices and IOMMUs. This patch adds a binding for > mapping fsl-mc devices to IOMMUs, using a new iommu-parent property. > > Signed-off-by: Nipun

Re: [PATCH 17/21] powerpc: Add missing prototype for sys_debug_setcontext

On Sun, Mar 4, 2018 at 11:54 AM, Michael Ellerman wrote: > Mathieu Malaterre writes: > >> In commit 81e7009ea46c ("powerpc: merge ppc signal.c and ppc64 signal32.c") >> the function sys_debug_setcontext was added without a prototype. >> >> Fix compilation

[PATCH v2 05/21] powerpc: Avoid comparison of unsigned long >= 0 in pfn_valid

Rewrite comparison since all values compared are of type `unsigned long`. Instead of using unsigned properties and rewriting the original code as: (originally suggested by Segher Boessenkool ) #define pfn_valid(pfn) \ (((pfn) - ARCH_PFN_OFFSET) <

[PATCH v2 15/21] powerpc: Make function MMU_setup static

Since function `MMU_setup` is not meant to be exported, change the signature to `static`. Fix warning (treated as error with W=1): CC kernel/sys.o arch/powerpc/mm/init_32.c:102:13: error: no previous prototype for ‘MMU_setup’ [-Werror=missing-prototypes] void __init MMU_setup(void)

Re: [PATCH 1/2] powerpc/mm/keys: Move pte bits to correct headers

On Wed, Mar 07, 2018 at 07:06:44PM +0530, Aneesh Kumar K.V wrote: > Memory keys are supported only with hash translation mode. Instead of #ifdef > in > generic code move the key related pte bits to respective headers > > Signed-off-by: Aneesh Kumar K.V > --- >

Re: [RFC v2 1/3] hotplug/mobility: Apply assoc updates for Post Migration Topo

On 02/26/2018 12:52 PM, Michael Bringmann wrote: > hotplug/mobility: Recognize more changes to the associativity of > memory blocks described by the 'ibm,dynamic-memory' and 'cpu' > properties when processing the topology of LPARS in Post Migration > events. Previous efforts only recognized

Re: [RFC PATCH 1/1] powerpc/ftrace: Exclude real mode code from

On Thu, 08 Mar 2018 00:07:07 +0530 "Naveen N. Rao" wrote: > Yes, that's negligible. > Though, to be honest, I will have to introduce a 'mfmsr' for the older > -pg variant. I still think that the improved reliability far outweighs > the minor slowdown there. In

Re: [RFC PATCH 1/1] powerpc/ftrace: Exclude real mode code from

Hi Steve, Steven Rostedt wrote: On Wed, 7 Mar 2018 22:16:19 +0530 "Naveen N. Rao" wrote: We can't take a trap in most parts of real mode code. Instead of adding the 'notrace' annotation to all C functions that can be invoked from real mode, detect that we

Re: [RFC PATCH 1/1] powerpc/ftrace: Exclude real mode code from

On Wed, 7 Mar 2018 22:16:19 +0530 "Naveen N. Rao" wrote: > We can't take a trap in most parts of real mode code. Instead of adding > the 'notrace' annotation to all C functions that can be invoked from > real mode, detect that we are in real mode on ftrace entry

[RFC PATCH 1/1] powerpc/ftrace: Exclude real mode code from

We can't take a trap in most parts of real mode code. Instead of adding the 'notrace' annotation to all C functions that can be invoked from real mode, detect that we are in real mode on ftrace entry and return back. Signed-off-by: Naveen N. Rao --- This RFC only

[RFC PATCH 0/1] Exclude real mode code from ftrace

If the function tracer is enabled when starting a guest, we get the below oops: [ cut here ] Delta way too big! 17582052940437522358 ts=17582052944931114496 write stamp = 4493592138 Oops: Bad interrupt in KVM entry/exit code, sig: 6 [#1] LE SMP NR_CPUS=2048 NUMA PowerNV

[PATCH V2] powerpc/mm/hugetlb: initialize the pagetable cache correctly for hugetlb

With 64k page size, we have hugetlb pte entries at the pmd and pud level for book3s64. We don't need to create a separate page table cache for that. With 4k we need to make sure hugepd page table cache for 16M is placed at PUD level and 16G at the PGD level. Simplify all these by not using

Re: [PATCH 06/10] powerpc/mm/slice: implement slice_check_range_fits

Le 07/03/2018 à 08:16, Nicholas Piggin a écrit : On Wed, 7 Mar 2018 07:12:23 +0100 Christophe LEROY wrote: Le 07/03/2018 à 00:12, Nicholas Piggin a écrit : On Tue, 6 Mar 2018 15:41:00 +0100 Christophe LEROY wrote: Le 06/03/2018 à

[PATCH 2/2] powerpc/mm/keys: Update documentation in key fault handling

No functionality change in this patch. Adds more code comments. We also remove an unnecessary pkey check after we check for pkey error in this patch. Signed-off-by: Aneesh Kumar K.V --- arch/powerpc/mm/fault.c | 28

[PATCH 1/2] powerpc/mm/keys: Move pte bits to correct headers

Memory keys are supported only with hash translation mode. Instead of #ifdef in generic code move the key related pte bits to respective headers Signed-off-by: Aneesh Kumar K.V --- arch/powerpc/include/asm/book3s/64/hash-4k.h | 7 +++

[RFC PATCH] powerpc/mm/radix: Parse disable_radix commandline correctly.

kernel parameter disable_radix takes different options disable_radix=yes|no|1|0 or just disable_radix. When using the later format we get below error. `Malformed early option 'disable_radix'` We also update the command line parsing in prom_init to handle the new format. Signed-off-by: Aneesh

[PATCH] powerpc/mm/hash: Move the slb_addr_limit check within PPC_MM_SLICES

Should not have any impact, because we always select PP_MM_SLICES these days. Nevertheless it is good to indicate that slb_addr_limit is available only with slice code. Signed-off-by: Aneesh Kumar K.V --- arch/powerpc/mm/slb_low.S | 3 ++- 1 file changed, 2

[PATCH V4 0/3] Add support for 4PB virtual address space on hash

This patch series extended the max virtual address space value from 512TB to 4PB with 64K page size. We do that by allocating one vsid context for each 512TB range. More details of that is explained in patch 3. Changes from V3: * move extended_id to be a union with mm_context_t id. This reduce

[PATCH V4 3/3] powerpc/mm/hash: Don't memset pgd table if not needed

We need to zero-out pgd table only if we share the slab cache with pud/pmd level caches. With the support of 4PB, we don't share the slab cache anymore. Instead of removing the code completely hide it within an #ifdef. We don't need to do this with any other page table level, because they all

[PATCH V4 2/3] powerpc/mm/hash64: Increase the VA range

This patch increase the max virtual address value to 4PB. With 4K page size config we continue to limit ourself to 64TB. Signed-off-by: Aneesh Kumar K.V --- arch/powerpc/include/asm/book3s/64/hash-64k.h | 2 +- arch/powerpc/include/asm/processor.h | 9

[PATCH V4 1/3] powerpc/mm: Add support for handling > 512TB address in SLB miss

For address above 512TB we allocate additional mmu context. To make it all easy address above 512TB is handled with IR/DR=1 and with stack frame setup. We do the additional context allocation in SLB miss handler. If the context is not allocated, we enable interrupts and allocate the context and

Re: [PATCH 00/14] numa aware allocation for pacas, stacks, pagetables

On Wed, 07 Mar 2018 21:50:04 +1100 Michael Ellerman wrote: > Nicholas Piggin writes: > > > This series allows numa aware allocations for various early data > > structures for radix. Hash still has a bolted SLB limitation that > > prevents at least pacas

Re: [PATCH 00/14] numa aware allocation for pacas, stacks, pagetables

Nicholas Piggin writes: > This series allows numa aware allocations for various early data > structures for radix. Hash still has a bolted SLB limitation that > prevents at least pacas and stacks from node-affine allocations. > > Fixed up a number of bugs, got pSeries working,

Re: [PATCH v2 10/10] powerpc/mm/slice: use the dynamic high slice size to limit bitmap operations

Nicholas Piggin writes: > On Wed, 7 Mar 2018 11:37:18 +1000 > Nicholas Piggin wrote: > >> The number of high slices a process might use now depends on its >> address space size, and what allocation address it has requested. >> >> This patch uses that limit

[PATCH] PCI/hotplug: ppc: correct a php_slot usage after free

From: Simon Guo In pnv_php_unregister_one(), pnv_php_put_slot() might kfree php_slot structure. But there is pci_hp_deregister() after that with php_slot reference. This patch moves pnv_php_put_slot() to the end of function. Signed-off-by: Simon Guo