[PATCH 3/3] drivers/base: only reordering consumer device when probing

commit 52cdbdd49853 ("driver core: correct device's shutdown order") places an assumption of supplier<-consumer order on the process of probe. But it turns out to break down the parent <- child order in some scene. E.g in pci, a bridge is enabled by pci core, and behind it, the devices have been

[PATCH 2/3] drivers/base: reorder consumer and its children behind suppliers

commit 52cdbdd49853 ("driver core: correct device's shutdown order") introduces supplier<-consumer order in devices_kset. The commit tries to cleverly maintain both parent<-child and supplier<-consumer order by reordering a device when probing. This method makes things simple and clean, but

[PATCH 1/3] drivers/base: introduce some help routines for reordering a group of dev

This patch introduce some help routines used by next patch. It aims to ease reviewing, while the next patch will concentrate on algorithm. Cc: Greg Kroah-Hartman Cc: Grygorii Strashko Cc: Christoph Hellwig Cc: Bjorn Helgaas Cc: Dave Young Cc: linux-...@vger.kernel.org Cc:

[PATCH 0/3] drivers/base: bugfix for supplier<-consumer ordering in device_kset

commit 52cdbdd49853 ("driver core: correct device's shutdown order") places an assumption of supplier<-consumer order on the process of probe. But it turns out to break down the parent <- child order in some scene. E.g in pci, a bridge is enabled by pci core, and behind it, the devices have been

Re: [PATCH 7/7] powerpc/powernv/pci: Don't use the lower 4G TCEs in

On Sat, 23 Jun 2018 18:54:58 -0500 (CDT) Timothy Pearson wrote: > pseudo-DMA mode > > Four TCEs are reserved for legacy 32-bit DMA mappings in psuedo DMA > mode. Mark these with an invalid address to avoid their use by > the TCE cache mapper. Can we still have 32bit DMA in the case when

Re: [PATCH 6/7] powerpc/powernv/pci: Invalidate TCE cache after DMA map

On Sat, 23 Jun 2018 18:54:36 -0500 (CDT) Timothy Pearson wrote: > setup > > Per the IODA2, TCEs must be invalidated after their settings > have been changed. Invalidate the cache after the address > is changed during TCE allocation when using pseudo DMA. > > Signed-off-by: Timothy Pearson >

Re: [PATCH 4/7] powerpc/powernv/pci: Safety fixes for pseudobypass TCE

On Sat, 23 Jun 2018 18:53:54 -0500 (CDT) Timothy Pearson wrote: > allocation > > Signed-off-by: Russell Currey > --- > arch/powerpc/platforms/powernv/pci-dma.c | 6 -- > 1 file changed, 4 insertions(+), 2 deletions(-) > > diff --git a/arch/powerpc/platforms/powernv/pci-dma.c >

Re: [PATCH 2/7] powerpc/powernv: DMA operations for discontiguous

On Sat, 23 Jun 2018 18:53:02 -0500 (CDT) Timothy Pearson wrote: > allocation > > Cognitive DMA is a new set of DMA operations that solve some issues for > devices that want to address more than 32 bits but can't address the 59 > bits required to enable direct DMA. > > The previous

Re: [PATCH 1/7] powerpc/powernv/pci: Track largest available TCE order

On Sat, 23 Jun 2018 18:52:30 -0500 (CDT) Timothy Pearson wrote: > per PHB > > Knowing the largest possible TCE size of a PHB is useful, so get it out > of the device tree. This relies on the property being added in OPAL. > > It is assumed that any PHB4 or later machine would be running

Re: [patchV2 2/2] pci/shpchp: no claim on pcie port device

On Wed, Jun 13, 2018 at 9:13 PM Bjorn Helgaas wrote: > > On Wed, Jun 13, 2018 at 02:29:57PM +0800, Pingfan Liu wrote: > > The Linux Device Driver Model allows a physical device to be handled > > by only a single driver. But at present, both shpchp and portdrv_pci > > claim PCI_CLASS_BRIDGE_PCI,

[PATCH v2 1/2] powerpc: Document issues with the DAWR on POWER9

Signed-off-by: Michael Neuling Acked-by: Stewart Smith --- v2: Spelling mistakes :-/ --- Documentation/powerpc/DAWR-POWER9.txt | 58 +++ 1 file changed, 58 insertions(+) create mode 100644 Documentation/powerpc/DAWR-POWER9.txt diff --git

[PATCH v2 2/2] powerpc: Document issues with TM on POWER9

Signed-off-by: Michael Neuling --- v2: Spelling mistakes :-/ --- .../powerpc/transactional_memory.txt | 44 +++ 1 file changed, 44 insertions(+) diff --git a/Documentation/powerpc/transactional_memory.txt b/Documentation/powerpc/transactional_memory.txt index

Re: [PATCH 1/2] powerpc: Document issues with the DAWR on POWER9

On Fri, 2018-06-22 at 12:23 -0500, Segher Boessenkool wrote: > On Fri, Jun 22, 2018 at 04:14:51PM +1000, Michael Neuling wrote: > > +will accept the command. Unfortunatley since there is no hardware > > "unfortunately". > > > +speed since it can use the hardware emualation. Unfortnatley if this

Re: [PATCH 0/7] Add initial version of "cognitive DMA"

When should we be targeting merge? At this point this is a substantial improvement over currently shipping kernels for our systems, and we don't really want to have to ship a patched / custom OS kernel if we can avoid it. On 06/24/2018 08:09 PM, Russell Currey wrote: > On Sat, 2018-06-23 at

Re: [PATCH 0/7] Add initial version of "cognitive DMA"

On Sat, 2018-06-23 at 18:52 -0500, Timothy Pearson wrote: There's still more to do and this shouldn't be merged yet - would encourage anyone with suitable hardware to test though. > POWER9 (PHB4) requires all peripherals using DMA to be either > restricted > to 32-bit windows or capable of

Re: [PATCH v3 00/12] macintosh: Resolve various PMU driver problems

On Wed, 13 Jun 2018, I wrote: > Finn Thain (12): > macintosh/via-pmu: Fix section mismatch warning > macintosh/via-pmu: Add missing mmio accessors > macintosh/via-pmu: Don't clear shift register interrupt flag twice > macintosh/via-pmu: Enhance state machine with new 'uninitialized' >