Le 18/09/2018 à 07:48, Joel Stanley a écrit :
Hey Christophe,
On Tue, 18 Sep 2018 at 15:13, Christophe Leroy wrote:
Since commit cafa0010cd51 ("Raise the minimum required gcc version
to 4.6"), it is not possible to build kernel with GCC lower than 4.6
This patch removes checkbin tests
On Wed, 2018-09-12 at 16:40 -0300, Breno Leitao wrote:
> Since the transaction will be doomed with treckpt., the TEXASR[FS]
> should be set, to reflect that the transaction is a failure. This patch
> ensures it before recheckpointing, and remove changes from other places
> that were calling
Hey Christophe,
On Tue, 18 Sep 2018 at 15:13, Christophe Leroy wrote:
>
> Since commit cafa0010cd51 ("Raise the minimum required gcc version
> to 4.6"), it is not possible to build kernel with GCC lower than 4.6
>
> This patch removes checkbin tests addressing older versions of GCC.
This is the
Since commit cafa0010cd51 ("Raise the minimum required gcc version
to 4.6"), it is not possible to build kernel with GCC lower than 4.6
This patch removes checkbin tests addressing older versions of GCC.
Signed-off-by: Christophe Leroy
---
arch/powerpc/Makefile | 28
On Wed, 2018-09-12 at 16:40 -0300, Breno Leitao wrote:
> In the previous TM code, trecheckpoint was being executed in the middle of
> an exception, thus, DSCR was being restored to default kernel DSCR value
> after trecheckpoint was done.
>
> With this current patchset, trecheckpoint is executed
On Wed, 2018-09-12 at 16:40 -0300, Breno Leitao wrote:
> Make sure that we are not suspended on ptrace and that the registers were
> already reclaimed.
>
> Since the data was already reclaimed, there is nothing to be done here
> except to restore the SPRs.
>
> Signed-off-by: Breno Leitao
> ---
On Wed, 2018-09-12 at 16:40 -0300, Breno Leitao wrote:
> Do not recheckpoint at signal code return. Just make sure TIF_RESTORE_TM is
> set, which will restore on the exit to userspace by restore_tm_state.
Cool, but what about the same for reclaim? Why not avoid treclaim since it's
done on entry?
On Mon, Sep 03, 2018 at 10:07:33PM +0530, Aneesh Kumar K.V wrote:
> Current code doesn't do page migration if the page allocated is a compound
> page.
> With HugeTLB migration support, we can end up allocating hugetlb pages from
> CMA region. Also THP pages can be allocated from CMA region. This
On Wed, 2018-09-12 at 16:40 -0300, Breno Leitao wrote:
> __switch_to_tm is the function that switches between two tasks which might
> have TM enabled. This function is clearly split in two parts, the task that
> is leaving the CPU, known as 'prev' and the task that is being scheduled,
> known as
Disable new features from recent releases, and clean out some other
unused options:
- Enable EXPERT, so we can disable some things
- Disable non-powerpc BPF decoders
- Disable TASKSTATS
- Disable unused syscalls
- Set more things to be modules
- Turn off unused network vendors
-
On Wed, 2018-09-12 at 16:40 -0300, Breno Leitao wrote:
> Now the transaction reclaims happens very earlier in the trap handler, and
> it is impossible to know precisely, at that early time, what should be set
> as the failure cause for some specific cases, as, if the task will be
> rescheduled,
On Wed, 2018-09-12 at 16:40 -0300, Breno Leitao wrote:
> This patch creates a macro that will be invoked on all entrance to the
> kernel, so, in kernel space the transaction will be completely reclaimed
> and not suspended anymore.
There are still some calls to tm_reclaim_current() in process.c.
On Wed, 2018-09-12 at 16:40 -0300, Breno Leitao wrote:
> Now the transaction reclaims happens very earlier in the trap handler, and
> it is impossible to know precisely, at that early time, what should be set
> as the failure cause for some specific cases, as, if the task will be
> rescheduled,
On Tue, 18 Sep 2018 at 06:11, Nick Desaulniers wrote:
>
> On Fri, Sep 14, 2018 at 2:08 PM Segher Boessenkool
> wrote:
> >
> > On Fri, Sep 14, 2018 at 10:47:08AM -0700, Nick Desaulniers wrote:
> > > On Thu, Sep 13, 2018 at 9:07 PM Joel Stanley wrote:
> > > > 10:addis
Hi Scott,
Could you please take a look at this patch?
Thanks,
Andy
> -Original Message-
> From: andy.t...@nxp.com
> Sent: 2018年9月11日 10:12
> To: o...@buserror.net
> Cc: robh...@kernel.org; mark.rutl...@arm.com;
> b...@kernel.crashing.org; devicet...@vger.kernel.org;
>
4.18-stable review patch. If anyone has any objections, please let me know.
--
From: Christophe Leroy
[ Upstream commit 21b8732eb4479b579bda9ee38e62b2c312c2a0e5 ]
After update of kernel, the perf tool doesn't run anymore on my 32MB RAM
powerpc board, but still runs on a 128MB
4.14-stable review patch. If anyone has any objections, please let me know.
--
From: Christophe Leroy
[ Upstream commit 21b8732eb4479b579bda9ee38e62b2c312c2a0e5 ]
After update of kernel, the perf tool doesn't run anymore on my 32MB RAM
powerpc board, but still runs on a 128MB
[+cc Russell, Ben, Oliver, linuxppc-dev]
On Mon, Sep 17, 2018 at 11:55:43PM +0300, Sergey Miroshnichenko wrote:
> Hello Sam,
>
> On 9/17/18 8:28 AM, Sam Bobroff wrote:
> > Hi Sergey,
> >
> > On Fri, Sep 14, 2018 at 07:14:01PM +0300, Sergey Miroshnichenko wrote:
> >> Introduce a new command line
4.9-stable review patch. If anyone has any objections, please let me know.
--
From: Christophe Leroy
[ Upstream commit 21b8732eb4479b579bda9ee38e62b2c312c2a0e5 ]
After update of kernel, the perf tool doesn't run anymore on my 32MB RAM
powerpc board, but still runs on a 128MB
4.4-stable review patch. If anyone has any objections, please let me know.
--
From: Christophe Leroy
[ Upstream commit 21b8732eb4479b579bda9ee38e62b2c312c2a0e5 ]
After update of kernel, the perf tool doesn't run anymore on my 32MB RAM
powerpc board, but still runs on a 128MB
On Sat, Sep 15, 2018 at 6:11 AM YueHaibing wrote:
>
> if 'mode' is COMM_DIR_TX, 'shift' should use TX_SYNC_SHIFT_BASE
>
> Fixes: bb8b2062aff3 ("fsl/qe: setup clock source for TDM mode")
> Signed-off-by: YueHaibing
Thanks for submitting the patch, but there is already the same fix in
the queue
On 09/17/2018 12:14 PM, Nathan Fontenot wrote:
> When performing partition migrations all present CPUs must be online
> as all present CPUs must make the H_JOIN call as part of the migration
> process. Once all present CPUs make the H_JOIN call, one CPU is returned
> to make the rtas call to
When performing partition migrations all present CPUs must be online
as all present CPUs must make the H_JOIN call as part of the migration
process. Once all present CPUs make the H_JOIN call, one CPU is returned
to make the rtas call to perform the migration to the destination system.
During
On Wed, 5 Sep 2018 07:29:51 -0700
Guenter Roeck wrote:
> Hi,
>
> On Tue, Aug 28, 2018 at 09:20:34PM +1000, Nicholas Piggin wrote:
> > Similarly to the previous patch, this tries to optimise dirty/accessed
> > bits in ptes to avoid access costs of hardware setting them.
> >
>
> This patch
On Mon, Sep 17, 2018 at 12:15:08PM +, Christophe Leroy wrote:
> I would have liked to use -mstack-protector-guard=tls
> -mstack-protector-guard-reg=r2
> -mstack-protector-guard-offset=offsetof(struct task_struct, stack_canary)
> but I have
> not found how set the value of offsetof(struct
/linux/commits/Christophe-Leroy/powerpc-initial-stack-protector-fstack-protector-support/20180917-202227
base: https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git next
config: powerpc-ppc6xx_defconfig (attached as .config)
compiler: powerpc-linux-gnu-gcc (Debian 7.2.0-11) 7.2.0
Hi Michael,
Le 10/09/2018 à 16:28, Xin Long a écrit :
On Mon, Sep 10, 2018 at 2:09 PM Christophe Leroy
wrote:
On little endian platforms, csum_ipv6_magic() keeps len and proto in
CPU byte order. This generates a bad results leading to ICMPv6 packets
from other hosts being dropped by
Partially copied from commit df0698be14c66 ("ARM: stack protector:
change the canary value per task")
A new random value for the canary is stored in the task struct whenever
a new task is forked. This is meant to allow for different canary values
per task. On powerpc, GCC expects the canary
Partialy copied from commit c743f38013aef ("ARM: initial stack protector
(-fstack-protector) support")
This is the very basic stuff without the changing canary upon
task switch yet. Just the Kconfig option and a constant canary
value initialized at boot time.
This patch was tentatively added in
On Mon, Sep 10, 2018 at 09:42:04AM +0200, Ondrej Mosnacek wrote:
> commit 0522236d4f9c5ab2e79889cb020d1acbe5da416e upstream.
>
> Conflicts:
> drivers/crypto/vmx/
> aes_cbc.c - adapted enable/disable calls to v4.4 state
> aes_xts.c - did not exist yet in v4.4
Now applied, thanks.
greg
On Mon, Sep 10, 2018 at 09:42:04AM +0200, Ondrej Mosnacek wrote:
> commit 0522236d4f9c5ab2e79889cb020d1acbe5da416e upstream.
>
> Conflicts:
> drivers/crypto/vmx/
> aes_cbc.c - adapted enable/disable calls to v4.4 state
> aes_xts.c - did not exist yet in v4.4
We don't need these lines
On Wed, 12 Sep 2018 17:08:52 +0200
Arnd Bergmann wrote:
> The .ioctl and .compat_ioctl file operations have the same prototype so
> they can both point to the same function, which works great almost all
> the time when all the commands are compatible.
>
> One exception is the s390 architecture,
Le 17/09/2018 à 11:03, Aneesh Kumar K.V a écrit :
Christophe Leroy writes:
Hi,
I'm having a hard time figuring out the best way to handle the following
situation:
On the powerpc8xx, handling 16k size pages requires to have page tables
with 4 identical entries.
I assume that hugetlb
Christophe Leroy writes:
> Hi,
>
> I'm having a hard time figuring out the best way to handle the following
> situation:
>
> On the powerpc8xx, handling 16k size pages requires to have page tables
> with 4 identical entries.
I assume that hugetlb page size? If so isn't that similar to FSL
On Mon, 17 Sep 2018 11:38:35 +0530
"Aneesh Kumar K.V" wrote:
> Nicholas Piggin writes:
>
> > The SLBIA IH=1 hint will remove all non-zero SLBEs, but only
> > invalidate ERAT entries associated with a class value of 1, for
> > processors that support the hint (e.g., POWER6 and newer), which
> >
On Mon, 17 Sep 2018 11:30:16 +0530
"Aneesh Kumar K.V" wrote:
> Nicholas Piggin writes:
>
> > The POWER5 < DD2.1 issue is that slbie needs to be issued more than
> > once. It came in with this change:
> >
> > ChangeSet@1.1608, 2004-04-29 07:12:31-07:00, da...@gibson.dropbear.id.au
> > [PATCH]
Christophe Leroy writes:
> The 'access' parameter of hash_preload() is either 0 or _PAGE_EXEC.
> Among the two versions of hash_preload(), only the PPC64 one is
> doing something with this 'access' parameter.
>
> In order to remove the use of _PAGE_EXEC outside platform code,
> 'access'
The powerpc kernel uses setjmp which causes a warning when building with
clang:
CC arch/powerpc/xmon/xmon.o
In file included from arch/powerpc/xmon/xmon.c:51:
./arch/powerpc/include/asm/setjmp.h:15:13: error: declaration of
built-in function 'setjmp' requires inclusion of the
On Mon, 17 Sep 2018 16:21:51 +0930
Joel Stanley wrote:
> On Sat, 15 Sep 2018 at 01:03, Nicholas Piggin wrote:
> >
> > This causes SLB alloation to start 1 beyond the start of the SLB.
allocation
> > There is no real problem because after it wraps it stats behaving
>
> starts?
>
> >
Am 03.09.18 um 02:36 schrieb Rashmica:
> Hi David,
>
>
> On 21/08/18 20:44, David Hildenbrand wrote:
>
>> There seem to be some problems as result of 30467e0b3be ("mm, hotplug:
>> fix concurrent memory hot-add deadlock"), which tried to fix a possible
>> lock inversion reported and discussed in
Ping?
The problem is still there...
On 24/08/2018 13:04, Alexey Kardashevskiy wrote:
>
>
> On 09/08/2018 14:41, Alexey Kardashevskiy wrote:
>>
>>
>> On 25/07/2018 19:50, Alexey Kardashevskiy wrote:
>>> I am trying to pass through a 3D controller:
>>> [0302]: NVIDIA Corporation GV100GL [Tesla
On Sat, 15 Sep 2018 at 01:03, Nicholas Piggin wrote:
>
> This causes SLB alloation to start 1 beyond the start of the SLB.
> There is no real problem because after it wraps it stats behaving
starts?
> properly, it's just surprisig to see when looking at SLB traces.
surprising
>
>
Add description of DT bindings for mpc8xxx-wdt driver which
handles the CPU watchdog timer on the mpc83xx, mpc86xx and mpc8xx.
Signed-off-by: Christophe Leroy
---
.../devicetree/bindings/watchdog/mpc8xxx-wdt.txt | 25 ++
1 file changed, 25 insertions(+)
create mode 100644
mpc8xxx watchdog driver supports the following platforms:
- mpc8xx
- mpc83xx
- mpc86xx
Those three platforms have a 32 bits register which provides the
reason of the last boot, including whether it was caused by the
watchdog.
mpc8xx: Register RSR, bit SWRS (bit 3)
mpc83xx: Register RSR, bit SWRS
mpc8xxx watchdog driver is a platform device drivers, it is
therefore possible to use dev_xxx() messaging rather than pr_xxx()
Reviewed-by: Guenter Roeck
Signed-off-by: Christophe Leroy
---
drivers/watchdog/mpc8xxx_wdt.c | 24
1 file changed, 12 insertions(+), 12
Nicholas Piggin writes:
> The SLBIA IH=1 hint will remove all non-zero SLBEs, but only
> invalidate ERAT entries associated with a class value of 1, for
> processors that support the hint (e.g., POWER6 and newer), which
> Linux assigns to user addresses.
>
> This prevents kernel ERAT entries
Nicholas Piggin writes:
> The POWER5 < DD2.1 issue is that slbie needs to be issued more than
> once. It came in with this change:
>
> ChangeSet@1.1608, 2004-04-29 07:12:31-07:00, da...@gibson.dropbear.id.au
> [PATCH] POWER5 erratum workaround
>
> Early POWER5 revisions ( instructions to
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