Re: [PATCH v2] idle/x86: remove the call to boot_init_stack_canary() from cpu_startup_entry()
On 10/19/2018 03:31 AM, Christophe Leroy wrote:
> commit d7880812b359 ("idle: Add the stack canary init to
> cpu_startup_entry()") added the call to boot_init_stack_canary()
> in cpu_startup_entry() in an #ifdef CONFIG_X86 statement, with
> the intention to remove that #ifdef later.
>
> While implementing stack protector for powerpc, it has been
> observed that calling boot_init_stack_canary() is also needed
> for powerpc which uses per task (TLS) stack canary like the X86.
>
> However, calling boot_init_stack_canary() would break arches
> using global stack canary (ARM, SH, MIPS and XTENSA).
>
> Instead of modifying the #ifdef CONFIG_X86 in an
> #if defined(CONFIG_X86) || defined(CONFIG_PPC), powerpc
> implemented the call to boot_init_stack_canary() in the function
> calling cpu_startup_entry()
>
> On x86, we have two functions calling cpu_startup_entry():
> - start_secondary()
> - cpu_bringup_and_idle()
>
> start_secondary() already calls boot_init_stack_canary().
>
> This patch adds the call to boot_init_stack_canary() in
> cpu_bringup_and_idle() and removes it from cpu_startup_entry()
>
> Reviewed-by: Juergen Gross
> Signed-off-by: Christophe Leroy
> ---
> v2: Revised commit log (#if defined had been droped by 'git commit')
>
> arch/x86/xen/smp_pv.c | 1 +
> kernel/sched/idle.c | 15 ---
> 2 files changed, 1 insertion(+), 15 deletions(-)
>
> diff --git a/arch/x86/xen/smp_pv.c b/arch/x86/xen/smp_pv.c
> index e3b18ad49889..0e05e8e23998 100644
> --- a/arch/x86/xen/smp_pv.c
> +++ b/arch/x86/xen/smp_pv.c
> @@ -88,6 +88,7 @@ static void cpu_bringup(void)
> asmlinkage __visible void cpu_bringup_and_idle(void)
> {
> cpu_bringup();
> + boot_init_stack_canary();
I think I saw from the kbuild test robot in your first pass that this is an
implicit declaration. Quick look at my local git tree and I don't see an
include for stackprotector.h in this file.
-Tyrel
> cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
> }
>
> diff --git a/kernel/sched/idle.c b/kernel/sched/idle.c
> index 16f84142f2f4..f5516bae0c1b 100644
> --- a/kernel/sched/idle.c
> +++ b/kernel/sched/idle.c
> @@ -347,21 +347,6 @@ EXPORT_SYMBOL_GPL(play_idle);
>
> void cpu_startup_entry(enum cpuhp_state state)
> {
> - /*
> - * This #ifdef needs to die, but it's too late in the cycle to
> - * make this generic (ARM and SH have never invoked the canary
> - * init for the non boot CPUs!). Will be fixed in 3.11
> - */
> -#ifdef CONFIG_X86
> - /*
> - * If we're the non-boot CPU, nothing set the stack canary up
> - * for us. The boot CPU already has it initialized but no harm
> - * in doing it again. This is a good place for updating it, as
> - * we wont ever return from this function (so the invalid
> - * canaries already on the stack wont ever trigger).
> - */
> - boot_init_stack_canary();
> -#endif
> arch_cpu_idle_prepare();
> cpuhp_online_idle(state);
> while (1)
>
Re: [PATCH] idle/x86: remove the call to boot_init_stack_canary() from cpu_startup_entry()
Hi Christophe,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on xen-tip/linux-next]
[also build test ERROR on v4.19-rc8 next-20181019]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci/linux/commits/Christophe-Leroy/idle-x86-remove-the-call-to-boot_init_stack_canary-from-cpu_startup_entry/20181020-015124
base: https://git.kernel.org/pub/scm/linux/kernel/git/xen/tip.git linux-next
config: x86_64-allmodconfig (attached as .config)
compiler: gcc-7 (Debian 7.3.0-1) 7.3.0
reproduce:
# save the attached .config to linux build tree
make ARCH=x86_64
All errors (new ones prefixed by >>):
arch/x86/xen/smp_pv.c: In function 'cpu_bringup_and_idle':
>> arch/x86/xen/smp_pv.c:91:2: error: implicit declaration of function
>> 'boot_init_stack_canary'; did you mean 'snprint_stack_trace'?
>> [-Werror=implicit-function-declaration]
boot_init_stack_canary();
^~
snprint_stack_trace
cc1: some warnings being treated as errors
vim +91 arch/x86/xen/smp_pv.c
87
88 asmlinkage __visible void cpu_bringup_and_idle(void)
89 {
90 cpu_bringup();
> 91 boot_init_stack_canary();
92 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
93 }
94
---
0-DAY kernel test infrastructureOpen Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
.config.gz
Description: application/gzip
Re: [PATCH] idle/x86: remove the call to boot_init_stack_canary() from cpu_startup_entry()
Hi Christophe,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on xen-tip/linux-next]
[also build test ERROR on v4.19-rc8 next-20181019]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci/linux/commits/Christophe-Leroy/idle-x86-remove-the-call-to-boot_init_stack_canary-from-cpu_startup_entry/20181020-015124
base: https://git.kernel.org/pub/scm/linux/kernel/git/xen/tip.git linux-next
config: x86_64-randconfig-s1-10200246 (attached as .config)
compiler: gcc-6 (Debian 6.4.0-9) 6.4.0 20171026
reproduce:
# save the attached .config to linux build tree
make ARCH=x86_64
All errors (new ones prefixed by >>):
arch/x86//xen/smp_pv.c: In function 'cpu_bringup_and_idle':
>> arch/x86//xen/smp_pv.c:91:2: error: implicit declaration of function
>> 'boot_init_stack_canary' [-Werror=implicit-function-declaration]
boot_init_stack_canary();
^~
cc1: some warnings being treated as errors
vim +/boot_init_stack_canary +91 arch/x86//xen/smp_pv.c
87
88 asmlinkage __visible void cpu_bringup_and_idle(void)
89 {
90 cpu_bringup();
> 91 boot_init_stack_canary();
92 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
93 }
94
---
0-DAY kernel test infrastructureOpen Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
.config.gz
Description: application/gzip
Re: [PATCH 6/9] PCI: consolidate PCI config entry in drivers/pci
On Fri, 19 Oct 2018 05:09:49 PDT (-0700), Christoph Hellwig wrote: There is no good reason to duplicate the PCI menu in every architecture. Instead provide a selectable HAVE_PCI symbol that indicates availability of PCI support and the handle the rest in drivers/pci. Note that for powerpc we now select HAVE_PCI globally instead of the convoluted mess of conditional or or non-conditional support per board, similar to what we do e.g. on x86. For alpha PCI is selected for the non-jensen configs as it was the default before, and a lot of code does not compile without PCI enabled. On other architectures with limited PCI support that wasn't as complicated I've left the selection as-is. Signed-off-by: Christoph Hellwig Acked-by: Max Filippov Acked-by: Thomas Gleixner Acked-by: Bjorn Helgaas ... diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index a344980287a5..071952cd4cae 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -39,8 +39,10 @@ config RISCV select SPARSE_IRQ select SYSCTL_EXCEPTION_TRACE select HAVE_ARCH_TRACEHOOK + select HAVE_PCI select MODULES_USE_ELF_RELA if MODULES select THREAD_INFO_IN_TASK + select PCI_MSI if PCI select RISCV_TIMER select GENERIC_IRQ_MULTI_HANDLER select ARCH_HAS_PTE_SPECIAL @@ -216,28 +218,12 @@ source "kernel/Kconfig.hz" endmenu -menu "Bus support" - -config PCI - bool "PCI support" - select PCI_MSI - help - This feature enables support for PCI bus system. If you say Y - here, the kernel will include drivers and infrastructure code - to support PCI bus devices. - - If you don't know what to do here, say Y. - config PCI_DOMAINS def_bool PCI config PCI_DOMAINS_GENERIC def_bool PCI -source "drivers/pci/Kconfig" - -endmenu - menu "Power management options" source kernel/power/Kconfig Reviewed-by: Palmer Dabbelt I'm assuming this will go in via PCI tree of some sort, so I'm not going to touch it any further. Thanks for cleaning this up!
Re: [PATCH v4 04/18] powerpc/pseries: add of_node_put() in dlpar_detach_node()
On Thu, Oct 18, 2018 at 2:09 PM Frank Rowand wrote: > > On 10/18/18 10:09, Rob Herring wrote: > > On Mon, Oct 15, 2018 at 07:37:24PM -0700, frowand.l...@gmail.com wrote: > >> From: Frank Rowand > >> > >> "of: overlay: add missing of_node_get() in __of_attach_node_sysfs" > >> added a missing of_node_get() to __of_attach_node_sysfs(). This > >> results in a refcount imbalance for nodes attached with > >> dlpar_attach_node(). The calling sequence from dlpar_attach_node() > >> to __of_attach_node_sysfs() is: > >> > >>dlpar_attach_node() > >> of_attach_node() > >> __of_attach_node_sysfs() > > > > IIRC, there's a long standing item in the todo (Grant's) to convert the > > open coded dlpar code. Maybe you want to do that first? > > I'd like to avoid extra delays to getting the current (with necesary > fixes) series accepted because the series is rather intrusive and > could have conflicts with other patches. > > I'm also worried that I don't have access to any of the systems that > use the dynamic overlay code, and I don't have any way to test the > changes. Mainly I was thinking you are asking them to test changes now, so I was thinking better to do that once than twice. Either way is fine though. > Can we encourage the users of this code to convert the open coded > dlpar code? That would be ideal... Rob
Re: [RFC PATCH] mm: add probe_user_read() and probe_user_address()
On Fri, Oct 19, 2018 at 8:14 AM, Christophe Leroy
wrote:
> In the powerpc, there are several places implementing safe
> access to user data. This is sometimes implemented using
> probe_kerne_address() with additional access_ok() verification,
> sometimes with get_user() enclosed in a pagefault_disable()/enable()
> pair, etc... :
> show_user_instructions()
> bad_stack_expansion()
> p9_hmi_special_emu()
> fsl_pci_mcheck_exception()
> read_user_stack_64()
> read_user_stack_32() on PPC64
> read_user_stack_32() on PPC32
> power_pmu_bhrb_to()
>
> In the same spirit as probe_kernel_read() and probe_kernel_address(),
> this patch adds probe_user_read() and probe_user_address().
>
> probe_user_read() does the same as probe_kernel_read() but
> first checks that it is really a user address.
>
> probe_user_address() is a shortcut to probe_user_read()
>
> Signed-off-by: Christophe Leroy
> ---
> include/linux/uaccess.h | 10 ++
> mm/maccess.c| 33 +
> 2 files changed, 43 insertions(+)
>
> diff --git a/include/linux/uaccess.h b/include/linux/uaccess.h
> index efe79c1cdd47..fb00e3f847d7 100644
> --- a/include/linux/uaccess.h
> +++ b/include/linux/uaccess.h
> @@ -266,6 +266,16 @@ extern long strncpy_from_unsafe(char *dst, const void
> *unsafe_addr, long count);
> #define probe_kernel_address(addr, retval) \
> probe_kernel_read(, addr, sizeof(retval))
>
> +/**
> + * probe_user_address(): safely attempt to read from a user location
> + * @addr: address to read from
> + * @retval: read into this variable
> + *
> + * Returns 0 on success, or -EFAULT.
> + */
> +#define probe_user_address(addr, retval) \
> + probe_user_read(&(retval), addr, sizeof(retval))
> +
> #ifndef user_access_begin
> #define user_access_begin() do { } while (0)
> #define user_access_end() do { } while (0)
> diff --git a/mm/maccess.c b/mm/maccess.c
> index ec00be51a24f..85d4a88a6917 100644
> --- a/mm/maccess.c
> +++ b/mm/maccess.c
> @@ -67,6 +67,39 @@ long __probe_kernel_write(void *dst, const void *src,
> size_t size)
> EXPORT_SYMBOL_GPL(probe_kernel_write);
>
> /**
> + * probe_user_read(): safely attempt to read from a user location
> + * @dst: pointer to the buffer that shall take the data
> + * @src: address to read from
> + * @size: size of the data chunk
> + *
> + * Safely read from address @src to the buffer at @dst. If a kernel fault
> + * happens, handle that and return -EFAULT.
> + *
> + * We ensure that the copy_from_user is executed in atomic context so that
> + * do_page_fault() doesn't attempt to take mmap_sem. This makes
> + * probe_user_read() suitable for use within regions where the caller
> + * already holds mmap_sem, or other locks which nest inside mmap_sem.
> + */
> +
> +long __weak probe_user_read(void *dst, const void *src, size_t size)
> + __attribute__((alias("__probe_user_read")));
Let's use #defines to deal with per-arch aliases so we can keep the
inline I'm suggesting below...
> +
> +long __probe_user_read(void *dst, const void __user *src, size_t size)
Please make this __always_inline so the "size" variable can be
examined for const-ness by the check_object_size() in
__copy_from_user_inatomic().
-Kees
--
Kees Cook
Pixel Security
Re: [PATCH 5/9] powerpc: PCI_MSI needs PCI
On Fri, Oct 19, 2018 at 02:09:48PM +0200, Christoph Hellwig wrote: > Various powerpc boards select the PCI_MSI config option without selecting > PCI, resulting in potentially not compilable configurations if the by > default enabled PCI option is disabled. Explicitly select PCI to ensure > we always have valid configs. [...] > --- a/arch/powerpc/platforms/44x/Kconfig > +++ b/arch/powerpc/platforms/44x/Kconfig > @@ -24,6 +24,7 @@ config BLUESTONE > default n > select PPC44x_SIMPLE > select APM821xx > + select PCI > select PCI_MSI > select PPC4xx_MSI > select PPC4xx_PCI_EXPRESS > @@ -78,6 +79,7 @@ config KATMAI > select 440SPe > select PCI > select PPC4xx_PCI_EXPRESS > + select PCI > select PCI_MSI This case already had PCI selected a couple of lines above. > select PPC4xx_MSI > help > @@ -219,6 +221,7 @@ config AKEBONO > select SWIOTLB > select 476FPE > select PPC4xx_PCI_EXPRESS > + select PCI > select PCI_MSI > select PPC4xx_HSTA_MSI > select I2C > -- > 2.19.1 >
[RFC PATCH] mm: add probe_user_read() and probe_user_address()
In the powerpc, there are several places implementing safe
access to user data. This is sometimes implemented using
probe_kerne_address() with additional access_ok() verification,
sometimes with get_user() enclosed in a pagefault_disable()/enable()
pair, etc... :
show_user_instructions()
bad_stack_expansion()
p9_hmi_special_emu()
fsl_pci_mcheck_exception()
read_user_stack_64()
read_user_stack_32() on PPC64
read_user_stack_32() on PPC32
power_pmu_bhrb_to()
In the same spirit as probe_kernel_read() and probe_kernel_address(),
this patch adds probe_user_read() and probe_user_address().
probe_user_read() does the same as probe_kernel_read() but
first checks that it is really a user address.
probe_user_address() is a shortcut to probe_user_read()
Signed-off-by: Christophe Leroy
---
include/linux/uaccess.h | 10 ++
mm/maccess.c| 33 +
2 files changed, 43 insertions(+)
diff --git a/include/linux/uaccess.h b/include/linux/uaccess.h
index efe79c1cdd47..fb00e3f847d7 100644
--- a/include/linux/uaccess.h
+++ b/include/linux/uaccess.h
@@ -266,6 +266,16 @@ extern long strncpy_from_unsafe(char *dst, const void
*unsafe_addr, long count);
#define probe_kernel_address(addr, retval) \
probe_kernel_read(, addr, sizeof(retval))
+/**
+ * probe_user_address(): safely attempt to read from a user location
+ * @addr: address to read from
+ * @retval: read into this variable
+ *
+ * Returns 0 on success, or -EFAULT.
+ */
+#define probe_user_address(addr, retval) \
+ probe_user_read(&(retval), addr, sizeof(retval))
+
#ifndef user_access_begin
#define user_access_begin() do { } while (0)
#define user_access_end() do { } while (0)
diff --git a/mm/maccess.c b/mm/maccess.c
index ec00be51a24f..85d4a88a6917 100644
--- a/mm/maccess.c
+++ b/mm/maccess.c
@@ -67,6 +67,39 @@ long __probe_kernel_write(void *dst, const void *src, size_t
size)
EXPORT_SYMBOL_GPL(probe_kernel_write);
/**
+ * probe_user_read(): safely attempt to read from a user location
+ * @dst: pointer to the buffer that shall take the data
+ * @src: address to read from
+ * @size: size of the data chunk
+ *
+ * Safely read from address @src to the buffer at @dst. If a kernel fault
+ * happens, handle that and return -EFAULT.
+ *
+ * We ensure that the copy_from_user is executed in atomic context so that
+ * do_page_fault() doesn't attempt to take mmap_sem. This makes
+ * probe_user_read() suitable for use within regions where the caller
+ * already holds mmap_sem, or other locks which nest inside mmap_sem.
+ */
+
+long __weak probe_user_read(void *dst, const void *src, size_t size)
+ __attribute__((alias("__probe_user_read")));
+
+long __probe_user_read(void *dst, const void __user *src, size_t size)
+{
+ long ret;
+
+ if (!access_ok(VERIFY_READ, src, size))
+ return -EFAULT;
+
+ pagefault_disable();
+ ret = __copy_from_user_inatomic(dst, src, size);
+ pagefault_enable();
+
+ return ret ? -EFAULT : 0;
+}
+EXPORT_SYMBOL_GPL(probe_user_read);
+
+/**
* strncpy_from_unsafe: - Copy a NUL terminated string from unsafe address.
* @dst: Destination address, in kernel space. This buffer must be at
* least @count bytes long.
--
2.13.3
Re: [PATCH 6/9] PCI: consolidate PCI config entry in drivers/pci
On Fri, Oct 19, 2018 at 9:23 PM Russell King - ARM Linux wrote: > > index a68b34183107..b185794549be 100644 > > --- a/arch/arm/mach-pxa/Kconfig > > +++ b/arch/arm/mach-pxa/Kconfig > > @@ -125,7 +125,7 @@ config MACH_ARMCORE > > bool "CompuLab CM-X255/CM-X270 modules" > > select ARCH_HAS_DMA_SET_COHERENT_MASK if PCI > > select IWMMXT > > - select MIGHT_HAVE_PCI > > + select HAVE_PCI > > select NEED_MACH_IO_H if PCI > > select PXA25x > > select PXA27x > > This is wrong. "MIGHT_HAVE_PCI" is _not_ the same as "HAVE_PCI" - we > have a bunch of platforms that mandatorily have PCI and these select > PCI directly. "MIGHT_HAVE_PCI" controls the _visibility_ of the PCI > menu option, but does not prevent it being selected. Your patch will > cause Kconfig to complain for those which mandatorily have PCI but > do not set HAVE_PCI. Good catch! But, adding a bunch of 'select HAVE_PCI' along with 'select PCI' is ugly. Do you have any suggestion? How about letting CONFIG_ARM to select HAVE_PCI ? -- Best Regards Masahiro Yamada
Re: [PATCH 2/9] arm: remove EISA kconfig option
On Fri, Oct 19, 2018 at 9:10 PM Christoph Hellwig wrote: > > No arm config enables EISA, and arm does not include drivers/eisa/Kconfig > which provides support for things like PCI to EISA bridges, so it is most > likely dead. > > If this is wrong we will be able to resurrect it easily by selecting > HAVE_EISA for the right arm configs after this series. What is your concern? This absolutely looks dead to me. > Suggested-by: Masahiro Yamada > Signed-off-by: Christoph Hellwig > --- > arch/arm/Kconfig | 15 --- > 1 file changed, 15 deletions(-) > > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig > index e8cd55a5b04c..e33735ce1c14 100644 > --- a/arch/arm/Kconfig > +++ b/arch/arm/Kconfig > @@ -165,21 +165,6 @@ config HAVE_PROC_CPU > config NO_IOPORT_MAP > bool > > -config EISA > - bool There is no prompt for this symbol. Hence, there is no way for a user to enable this directly. 'select EISA' is the only way to enable it. git grep 'select EISA' gave no hit. So, we can say it is dead. > - ---help--- > - The Extended Industry Standard Architecture (EISA) bus was > - developed as an open alternative to the IBM MicroChannel bus. > - > - The EISA bus provided some of the features of the IBM MicroChannel > - bus while maintaining backward compatibility with cards made for > - the older ISA bus. The EISA bus saw limited use between 1988 and > - 1995 when it was made obsolete by the PCI bus. > - > - Say Y here if you are building a kernel for an EISA-based machine. > - > - Otherwise, say N. > - > config SBUS > bool I guess the situation is the same as powerpc. The difference between arm and powerpc is the presence of help. You fold the powerpc change in 9/9. -- Best Regards Masahiro Yamada
Re: [PATCH 6/9] PCI: consolidate PCI config entry in drivers/pci
On Fri, Oct 19, 2018 at 02:09:49PM +0200, Christoph Hellwig wrote: > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig > index e33735ce1c14..7495d0a0aa31 100644 > --- a/arch/arm/Kconfig > +++ b/arch/arm/Kconfig > @@ -149,9 +149,6 @@ config ARM_DMA_IOMMU_ALIGNMENT > > endif > > -config MIGHT_HAVE_PCI > - bool > - > config SYS_SUPPORTS_APM_EMULATION > bool > > @@ -320,7 +317,7 @@ config ARCH_MULTIPLATFORM > select COMMON_CLK > select GENERIC_CLOCKEVENTS > select GENERIC_IRQ_MULTI_HANDLER > - select MIGHT_HAVE_PCI > + select HAVE_PCI > select PCI_DOMAINS if PCI > select SPARSE_IRQ > select USE_OF > @@ -436,7 +433,7 @@ config ARCH_IXP4XX > select DMABOUNCE if PCI > select GENERIC_CLOCKEVENTS > select GPIOLIB > - select MIGHT_HAVE_PCI > + select HAVE_PCI > select NEED_MACH_IO_H > select USB_EHCI_BIG_ENDIAN_DESC > select USB_EHCI_BIG_ENDIAN_MMIO > @@ -449,7 +446,7 @@ config ARCH_DOVE > select GENERIC_CLOCKEVENTS > select GENERIC_IRQ_MULTI_HANDLER > select GPIOLIB > - select MIGHT_HAVE_PCI > + select HAVE_PCI > select MVEBU_MBUS > select PINCTRL > select PINCTRL_DOVE > @@ -1216,14 +1213,6 @@ config ISA_DMA > config ISA_DMA_API > bool > > -config PCI > - bool "PCI support" if MIGHT_HAVE_PCI > - help > - Find out whether you have a PCI motherboard. PCI is the name of a > - bus system, i.e. the way the CPU talks to the other stuff inside > - your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or > - VESA. If you have PCI, say Y, otherwise N. > - > config PCI_DOMAINS > bool "Support for multiple PCI domains" > depends on PCI > @@ -1252,8 +1241,6 @@ config PCI_HOST_ITE8152 > default y > select DMABOUNCE > > -source "drivers/pci/Kconfig" > - > source "drivers/pcmcia/Kconfig" > > endmenu > diff --git a/arch/arm/mach-ks8695/Kconfig b/arch/arm/mach-ks8695/Kconfig > index a545976bdbd6..b3185c05fffa 100644 > --- a/arch/arm/mach-ks8695/Kconfig > +++ b/arch/arm/mach-ks8695/Kconfig > @@ -4,7 +4,7 @@ menu "Kendin/Micrel KS8695 Implementations" > > config MACH_KS8695 > bool "KS8695 development board" > - select MIGHT_HAVE_PCI > + select HAVE_PCI > help > Say 'Y' here if you want your kernel to run on the original > Kendin-Micrel KS8695 development board. > @@ -52,7 +52,7 @@ config MACH_CM4002 > > config MACH_CM4008 > bool "OpenGear CM4008" > - select MIGHT_HAVE_PCI > + select HAVE_PCI > help > Say 'Y' here if you want your kernel to support the OpenGear > CM4008 Console Server. See http://www.opengear.com for more > @@ -60,7 +60,7 @@ config MACH_CM4008 > > config MACH_CM41xx > bool "OpenGear CM41xx" > - select MIGHT_HAVE_PCI > + select HAVE_PCI > help > Say 'Y' here if you want your kernel to support the OpenGear > CM4016 or CM4048 Console Servers. See http://www.opengear.com for > @@ -68,7 +68,7 @@ config MACH_CM41xx > > config MACH_IM4004 > bool "OpenGear IM4004" > - select MIGHT_HAVE_PCI > + select HAVE_PCI > help > Say 'Y' here if you want your kernel to support the OpenGear > IM4004 Secure Access Server. See http://www.opengear.com for > @@ -76,7 +76,7 @@ config MACH_IM4004 > > config MACH_IM42xx > bool "OpenGear IM42xx" > - select MIGHT_HAVE_PCI > + select HAVE_PCI > help > Say 'Y' here if you want your kernel to support the OpenGear > IM4216 or IM4248 Console Servers. See http://www.opengear.com for > diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig > index a68b34183107..b185794549be 100644 > --- a/arch/arm/mach-pxa/Kconfig > +++ b/arch/arm/mach-pxa/Kconfig > @@ -125,7 +125,7 @@ config MACH_ARMCORE > bool "CompuLab CM-X255/CM-X270 modules" > select ARCH_HAS_DMA_SET_COHERENT_MASK if PCI > select IWMMXT > - select MIGHT_HAVE_PCI > + select HAVE_PCI > select NEED_MACH_IO_H if PCI > select PXA25x > select PXA27x This is wrong. "MIGHT_HAVE_PCI" is _not_ the same as "HAVE_PCI" - we have a bunch of platforms that mandatorily have PCI and these select PCI directly. "MIGHT_HAVE_PCI" controls the _visibility_ of the PCI menu option, but does not prevent it being selected. Your patch will cause Kconfig to complain for those which mandatorily have PCI but do not set HAVE_PCI. -- RMK's Patch system: http://www.armlinux.org.uk/developer/patches/ FTTC broadband for 0.8mile line in suburbia: sync at 12.1Mbps down 622kbps up According to speedtest.net: 11.9Mbps down 500kbps up
[PATCH 9/9] eisa: consolidate EISA Kconfig entry in drivers/eisa
Let architectures opt into EISA support by selecting HAS_EISA and handle everything else in drivers/eisa. Signed-off-by: Christoph Hellwig Acked-by: Thomas Gleixner --- arch/alpha/Kconfig | 15 --- arch/mips/Kconfig | 31 +-- arch/powerpc/Kconfig | 3 --- arch/x86/Kconfig | 19 +-- drivers/Kconfig| 1 + drivers/eisa/Kconfig | 21 - drivers/parisc/Kconfig | 11 +-- 7 files changed, 36 insertions(+), 65 deletions(-) diff --git a/arch/alpha/Kconfig b/arch/alpha/Kconfig index 96f02268ea16..b723cd8ee6fb 100644 --- a/arch/alpha/Kconfig +++ b/arch/alpha/Kconfig @@ -128,11 +128,13 @@ choice config ALPHA_GENERIC bool "Generic" depends on TTY + select HAVE_EISA help A generic kernel will run on all supported Alpha hardware. config ALPHA_ALCOR bool "Alcor/Alpha-XLT" + select HAVE_EISA help For systems using the Digital ALCOR chipset: 5 chips (4, 64-bit data slices (Data Switch, DSW) - 208-pin PQFP and 1 control (Control, I/O @@ -206,6 +208,7 @@ config ALPHA_JENSEN bool "Jensen" depends on BROKEN select DMA_DIRECT_OPS + select HAVE_EISA help DEC PC 150 AXP (aka Jensen): This is a very old Digital system - one of the first-generation Alpha systems. A number of these systems @@ -222,6 +225,7 @@ config ALPHA_LX164 config ALPHA_LYNX bool "Lynx" + select HAVE_EISA help AlphaServer 2100A-based systems. @@ -232,6 +236,7 @@ config ALPHA_MARVEL config ALPHA_MIATA bool "Miata" + select HAVE_EISA help The Digital PersonalWorkStation (PWS 433a, 433au, 500a, 500au, 600a, or 600au). @@ -251,6 +256,7 @@ config ALPHA_NONAME_CH config ALPHA_NORITAKE bool "Noritake" + select HAVE_EISA help AlphaServer 1000A, AlphaServer 600A, and AlphaServer 800-based systems. @@ -263,6 +269,7 @@ config ALPHA_P2K config ALPHA_RAWHIDE bool "Rawhide" + select HAVE_EISA help AlphaServer 1200, AlphaServer 4000 and AlphaServer 4100 machines. See HOWTO at @@ -282,6 +289,7 @@ config ALPHA_SX164 config ALPHA_SABLE bool "Sable" + select HAVE_EISA help Digital AlphaServer 2000 and 2100-based systems. @@ -518,11 +526,6 @@ config ALPHA_SRM If unsure, say N. -config EISA - bool - depends on ALPHA_GENERIC || ALPHA_JENSEN || ALPHA_ALCOR || ALPHA_MIKASA || ALPHA_SABLE || ALPHA_LYNX || ALPHA_NORITAKE || ALPHA_RAWHIDE - default y - config ARCH_MAY_HAVE_PC_FDC def_bool y @@ -673,8 +676,6 @@ config HZ default 1200 if HZ_1200 default 1024 -source "drivers/eisa/Kconfig" - config SRM_ENV tristate "SRM environment through procfs" depends on PROC_FS diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 96198f8375e1..7cf58031a43e 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -23,6 +23,7 @@ config MIPS select GENERIC_CPU_AUTOPROBE select GENERIC_IRQ_PROBE select GENERIC_IRQ_SHOW + select GENERIC_ISA_DMA if EISA select GENERIC_LIB_ASHLDI3 select GENERIC_LIB_ASHRDI3 select GENERIC_LIB_CMPDI2 @@ -72,6 +73,7 @@ config MIPS select HAVE_SYSCALL_TRACEPOINTS select HAVE_VIRT_CPU_ACCOUNTING_GEN if 64BIT || !SMP select IRQ_FORCED_THREADING + select ISA if EISA select MODULES_USE_ELF_RELA if MODULES && 64BIT select MODULES_USE_ELF_REL if MODULES select PCI_DOMAINS if PCI @@ -634,7 +636,7 @@ config SGI_IP22 select CSRC_R4K select DEFAULT_SGI_PARTITION select DMA_NONCOHERENT - select HW_HAS_EISA + select HAVE_EISA select I8253 select I8259 select IP22_CPU_SCACHE @@ -699,7 +701,7 @@ config SGI_IP28 select DMA_NONCOHERENT select GENERIC_ISA_DMA_SUPPORT_BROKEN select IRQ_MIPS_CPU - select HW_HAS_EISA + select HAVE_EISA select I8253 select I8259 select SGI_HAS_I8042 @@ -842,8 +844,8 @@ config SNI_RM select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN select DMA_NONCOHERENT select GENERIC_ISA_DMA + select HAVE_EISA select HAVE_PCSPKR_PLATFORM - select HW_HAS_EISA select HAVE_PCI select IRQ_MIPS_CPU select I8253 @@ -2991,9 +2993,6 @@ config MIPS_AUTO_PFN_OFFSET menu "Bus options (PCI, PCMCIA, EISA, ISA, TC)" -config HW_HAS_EISA - bool - config HT_PCI bool "Support for HT-linked PCI" default y @@ -3027,26 +3026,6 @@ config PCI_DRIVERS_LEGACY config ISA bool -config EISA - bool "EISA support" - depends on HW_HAS_EISA - select ISA - select GENERIC_ISA_DMA - ---help--- - The Extended
[PATCH 8/9] rapidio: consolidate RAPIDIO config entry in drivers/rapidio
There is no good reason to duplicate the RAPIDIO menu in various architectures. Instead provide a selectable HAVE_RAPIDIO symbol that indicates native availability of RAPIDIO support and the handle the rest in drivers/pci. This also means we now provide support for PCI(e) to Rapidio bridges for every architecture instead of a limited subset. Signed-off-by: Christoph Hellwig Acked-by: Thomas Gleixner --- arch/mips/Kconfig | 15 +-- arch/powerpc/Kconfig| 15 +-- arch/powerpc/platforms/85xx/Kconfig | 8 arch/powerpc/platforms/86xx/Kconfig | 4 ++-- arch/x86/Kconfig| 10 -- drivers/Kconfig | 1 + drivers/rapidio/Kconfig | 11 +++ 7 files changed, 20 insertions(+), 44 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 18eeb66c6d99..96198f8375e1 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -894,7 +894,7 @@ config CAVIUM_OCTEON_SOC bool "Cavium Networks Octeon SoC based boards" select CEVT_R4K select ARCH_HAS_PHYS_TO_DMA - select HAS_RAPIDIO + select HAVE_RAPIDIO select PHYS_ADDR_T_64BIT select SYS_SUPPORTS_64BIT_KERNEL select SYS_SUPPORTS_BIG_ENDIAN @@ -3090,19 +3090,6 @@ config ZONE_DMA config ZONE_DMA32 bool -config HAS_RAPIDIO - bool - default n - -config RAPIDIO - tristate "RapidIO support" - depends on HAS_RAPIDIO || PCI - help - If you say Y here, the kernel will include drivers and - infrastructure code to support RapidIO interconnect devices. - -source "drivers/rapidio/Kconfig" - endmenu config TRAD_SIGNALS diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig index ffd1695ad9b4..6b29c27770db 100644 --- a/arch/powerpc/Kconfig +++ b/arch/powerpc/Kconfig @@ -959,27 +959,14 @@ config PCI_8260 select PPC_INDIRECT_PCI default y -config HAS_RAPIDIO - bool - default n - -config RAPIDIO - tristate "RapidIO support" - depends on HAS_RAPIDIO || PCI - help - If you say Y here, the kernel will include drivers and - infrastructure code to support RapidIO interconnect devices. - config FSL_RIO bool "Freescale Embedded SRIO Controller support" - depends on RAPIDIO = y && HAS_RAPIDIO + depends on RAPIDIO = y && HAVE_RAPIDIO default "n" ---help--- Include support for RapidIO controller on Freescale embedded processors (MPC8548, MPC8641, etc). -source "drivers/rapidio/Kconfig" - endmenu config NONSTATIC_KERNEL diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/platforms/85xx/Kconfig index 20867a23f3f2..1c6bb9180d70 100644 --- a/arch/powerpc/platforms/85xx/Kconfig +++ b/arch/powerpc/platforms/85xx/Kconfig @@ -65,7 +65,7 @@ config MPC85xx_CDS bool "Freescale MPC85xx CDS" select DEFAULT_UIMAGE select PPC_I8259 - select HAS_RAPIDIO + select HAVE_RAPIDIO help This option enables support for the MPC85xx CDS board @@ -73,7 +73,7 @@ config MPC85xx_MDS bool "Freescale MPC85xx MDS" select DEFAULT_UIMAGE select PHYLIB if NETDEVICES - select HAS_RAPIDIO + select HAVE_RAPIDIO select SWIOTLB help This option enables support for the MPC85xx MDS board @@ -218,7 +218,7 @@ config PPA8548 help This option enables support for the Prodrive PPA8548 board. select DEFAULT_UIMAGE - select HAS_RAPIDIO + select HAVE_RAPIDIO config GE_IMP3A bool "GE Intelligent Platforms IMP3A" @@ -276,7 +276,7 @@ config CORENET_GENERIC select SWIOTLB select GPIOLIB select GPIO_MPC8XXX - select HAS_RAPIDIO + select HAVE_RAPIDIO select PPC_EPAPR_HV_PIC help This option enables support for the FSL CoreNet based boards. diff --git a/arch/powerpc/platforms/86xx/Kconfig b/arch/powerpc/platforms/86xx/Kconfig index 87220554dd6f..badd9d6ba1ef 100644 --- a/arch/powerpc/platforms/86xx/Kconfig +++ b/arch/powerpc/platforms/86xx/Kconfig @@ -15,7 +15,7 @@ config MPC8641_HPCN select PPC_I8259 select DEFAULT_UIMAGE select FSL_ULI1575 if PCI - select HAS_RAPIDIO + select HAVE_RAPIDIO select SWIOTLB help This option enables support for the MPC8641 HPCN board. @@ -57,7 +57,7 @@ config GEF_SBC610 select MMIO_NVRAM select GPIOLIB select GE_FPGA - select HAS_RAPIDIO + select HAVE_RAPIDIO help This option enables support for the GE SBC610. diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index fda01408b596..6fe3740018f6 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -2810,16 +2810,6 @@ config AMD_NB def_bool y depends on CPU_SUP_AMD && PCI -config RAPIDIO - tristate "RapidIO
[PATCH 7/9] pcmcia: allow PCMCIA support independent of the architecture
There is nothing architecture specific in the PCMCIA core, so allow building it everywhere. The actual host controllers will depend on ISA, PCI or a specific SOC. Signed-off-by: Christoph Hellwig Acked-by: Dominik Brodowski Acked-by: Thomas Gleixner --- arch/alpha/Kconfig | 2 -- arch/arm/Kconfig | 2 -- arch/ia64/Kconfig | 2 -- arch/m68k/Kconfig.bus | 2 -- arch/mips/Kconfig | 2 -- arch/powerpc/Kconfig | 2 -- arch/sh/Kconfig| 2 -- arch/sparc/Kconfig | 2 -- arch/unicore32/Kconfig | 6 -- arch/x86/Kconfig | 2 -- arch/xtensa/Kconfig| 2 -- drivers/Kconfig| 1 + drivers/parisc/Kconfig | 2 -- drivers/pcmcia/Kconfig | 1 + 14 files changed, 2 insertions(+), 28 deletions(-) diff --git a/arch/alpha/Kconfig b/arch/alpha/Kconfig index bb89924c0361..96f02268ea16 100644 --- a/arch/alpha/Kconfig +++ b/arch/alpha/Kconfig @@ -675,8 +675,6 @@ config HZ source "drivers/eisa/Kconfig" -source "drivers/pcmcia/Kconfig" - config SRM_ENV tristate "SRM environment through procfs" depends on PROC_FS diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 7495d0a0aa31..ec602deaab43 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1241,8 +1241,6 @@ config PCI_HOST_ITE8152 default y select DMABOUNCE -source "drivers/pcmcia/Kconfig" - endmenu menu "Kernel Features" diff --git a/arch/ia64/Kconfig b/arch/ia64/Kconfig index 89da763d7c17..704ff5922ce0 100644 --- a/arch/ia64/Kconfig +++ b/arch/ia64/Kconfig @@ -553,8 +553,6 @@ config PCI_DOMAINS config PCI_SYSCALL def_bool PCI -source "drivers/pcmcia/Kconfig" - endmenu endif diff --git a/arch/m68k/Kconfig.bus b/arch/m68k/Kconfig.bus index 8cb0604b195b..9d0a3a23d50e 100644 --- a/arch/m68k/Kconfig.bus +++ b/arch/m68k/Kconfig.bus @@ -68,6 +68,4 @@ if !MMU config ISA_DMA_API def_bool !M5272 -source "drivers/pcmcia/Kconfig" - endif diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 09b93d5a55cb..18eeb66c6d99 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -3090,8 +3090,6 @@ config ZONE_DMA config ZONE_DMA32 bool -source "drivers/pcmcia/Kconfig" - config HAS_RAPIDIO bool default n diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig index 086d78c7c2c8..ffd1695ad9b4 100644 --- a/arch/powerpc/Kconfig +++ b/arch/powerpc/Kconfig @@ -959,8 +959,6 @@ config PCI_8260 select PPC_INDIRECT_PCI default y -source "drivers/pcmcia/Kconfig" - config HAS_RAPIDIO bool default n diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig index 2ff6855811a5..ce9487139155 100644 --- a/arch/sh/Kconfig +++ b/arch/sh/Kconfig @@ -861,8 +861,6 @@ config MAPLE config PCI_DOMAINS bool -source "drivers/pcmcia/Kconfig" - endmenu menu "Power management options (EXPERIMENTAL)" diff --git a/arch/sparc/Kconfig b/arch/sparc/Kconfig index fc311b8dc46b..0198f96528fc 100644 --- a/arch/sparc/Kconfig +++ b/arch/sparc/Kconfig @@ -509,8 +509,6 @@ config SPARC_GRPCI2 help Say Y here to include the GRPCI2 Host Bridge Driver. -source "drivers/pcmcia/Kconfig" - config SUN_OPENPROMFS tristate "Openprom tree appears in /proc/openprom" help diff --git a/arch/unicore32/Kconfig b/arch/unicore32/Kconfig index 601dcad2560e..d7750e7c7ccb 100644 --- a/arch/unicore32/Kconfig +++ b/arch/unicore32/Kconfig @@ -118,12 +118,6 @@ config UNICORE_FPU_F64 endmenu -menu "Bus support" - -source "drivers/pcmcia/Kconfig" - -endmenu - menu "Kernel Features" source "kernel/Kconfig.hz" diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 5816e20a3ff9..fda01408b596 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -2810,8 +2810,6 @@ config AMD_NB def_bool y depends on CPU_SUP_AMD && PCI -source "drivers/pcmcia/Kconfig" - config RAPIDIO tristate "RapidIO support" depends on PCI diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig index f057c16a48a5..c18ceaab7860 100644 --- a/arch/xtensa/Kconfig +++ b/arch/xtensa/Kconfig @@ -517,8 +517,6 @@ config FORCE_MAX_ZONEORDER This config option is actually maximum order plus one. For example, a value of 11 means that the largest free memory block is 2^10 pages. -source "drivers/pcmcia/Kconfig" - config PLATFORM_WANT_DEFAULT_MEM def_bool n diff --git a/drivers/Kconfig b/drivers/Kconfig index 059573823387..58ee88c36cf5 100644 --- a/drivers/Kconfig +++ b/drivers/Kconfig @@ -5,6 +5,7 @@ menu "Device Drivers" source "drivers/amba/Kconfig" source "drivers/pci/Kconfig" +source "drivers/pcmcia/Kconfig" source "drivers/base/Kconfig" diff --git a/drivers/parisc/Kconfig b/drivers/parisc/Kconfig index 5bbfea1a019c..1a55763d1245 100644 --- a/drivers/parisc/Kconfig +++ b/drivers/parisc/Kconfig @@ -92,8 +92,6 @@ config IOMMU_SBA depends on PCI_LBA default PCI_LBA -source "drivers/pcmcia/Kconfig" - endmenu menu "PA-RISC specific drivers" diff --git
[PATCH 6/9] PCI: consolidate PCI config entry in drivers/pci
There is no good reason to duplicate the PCI menu in every architecture. Instead provide a selectable HAVE_PCI symbol that indicates availability of PCI support and the handle the rest in drivers/pci. Note that for powerpc we now select HAVE_PCI globally instead of the convoluted mess of conditional or or non-conditional support per board, similar to what we do e.g. on x86. For alpha PCI is selected for the non-jensen configs as it was the default before, and a lot of code does not compile without PCI enabled. On other architectures with limited PCI support that wasn't as complicated I've left the selection as-is. Signed-off-by: Christoph Hellwig Acked-by: Max Filippov Acked-by: Thomas Gleixner Acked-by: Bjorn Helgaas --- arch/alpha/Kconfig | 15 ++--- arch/arc/Kconfig | 20 arch/arc/plat-axs10x/Kconfig | 2 +- arch/arc/plat-hsdk/Kconfig | 2 +- arch/arm/Kconfig | 19 ++-- arch/arm/mach-ks8695/Kconfig | 10 +++--- arch/arm/mach-pxa/Kconfig | 2 +- arch/arm64/Kconfig | 10 +- arch/hexagon/Kconfig | 3 -- arch/ia64/Kconfig | 9 +- arch/m68k/Kconfig.bus | 11 --- arch/m68k/Kconfig.cpu | 1 + arch/microblaze/Kconfig| 6 +--- arch/mips/Kconfig | 43 +- arch/mips/alchemy/Kconfig | 6 ++-- arch/mips/ath25/Kconfig| 2 +- arch/mips/ath79/Kconfig| 8 ++--- arch/mips/bcm63xx/Kconfig | 14 - arch/mips/lantiq/Kconfig | 2 +- arch/mips/loongson64/Kconfig | 6 ++-- arch/mips/pmcs-msp71xx/Kconfig | 10 +++--- arch/mips/ralink/Kconfig | 8 ++--- arch/mips/sibyte/Kconfig | 10 +++--- arch/mips/txx9/Kconfig | 8 ++--- arch/mips/vr41xx/Kconfig | 8 ++--- arch/parisc/Kconfig| 1 + arch/powerpc/Kconfig | 25 --- arch/powerpc/platforms/44x/Kconfig | 1 - arch/powerpc/platforms/512x/Kconfig| 1 - arch/powerpc/platforms/52xx/Kconfig| 1 - arch/powerpc/platforms/83xx/Kconfig| 1 - arch/powerpc/platforms/85xx/Kconfig| 1 - arch/powerpc/platforms/86xx/Kconfig| 2 -- arch/powerpc/platforms/Kconfig | 1 - arch/powerpc/platforms/Kconfig.cputype | 2 -- arch/powerpc/platforms/ps3/Kconfig | 1 - arch/riscv/Kconfig | 18 ++- arch/s390/Kconfig | 23 +- arch/sh/Kconfig| 19 ++-- arch/sh/boards/Kconfig | 30 +- arch/sparc/Kconfig | 15 + arch/um/Kconfig| 3 -- arch/unicore32/Kconfig | 11 +-- arch/x86/Kconfig | 12 +-- arch/x86/configs/i386_defconfig| 1 + arch/x86/configs/x86_64_defconfig | 1 + arch/xtensa/Kconfig| 16 +- arch/xtensa/configs/common_defconfig | 1 + arch/xtensa/configs/iss_defconfig | 1 - drivers/Kconfig| 4 +++ drivers/parisc/Kconfig | 11 --- drivers/pci/Kconfig| 12 +++ drivers/pci/endpoint/Kconfig | 2 +- 53 files changed, 133 insertions(+), 319 deletions(-) diff --git a/arch/alpha/Kconfig b/arch/alpha/Kconfig index 5b4f88363453..bb89924c0361 100644 --- a/arch/alpha/Kconfig +++ b/arch/alpha/Kconfig @@ -6,6 +6,8 @@ config ALPHA select ARCH_MIGHT_HAVE_PC_SERIO select ARCH_NO_PREEMPT select ARCH_USE_CMPXCHG_LOCKREF + select HAVE_PCI if !ALPHA_JENSEN + select PCI if !ALPHA_JENSEN select HAVE_AOUT select HAVE_IDE select HAVE_OPROFILE @@ -15,6 +17,7 @@ config ALPHA select NEED_SG_DMA_LENGTH select VIRT_TO_BUS select GENERIC_IRQ_PROBE + select GENERIC_PCI_IOMAP if PCI select AUTO_IRQ_AFFINITY if SMP select GENERIC_IRQ_SHOW select ARCH_WANT_IPC_PARSE_VERSION @@ -319,17 +322,6 @@ config ISA_DMA_API bool default y -config PCI - bool - depends on !ALPHA_JENSEN - select GENERIC_PCI_IOMAP - default y - help - Find out whether you have a PCI motherboard. PCI is the name of a - bus system, i.e. the way the CPU talks to the other stuff inside - your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or - VESA. If you have PCI, say Y, otherwise N. - config PCI_DOMAINS bool default y @@ -681,7 +673,6 @@ config HZ default 1200 if HZ_1200 default 1024 -source "drivers/pci/Kconfig" source "drivers/eisa/Kconfig" source "drivers/pcmcia/Kconfig" diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig
[PATCH 5/9] powerpc: PCI_MSI needs PCI
Various powerpc boards select the PCI_MSI config option without selecting PCI, resulting in potentially not compilable configurations if the by default enabled PCI option is disabled. Explicitly select PCI to ensure we always have valid configs. Signed-off-by: Christoph Hellwig Acked-by: Thomas Gleixner --- arch/powerpc/platforms/40x/Kconfig | 1 + arch/powerpc/platforms/44x/Kconfig | 3 +++ 2 files changed, 4 insertions(+) diff --git a/arch/powerpc/platforms/40x/Kconfig b/arch/powerpc/platforms/40x/Kconfig index 60254a321a91..d5361e63e0bb 100644 --- a/arch/powerpc/platforms/40x/Kconfig +++ b/arch/powerpc/platforms/40x/Kconfig @@ -33,6 +33,7 @@ config KILAUEA select 405EX select PPC40x_SIMPLE select PPC4xx_PCI_EXPRESS + select PCI select PCI_MSI select PPC4xx_MSI help diff --git a/arch/powerpc/platforms/44x/Kconfig b/arch/powerpc/platforms/44x/Kconfig index a6011422b861..70856a213663 100644 --- a/arch/powerpc/platforms/44x/Kconfig +++ b/arch/powerpc/platforms/44x/Kconfig @@ -24,6 +24,7 @@ config BLUESTONE default n select PPC44x_SIMPLE select APM821xx + select PCI select PCI_MSI select PPC4xx_MSI select PPC4xx_PCI_EXPRESS @@ -78,6 +79,7 @@ config KATMAI select 440SPe select PCI select PPC4xx_PCI_EXPRESS + select PCI select PCI_MSI select PPC4xx_MSI help @@ -219,6 +221,7 @@ config AKEBONO select SWIOTLB select 476FPE select PPC4xx_PCI_EXPRESS + select PCI select PCI_MSI select PPC4xx_HSTA_MSI select I2C -- 2.19.1
[PATCH 4/9] powerpc: remove CONFIG_MCA leftovers
Signed-off-by: Christoph Hellwig Acked-by: Thomas Gleixner --- arch/powerpc/Kconfig | 4 drivers/scsi/Kconfig | 6 +++--- 2 files changed, 3 insertions(+), 7 deletions(-) diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig index e8c8970248bc..d4e97469a5f0 100644 --- a/arch/powerpc/Kconfig +++ b/arch/powerpc/Kconfig @@ -941,10 +941,6 @@ config FSL_GTM help Freescale General-purpose Timers support -# Yes MCA RS/6000s exist but Linux-PPC does not currently support any -config MCA - bool - # Platforms that what PCI turned unconditionally just do select PCI # in their config node. Platforms that want to choose at config # time should select PPC_PCI_CHOICE diff --git a/drivers/scsi/Kconfig b/drivers/scsi/Kconfig index 7c097006c54d..d3734c54aec9 100644 --- a/drivers/scsi/Kconfig +++ b/drivers/scsi/Kconfig @@ -535,7 +535,7 @@ config SCSI_HPTIOP config SCSI_BUSLOGIC tristate "BusLogic SCSI support" - depends on (PCI || ISA || MCA) && SCSI && ISA_DMA_API && VIRT_TO_BUS + depends on (PCI || ISA) && SCSI && ISA_DMA_API && VIRT_TO_BUS ---help--- This is support for BusLogic MultiMaster and FlashPoint SCSI Host Adapters. Consult the SCSI-HOWTO, available from @@ -1142,12 +1142,12 @@ config SCSI_LPFC_DEBUG_FS config SCSI_SIM710 tristate "Simple 53c710 SCSI support (Compaq, NCR machines)" - depends on (EISA || MCA) && SCSI + depends on EISA && SCSI select SCSI_SPI_ATTRS ---help--- This driver is for NCR53c710 based SCSI host adapters. - It currently supports Compaq EISA cards and NCR MCA cards + It currently supports Compaq EISA cards. config SCSI_DC395x tristate "Tekram DC395(U/UW/F) and DC315(U) SCSI support" -- 2.19.1
[PATCH 3/9] powerpc: remove CONFIG_PCI_QSPAN
This option isn't actually used anywhere. Signed-off-by: Christoph Hellwig Acked-by: Benjamin Herrenschmidt --- arch/powerpc/Kconfig | 9 - 1 file changed, 9 deletions(-) diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig index a80669209155..e8c8970248bc 100644 --- a/arch/powerpc/Kconfig +++ b/arch/powerpc/Kconfig @@ -955,7 +955,6 @@ config PCI bool "PCI support" if PPC_PCI_CHOICE default y if !40x && !CPM2 && !PPC_8xx && !PPC_83xx \ && !PPC_85xx && !PPC_86xx && !GAMECUBE_COMMON - default PCI_QSPAN if PPC_8xx select GENERIC_PCI_IOMAP help Find out whether your system includes a PCI bus. PCI is the name of @@ -969,14 +968,6 @@ config PCI_DOMAINS config PCI_SYSCALL def_bool PCI -config PCI_QSPAN - bool "QSpan PCI" - depends on PPC_8xx - select PPC_I8259 - help - Say Y here if you have a system based on a Motorola 8xx-series - embedded processor with a QSPAN PCI interface, otherwise say N. - config PCI_8260 bool depends on PCI && 8260 -- 2.19.1
[PATCH 2/9] arm: remove EISA kconfig option
No arm config enables EISA, and arm does not include drivers/eisa/Kconfig which provides support for things like PCI to EISA bridges, so it is most likely dead. If this is wrong we will be able to resurrect it easily by selecting HAVE_EISA for the right arm configs after this series. Suggested-by: Masahiro Yamada Signed-off-by: Christoph Hellwig --- arch/arm/Kconfig | 15 --- 1 file changed, 15 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index e8cd55a5b04c..e33735ce1c14 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -165,21 +165,6 @@ config HAVE_PROC_CPU config NO_IOPORT_MAP bool -config EISA - bool - ---help--- - The Extended Industry Standard Architecture (EISA) bus was - developed as an open alternative to the IBM MicroChannel bus. - - The EISA bus provided some of the features of the IBM MicroChannel - bus while maintaining backward compatibility with cards made for - the older ISA bus. The EISA bus saw limited use between 1988 and - 1995 when it was made obsolete by the PCI bus. - - Say Y here if you are building a kernel for an EISA-based machine. - - Otherwise, say N. - config SBUS bool -- 2.19.1
move bus (PCI, PCMCIA, EISA, rapdio) config to drivers/ v3
Hi all, currently every architecture that wants to provide on of the common periphal busses needs to add some boilerplate code and include the right Kconfig files. This series instead just selects the presence (when needed) and then handles everything in the bus-specific Kconfig file under drivers/. Changes since v2: - depend on HAVE_PCI for PCIe endpoint code - fix some commit message typos - remove CONFIG_PCI from xtensa iss defconfig - drop EISA support from arm - clean up EISA selection for alpha Changes since v1: - rename all HAS_* Kconfig symbols to HAVE_* - drop the CONFIG_PCI_QSPAN option entirely - drop duplicate select from powerpc - restore missing selection of PCI_MSI for riscv - update x86 and riscv defconfigs to include PCI - actually inclue drivers/eisa/Kconfig - adjust some captilizations
[PATCH 1/9] aha152x: rename the PCMCIA define
We plan to enable building the PCMCIA core and drivers, and the
non-prefixed PCMCIA name clashes with some arch headers.
Signed-off-by: Christoph Hellwig
Acked-by: Thomas Gleixner
---
drivers/scsi/aha152x.c | 14 +++---
drivers/scsi/pcmcia/aha152x_core.c | 2 +-
2 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/scsi/aha152x.c b/drivers/scsi/aha152x.c
index 4d7b0e0adbf7..301b3cad15f8 100644
--- a/drivers/scsi/aha152x.c
+++ b/drivers/scsi/aha152x.c
@@ -269,7 +269,7 @@ static LIST_HEAD(aha152x_host_list);
/* DEFINES */
/* For PCMCIA cards, always use AUTOCONF */
-#if defined(PCMCIA) || defined(MODULE)
+#if defined(AHA152X_PCMCIA) || defined(MODULE)
#if !defined(AUTOCONF)
#define AUTOCONF
#endif
@@ -297,7 +297,7 @@ CMD_INC_RESID(struct scsi_cmnd *cmd, int inc)
#define DELAY_DEFAULT 1000
-#if defined(PCMCIA)
+#if defined(AHA152X_PCMCIA)
#define IRQ_MIN 0
#define IRQ_MAX 16
#else
@@ -328,7 +328,7 @@ MODULE_AUTHOR("Jürgen Fischer");
MODULE_DESCRIPTION(AHA152X_REVID);
MODULE_LICENSE("GPL");
-#if !defined(PCMCIA)
+#if !defined(AHA152X_PCMCIA)
#if defined(MODULE)
static int io[] = {0, 0};
module_param_hw_array(io, int, ioport, NULL, 0);
@@ -391,7 +391,7 @@ static struct isapnp_device_id id_table[] = {
MODULE_DEVICE_TABLE(isapnp, id_table);
#endif /* ISAPNP */
-#endif /* !PCMCIA */
+#endif /* !AHA152X_PCMCIA */
static struct scsi_host_template aha152x_driver_template;
@@ -863,7 +863,7 @@ void aha152x_release(struct Scsi_Host *shpnt)
if (shpnt->irq)
free_irq(shpnt->irq, shpnt);
-#if !defined(PCMCIA)
+#if !defined(AHA152X_PCMCIA)
if (shpnt->io_port)
release_region(shpnt->io_port, IO_RANGE);
#endif
@@ -2924,7 +2924,7 @@ static struct scsi_host_template aha152x_driver_template
= {
.slave_alloc= aha152x_adjust_queue,
};
-#if !defined(PCMCIA)
+#if !defined(AHA152X_PCMCIA)
static int setup_count;
static struct aha152x_setup setup[2];
@@ -3392,4 +3392,4 @@ static int __init aha152x_setup(char *str)
__setup("aha152x=", aha152x_setup);
#endif
-#endif /* !PCMCIA */
+#endif /* !AHA152X_PCMCIA */
diff --git a/drivers/scsi/pcmcia/aha152x_core.c
b/drivers/scsi/pcmcia/aha152x_core.c
index dba3716511c5..24b89228b241 100644
--- a/drivers/scsi/pcmcia/aha152x_core.c
+++ b/drivers/scsi/pcmcia/aha152x_core.c
@@ -1,3 +1,3 @@
-#define PCMCIA 1
+#define AHA152X_PCMCIA 1
#define AHA152X_STAT 1
#include "aha152x.c"
--
2.19.1
Re: move bus (PCI, PCMCIA, EISA, rapdio) config to drivers/ v2
On Fri, Oct 19, 2018 at 09:22:08AM +0200, Geert Uytterhoeven wrote: > Hi Christoph, > > On Fri, Oct 19, 2018 at 9:10 AM Christoph Hellwig wrote: > > On Fri, Oct 19, 2018 at 09:07:51AM +0200, Geert Uytterhoeven wrote: > > > Without this: > > > - It's hard to visually match your untagged cover letter with the > > > actual patches, > > > - Your individual patches lack the version info, so people cannot see > > > which > > > version review comments in an email reply apply to. > > > > All of that is trivially solved by mail threading. > > You forgot to answer this question: > > | Can you please clarify what exactly that would mess up? It makes the already limited space in the subject line even shorted (or harder to read depending on which way you go) for absolutely not good reason.
Re: [PATCH 13/36] dt-bindings: arm: Convert PMU binding to json-schema
Hi Rob, On Wed, Oct 10, 2018 at 01:51:24PM -0500, Rob Herring wrote: > On Wed, Oct 10, 2018 at 11:50 AM Will Deacon wrote: > > On Tue, Oct 09, 2018 at 01:14:02PM -0500, Rob Herring wrote: > > > I guess the single interrupt case is less obvious now with no > > > description (it's the first list item of 'oneOf'). The schema If the > > > single interrupt is not supported, then we can drop it here. > > > > Well the description says "1 interrupt per core" which is incorrect. > > You are reading the schema wrong. There are 2 cases supported as > defined by each '-'. The 2nd case is all the keywords until the > indentation decreases. So 'description' is just description of the 2nd > case. The first case is just "maxItems: 1". I probably didn't put a > description because why write in free form text what the schema says > (other than of course no one knows json-schema...). Apologies, I've not read one of these things before and looks like I completely misread it. > YAML combines the best of Makefiles and python. You can't have tabs > and Indentation is significant. :) Oh wow, I'm in way over my head here! > > I also > > don't understand why maxItems is 8. > > Humm, I probably just made that up based on GICv2 limitations. What > should it be? If there's not any inherit maximum, can we put something > reasonable? There's not really any way to express that it should match > the number of cores in the system. What's the largest number you can think of? Will
Re: [PATCH] idle/x86: remove the call to boot_init_stack_canary() from cpu_startup_entry()
Le 19/10/2018 à 12:01, Juergen Gross a écrit :
On 19/10/2018 11:29, Christophe Leroy wrote:
commit d7880812b359 ("idle: Add the stack canary init to
cpu_startup_entry()") added the call to boot_init_stack_canary()
in cpu_startup_entry() in an #ifdef CONFIG_X86 statement, with
the intention to remove that #ifdef later.
While implementing stack protector for powerpc, it has been
observed that calling boot_init_stack_canary() is also needed
for powerpc which uses per task (TLS) stack canary like the X86.
However, calling boot_init_stack_canary() would break arches
using global stack canary (ARM, SH, MIPS and XTENSA).
Instead of adding modifying the #ifdef in a
implemented the call to boot_init_stack_canary() in the function
calling cpu_startup_entry()
I can't parse this sentence.
Oops, git commit took the #if for a comment and droped it. Fixed in v2.
On x86, we have two functions calling cpu_startup_entry():
- start_secondary()
- cpu_bringup_and_idle()
start_secondary() already calls boot_init_stack_canary().
This patch adds the call to boot_init_stack_canary() in
cpu_bringup_and_idle() and removes it from cpu_startup_entry()
Signed-off-by: Christophe Leroy
With the commit message made understandable you can add my
Reviewed-by: Juergen Gross
Thanks
Christophe
[PATCH v2] idle/x86: remove the call to boot_init_stack_canary() from cpu_startup_entry()
commit d7880812b359 ("idle: Add the stack canary init to
cpu_startup_entry()") added the call to boot_init_stack_canary()
in cpu_startup_entry() in an #ifdef CONFIG_X86 statement, with
the intention to remove that #ifdef later.
While implementing stack protector for powerpc, it has been
observed that calling boot_init_stack_canary() is also needed
for powerpc which uses per task (TLS) stack canary like the X86.
However, calling boot_init_stack_canary() would break arches
using global stack canary (ARM, SH, MIPS and XTENSA).
Instead of modifying the #ifdef CONFIG_X86 in an
#if defined(CONFIG_X86) || defined(CONFIG_PPC), powerpc
implemented the call to boot_init_stack_canary() in the function
calling cpu_startup_entry()
On x86, we have two functions calling cpu_startup_entry():
- start_secondary()
- cpu_bringup_and_idle()
start_secondary() already calls boot_init_stack_canary().
This patch adds the call to boot_init_stack_canary() in
cpu_bringup_and_idle() and removes it from cpu_startup_entry()
Reviewed-by: Juergen Gross
Signed-off-by: Christophe Leroy
---
v2: Revised commit log (#if defined had been droped by 'git commit')
arch/x86/xen/smp_pv.c | 1 +
kernel/sched/idle.c | 15 ---
2 files changed, 1 insertion(+), 15 deletions(-)
diff --git a/arch/x86/xen/smp_pv.c b/arch/x86/xen/smp_pv.c
index e3b18ad49889..0e05e8e23998 100644
--- a/arch/x86/xen/smp_pv.c
+++ b/arch/x86/xen/smp_pv.c
@@ -88,6 +88,7 @@ static void cpu_bringup(void)
asmlinkage __visible void cpu_bringup_and_idle(void)
{
cpu_bringup();
+ boot_init_stack_canary();
cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
}
diff --git a/kernel/sched/idle.c b/kernel/sched/idle.c
index 16f84142f2f4..f5516bae0c1b 100644
--- a/kernel/sched/idle.c
+++ b/kernel/sched/idle.c
@@ -347,21 +347,6 @@ EXPORT_SYMBOL_GPL(play_idle);
void cpu_startup_entry(enum cpuhp_state state)
{
- /*
-* This #ifdef needs to die, but it's too late in the cycle to
-* make this generic (ARM and SH have never invoked the canary
-* init for the non boot CPUs!). Will be fixed in 3.11
-*/
-#ifdef CONFIG_X86
- /*
-* If we're the non-boot CPU, nothing set the stack canary up
-* for us. The boot CPU already has it initialized but no harm
-* in doing it again. This is a good place for updating it, as
-* we wont ever return from this function (so the invalid
-* canaries already on the stack wont ever trigger).
-*/
- boot_init_stack_canary();
-#endif
arch_cpu_idle_prepare();
cpuhp_online_idle(state);
while (1)
--
2.13.3
[PATCH] KVM: PPC: Use exported tb_to_ns() function in decrementer emulation
This changes the KVM code that emulates the decrementer function to do the conversion of decrementer values to time intervals in nanoseconds by calling the tb_to_ns() function exported by the powerpc timer code, in preference to open-coded arithmetic using values from the decrementer_clockevent struct. Similarly, the HV-KVM code that did the same conversion using arithmetic on tb_ticks_per_sec also now uses tb_to_ns(). Signed-off-by: Paul Mackerras --- arch/powerpc/kvm/book3s_hv.c | 3 +-- arch/powerpc/kvm/emulate.c | 6 ++ 2 files changed, 3 insertions(+), 6 deletions(-) diff --git a/arch/powerpc/kvm/book3s_hv.c b/arch/powerpc/kvm/book3s_hv.c index bf8def2..d65b961 100644 --- a/arch/powerpc/kvm/book3s_hv.c +++ b/arch/powerpc/kvm/book3s_hv.c @@ -2337,8 +2337,7 @@ static void kvmppc_set_timer(struct kvm_vcpu *vcpu) kvmppc_core_prepare_to_enter(vcpu); return; } - dec_nsec = (vcpu->arch.dec_expires - now) * NSEC_PER_SEC - / tb_ticks_per_sec; + dec_nsec = tb_to_ns(vcpu->arch.dec_expires - now); hrtimer_start(>arch.dec_timer, dec_nsec, HRTIMER_MODE_REL); vcpu->arch.timer_running = 1; } diff --git a/arch/powerpc/kvm/emulate.c b/arch/powerpc/kvm/emulate.c index fa888bf..7a7c348 100644 --- a/arch/powerpc/kvm/emulate.c +++ b/arch/powerpc/kvm/emulate.c @@ -62,11 +62,9 @@ void kvmppc_emulate_dec(struct kvm_vcpu *vcpu) dec_time = vcpu->arch.dec; /* * Guest timebase ticks at the same frequency as host decrementer. -* So use the host decrementer calculations for decrementer emulation. +* So use the host timebase calculations for decrementer emulation. */ - dec_time = dec_time << decrementer_clockevent.shift; - do_div(dec_time, decrementer_clockevent.mult); - dec_nsec = do_div(dec_time, NSEC_PER_SEC); + dec_nsec = tb_to_ns(dec_time); hrtimer_start(>arch.dec_timer, ktime_set(dec_time, dec_nsec), HRTIMER_MODE_REL); vcpu->arch.dec_jiffies = get_tb(); -- 2.7.4
Re: [PATCH] idle/x86: remove the call to boot_init_stack_canary() from cpu_startup_entry()
On 19/10/2018 11:29, Christophe Leroy wrote:
> commit d7880812b359 ("idle: Add the stack canary init to
> cpu_startup_entry()") added the call to boot_init_stack_canary()
> in cpu_startup_entry() in an #ifdef CONFIG_X86 statement, with
> the intention to remove that #ifdef later.
>
> While implementing stack protector for powerpc, it has been
> observed that calling boot_init_stack_canary() is also needed
> for powerpc which uses per task (TLS) stack canary like the X86.
>
> However, calling boot_init_stack_canary() would break arches
> using global stack canary (ARM, SH, MIPS and XTENSA).
>
> Instead of adding modifying the #ifdef in a
> implemented the call to boot_init_stack_canary() in the function
> calling cpu_startup_entry()
I can't parse this sentence.
>
> On x86, we have two functions calling cpu_startup_entry():
> - start_secondary()
> - cpu_bringup_and_idle()
>
> start_secondary() already calls boot_init_stack_canary().
>
> This patch adds the call to boot_init_stack_canary() in
> cpu_bringup_and_idle() and removes it from cpu_startup_entry()
>
> Signed-off-by: Christophe Leroy
With the commit message made understandable you can add my
Reviewed-by: Juergen Gross
Juergen
[PATCH] idle/x86: remove the call to boot_init_stack_canary() from cpu_startup_entry()
commit d7880812b359 ("idle: Add the stack canary init to
cpu_startup_entry()") added the call to boot_init_stack_canary()
in cpu_startup_entry() in an #ifdef CONFIG_X86 statement, with
the intention to remove that #ifdef later.
While implementing stack protector for powerpc, it has been
observed that calling boot_init_stack_canary() is also needed
for powerpc which uses per task (TLS) stack canary like the X86.
However, calling boot_init_stack_canary() would break arches
using global stack canary (ARM, SH, MIPS and XTENSA).
Instead of adding modifying the #ifdef in a
implemented the call to boot_init_stack_canary() in the function
calling cpu_startup_entry()
On x86, we have two functions calling cpu_startup_entry():
- start_secondary()
- cpu_bringup_and_idle()
start_secondary() already calls boot_init_stack_canary().
This patch adds the call to boot_init_stack_canary() in
cpu_bringup_and_idle() and removes it from cpu_startup_entry()
Signed-off-by: Christophe Leroy
---
arch/x86/xen/smp_pv.c | 1 +
kernel/sched/idle.c | 15 ---
2 files changed, 1 insertion(+), 15 deletions(-)
diff --git a/arch/x86/xen/smp_pv.c b/arch/x86/xen/smp_pv.c
index e3b18ad49889..0e05e8e23998 100644
--- a/arch/x86/xen/smp_pv.c
+++ b/arch/x86/xen/smp_pv.c
@@ -88,6 +88,7 @@ static void cpu_bringup(void)
asmlinkage __visible void cpu_bringup_and_idle(void)
{
cpu_bringup();
+ boot_init_stack_canary();
cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
}
diff --git a/kernel/sched/idle.c b/kernel/sched/idle.c
index 16f84142f2f4..f5516bae0c1b 100644
--- a/kernel/sched/idle.c
+++ b/kernel/sched/idle.c
@@ -347,21 +347,6 @@ EXPORT_SYMBOL_GPL(play_idle);
void cpu_startup_entry(enum cpuhp_state state)
{
- /*
-* This #ifdef needs to die, but it's too late in the cycle to
-* make this generic (ARM and SH have never invoked the canary
-* init for the non boot CPUs!). Will be fixed in 3.11
-*/
-#ifdef CONFIG_X86
- /*
-* If we're the non-boot CPU, nothing set the stack canary up
-* for us. The boot CPU already has it initialized but no harm
-* in doing it again. This is a good place for updating it, as
-* we wont ever return from this function (so the invalid
-* canaries already on the stack wont ever trigger).
-*/
- boot_init_stack_canary();
-#endif
arch_cpu_idle_prepare();
cpuhp_online_idle(state);
while (1)
--
2.13.3
Re: move bus (PCI, PCMCIA, EISA, rapdio) config to drivers/ v2
Hi Christoph,
On Fri, Oct 19, 2018 at 9:10 AM Christoph Hellwig wrote:
> On Fri, Oct 19, 2018 at 09:07:51AM +0200, Geert Uytterhoeven wrote:
> > Without this:
> > - It's hard to visually match your untagged cover letter with the
> > actual patches,
> > - Your individual patches lack the version info, so people cannot see
> > which
> > version review comments in an email reply apply to.
>
> All of that is trivially solved by mail threading.
You forgot to answer this question:
| Can you please clarify what exactly that would mess up?
Thanks!
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Re: move bus (PCI, PCMCIA, EISA, rapdio) config to drivers/ v2
On Fri, Oct 19, 2018 at 09:07:51AM +0200, Geert Uytterhoeven wrote: > Without this: > - It's hard to visually match your untagged cover letter with the > actual patches, > - Your individual patches lack the version info, so people cannot see which > version review comments in an email reply apply to. All of that is trivially solved by mail threading.
Re: move bus (PCI, PCMCIA, EISA, rapdio) config to drivers/ v2
Hi Christoph,
On Fri, Oct 19, 2018 at 9:00 AM Christoph Hellwig wrote:
> On Wed, Oct 17, 2018 at 10:30:49AM +0200, Geert Uytterhoeven wrote:
> > Please use "git format-patch -v --cover" to prepare patch series
> > for sending with git-send-email.
> >
> > "-v" to prefix all patches with version number ,
> > "--cover" to have a "[PATCH 0/]" prefix in the cover letter.
>
> We had that discussion before and I strongly disagree with messing
> up the subject lines like that. The git-send-email defaults are
> perfectly fine.
Can you please clarify what exactly that would mess up?
Documentation/process/submitting-patches.rst even mentions the tags
to put in "[PATCH ]"?
Without this:
- It's hard to visually match your untagged cover letter with the
actual patches,
- Your individual patches lack the version info, so people cannot see which
version review comments in an email reply apply to.
Thanks!
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Re: [PATCH 7/8] eisa: consolidate EISA Kconfig entry in drivers/eisa
On Fri, Oct 19, 2018 at 01:46:50PM +0900, Masahiro Yamada wrote: > > --- a/arch/arm/Kconfig > > +++ b/arch/arm/Kconfig > > @@ -59,6 +59,7 @@ config ARM > > select HAVE_ARCH_TRACEHOOK > > select HAVE_ARM_SMCCC if CPU_V7 > > select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32 > > + select HAVE_EISA > > I doubt this. > > arch/arm/Kconfig previously did not include > driver/eisa/Kconfig. > > No ARM platform enabled CONFIG_EISA either. But it did offer the EISA option. I guess I can remove this in a separate commit and see if anyone screams.
Re: [PATCH 4/8] PCI: consolidate PCI config entry in drivers/pci
On Fri, Oct 19, 2018 at 02:07:04PM +0900, Masahiro Yamada wrote: > We could add 'depends on HAVE_PCI' or something > to guard it to avoid changing the logic. I guess that makes sense. > config PCI_ENDPOINT > bool "PCI Endpoint Support" > depends on HAVE_PCI # Is this correct ?? > depends on HAS_DMA > > > or better to have 'depends on PCI' ? It does not depend on the normal PCI support, so I don't think this is the right thing to do.
Re: move bus (PCI, PCMCIA, EISA, rapdio) config to drivers/ v2
On Wed, Oct 17, 2018 at 10:30:49AM +0200, Geert Uytterhoeven wrote: > Please use "git format-patch -v --cover" to prepare patch series > for sending with git-send-email. > > "-v" to prefix all patches with version number , > "--cover" to have a "[PATCH 0/]" prefix in the cover letter. We had that discussion before and I strongly disagree with messing up the subject lines like that. The git-send-email defaults are perfectly fine.
[PATCH v6 20/20] powerpc/mm: reintroduce 16K pages with HW assistance on 8xx
Using this HW assistance implies some constraints on the
page table structure:
- Regardless of the main page size used (4k or 16k), the
level 1 table (PGD) contains 1024 entries and each PGD entry covers
a 4Mbytes area which is managed by a level 2 table (PTE) containing
also 1024 entries each describing a 4k page.
- 16k pages require 4 identifical entries in the L2 table
- 512k pages PTE have to be spread every 128 bytes in the L2 table
- 8M pages PTE are at the address pointed by the L1 entry and each
8M page require 2 identical entries in the PGD.
In order to use hardware assistance with 16K pages, this patch does
the following modifications:
- Make PGD size independent of the main page size
- In 16k pages mode, redefine pte_t as a struct with 4 elements,
and populate those 4 elements in __set_pte_at() and pte_update()
- Adapt the size of the hugepage tables.
Signed-off-by: Christophe Leroy
---
arch/powerpc/Kconfig | 2 +-
arch/powerpc/include/asm/nohash/32/pgtable.h | 18 +-
arch/powerpc/include/asm/nohash/pgtable.h| 4
arch/powerpc/include/asm/pgtable-types.h | 4
4 files changed, 26 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 287befcf37ab..3d008115fe18 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -690,7 +690,7 @@ config PPC_4K_PAGES
config PPC_16K_PAGES
bool "16k page size"
- depends on 44x
+ depends on 44x || PPC_8xx
config PPC_64K_PAGES
bool "64k page size"
diff --git a/arch/powerpc/include/asm/nohash/32/pgtable.h
b/arch/powerpc/include/asm/nohash/32/pgtable.h
index c33fbbb7ce82..19941fb8d690 100644
--- a/arch/powerpc/include/asm/nohash/32/pgtable.h
+++ b/arch/powerpc/include/asm/nohash/32/pgtable.h
@@ -19,9 +19,15 @@ extern int icache_44x_need_flush;
#endif /* __ASSEMBLY__ */
+#if defined(CONFIG_PPC_8xx) && defined(CONFIG_PPC_16K_PAGES)
+#define PTE_INDEX_SIZE (PTE_SHIFT - 2)
+#define PTE_FRAG_NR4
+#define PTE_FRAG_SIZE_SHIFT12
+#else
#define PTE_INDEX_SIZE PTE_SHIFT
#define PTE_FRAG_NR1
#define PTE_FRAG_SIZE_SHIFTPAGE_SHIFT
+#endif
#define PTE_FRAG_SIZE (1UL << PTE_FRAG_SIZE_SHIFT)
#define PMD_INDEX_SIZE 0
@@ -52,7 +58,11 @@ extern int icache_44x_need_flush;
* -Matt
*/
/* PGDIR_SHIFT determines what a top-level page table entry can map */
+#ifdef CONFIG_PPC_8xx
+#define PGDIR_SHIFT22
+#else
#define PGDIR_SHIFT(PAGE_SHIFT + PTE_INDEX_SIZE)
+#endif
#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
#define PGDIR_MASK (~(PGDIR_SIZE-1))
@@ -236,7 +246,13 @@ static inline unsigned long pte_update(pte_t *p,
: "cc" );
#else /* PTE_ATOMIC_UPDATES */
unsigned long old = pte_val(*p);
- *p = __pte((old & ~clr) | set);
+ unsigned long new = (old & ~clr) | set;
+
+#if defined(CONFIG_PPC_8xx) && defined(CONFIG_PPC_16K_PAGES)
+ p->pte = p->pte1 = p->pte2 = p->pte3 = new;
+#else
+ *p = __pte(new);
+#endif
#endif /* !PTE_ATOMIC_UPDATES */
#ifdef CONFIG_44x
diff --git a/arch/powerpc/include/asm/nohash/pgtable.h
b/arch/powerpc/include/asm/nohash/pgtable.h
index 70ff23974b59..1ca1c1864b32 100644
--- a/arch/powerpc/include/asm/nohash/pgtable.h
+++ b/arch/powerpc/include/asm/nohash/pgtable.h
@@ -209,7 +209,11 @@ static inline void __set_pte_at(struct mm_struct *mm,
unsigned long addr,
/* Anything else just stores the PTE normally. That covers all 64-bit
* cases, and 32-bit non-hash with 32-bit PTEs.
*/
+#if defined(CONFIG_PPC_8xx) && defined(CONFIG_PPC_16K_PAGES)
+ ptep->pte = ptep->pte1 = ptep->pte2 = ptep->pte3 = pte_val(pte);
+#else
*ptep = pte;
+#endif
/*
* With hardware tablewalk, a sync is needed to ensure that
diff --git a/arch/powerpc/include/asm/pgtable-types.h
b/arch/powerpc/include/asm/pgtable-types.h
index eccb30b38b47..3b0edf041b2e 100644
--- a/arch/powerpc/include/asm/pgtable-types.h
+++ b/arch/powerpc/include/asm/pgtable-types.h
@@ -3,7 +3,11 @@
#define _ASM_POWERPC_PGTABLE_TYPES_H
/* PTE level */
+#if defined(CONFIG_PPC_8xx) && defined(CONFIG_PPC_16K_PAGES)
+typedef struct { pte_basic_t pte, pte1, pte2, pte3; } pte_t;
+#else
typedef struct { pte_basic_t pte; } pte_t;
+#endif
#define __pte(x) ((pte_t) { (x) })
static inline pte_basic_t pte_val(pte_t x)
{
--
2.13.3
[PATCH v6 19/20] powerpc/8xx: Remove PTE_ATOMIC_UPDATES
commit 1bc54c03117b9 ("powerpc: rework 4xx PTE access and TLB miss")
introduced non atomic PTE updates and started the work of removing
PTE updates in TLB miss handlers, but kept PTE_ATOMIC_UPDATES for the
8xx with the following comment:
/* Until my rework is finished, 8xx still needs atomic PTE updates */
commit fe11dc3f9628e ("powerpc/8xx: Update TLB asm so it behaves as
linux mm expects") removed all PTE updates done in TLB miss handlers
Therefore, atomic PTE updates are not needed anymore for the 8xx
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/nohash/32/pte-8xx.h | 3 ---
1 file changed, 3 deletions(-)
diff --git a/arch/powerpc/include/asm/nohash/32/pte-8xx.h
b/arch/powerpc/include/asm/nohash/32/pte-8xx.h
index 6bfe041ef59d..c9e4b2d90f65 100644
--- a/arch/powerpc/include/asm/nohash/32/pte-8xx.h
+++ b/arch/powerpc/include/asm/nohash/32/pte-8xx.h
@@ -65,9 +65,6 @@
#define _PTE_NONE_MASK 0
-/* Until my rework is finished, 8xx still needs atomic PTE updates */
-#define PTE_ATOMIC_UPDATES 1
-
#ifdef CONFIG_PPC_16K_PAGES
#define _PAGE_PSIZE_PAGE_SPS
#else
--
2.13.3
[PATCH v6 18/20] powerpc/mm: Extend pte_fragment functionality to nohash/32
In order to allow the 8xx to handle pte_fragments, this patch
extends the use of pte_fragments to nohash/32 platforms.
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/mmu_context.h | 2 +-
arch/powerpc/include/asm/nohash/32/mmu-40x.h | 1 +
arch/powerpc/include/asm/nohash/32/mmu-44x.h | 1 +
arch/powerpc/include/asm/nohash/32/mmu-8xx.h | 1 +
arch/powerpc/include/asm/nohash/32/mmu.h | 4 ++-
arch/powerpc/include/asm/nohash/32/pgalloc.h | 52 +---
arch/powerpc/include/asm/nohash/32/pgtable.h | 11 --
arch/powerpc/include/asm/nohash/mmu-book3e.h | 1 +
arch/powerpc/mm/Makefile | 3 ++
arch/powerpc/mm/mmu_context_nohash.c | 14
10 files changed, 57 insertions(+), 33 deletions(-)
diff --git a/arch/powerpc/include/asm/mmu_context.h
b/arch/powerpc/include/asm/mmu_context.h
index 0381394a425b..8eec1680b699 100644
--- a/arch/powerpc/include/asm/mmu_context.h
+++ b/arch/powerpc/include/asm/mmu_context.h
@@ -223,7 +223,7 @@ static inline int arch_dup_mmap(struct mm_struct *oldmm,
return 0;
}
-#ifndef CONFIG_PPC_BOOK3S_64
+#if defined(CONFIG_PPC_BOOK3E_64) || defined(CONFIG_PPC_BOOK3S_32)
static inline void arch_exit_mmap(struct mm_struct *mm)
{
}
diff --git a/arch/powerpc/include/asm/nohash/32/mmu-40x.h
b/arch/powerpc/include/asm/nohash/32/mmu-40x.h
index 74f4edb5916e..7c77ceed71d6 100644
--- a/arch/powerpc/include/asm/nohash/32/mmu-40x.h
+++ b/arch/powerpc/include/asm/nohash/32/mmu-40x.h
@@ -58,6 +58,7 @@ typedef struct {
unsigned intid;
unsigned intactive;
unsigned long vdso_base;
+ void *pte_frag;
} mm_context_t;
#endif /* !__ASSEMBLY__ */
diff --git a/arch/powerpc/include/asm/nohash/32/mmu-44x.h
b/arch/powerpc/include/asm/nohash/32/mmu-44x.h
index 295b3dbb2698..3d72e889ae7b 100644
--- a/arch/powerpc/include/asm/nohash/32/mmu-44x.h
+++ b/arch/powerpc/include/asm/nohash/32/mmu-44x.h
@@ -109,6 +109,7 @@ typedef struct {
unsigned intid;
unsigned intactive;
unsigned long vdso_base;
+ void *pte_frag;
} mm_context_t;
#endif /* !__ASSEMBLY__ */
diff --git a/arch/powerpc/include/asm/nohash/32/mmu-8xx.h
b/arch/powerpc/include/asm/nohash/32/mmu-8xx.h
index fa05aa566ece..750cef6f65e3 100644
--- a/arch/powerpc/include/asm/nohash/32/mmu-8xx.h
+++ b/arch/powerpc/include/asm/nohash/32/mmu-8xx.h
@@ -179,6 +179,7 @@ typedef struct {
unsigned int id;
unsigned int active;
unsigned long vdso_base;
+ void *pte_frag;
#ifdef CONFIG_PPC_MM_SLICES
u16 user_psize; /* page size index */
unsigned char low_slices_psize[SLICE_ARRAY_SIZE];
diff --git a/arch/powerpc/include/asm/nohash/32/mmu.h
b/arch/powerpc/include/asm/nohash/32/mmu.h
index f61f933a4cd8..7d94a36d57d2 100644
--- a/arch/powerpc/include/asm/nohash/32/mmu.h
+++ b/arch/powerpc/include/asm/nohash/32/mmu.h
@@ -2,6 +2,8 @@
#ifndef _ASM_POWERPC_NOHASH_32_MMU_H_
#define _ASM_POWERPC_NOHASH_32_MMU_H_
+#include
+
#if defined(CONFIG_40x)
/* 40x-style software loaded TLB */
#include
@@ -17,7 +19,7 @@
#endif
#ifndef __ASSEMBLY__
-typedef struct page *pgtable_t;
+typedef pte_t *pgtable_t;
#endif
#endif /* _ASM_POWERPC_NOHASH_32_MMU_H_ */
diff --git a/arch/powerpc/include/asm/nohash/32/pgalloc.h
b/arch/powerpc/include/asm/nohash/32/pgalloc.h
index 78367855a4f3..77c09bef3122 100644
--- a/arch/powerpc/include/asm/nohash/32/pgalloc.h
+++ b/arch/powerpc/include/asm/nohash/32/pgalloc.h
@@ -28,6 +28,10 @@ extern void __bad_pte(pmd_t *pmd);
extern struct kmem_cache *pgtable_cache[];
#define PGT_CACHE(shift) pgtable_cache[shift]
+void pte_frag_destroy(void *pte_frag);
+pte_t *pte_fragment_alloc(struct mm_struct *mm, unsigned long vmaddr, int
kernel);
+void pte_fragment_free(unsigned long *table, int kernel);
+
static inline pgd_t *pgd_alloc(struct mm_struct *mm)
{
return kmem_cache_alloc(PGT_CACHE(PGD_INDEX_SIZE),
@@ -59,11 +63,10 @@ static inline void pmd_populate_kernel(struct mm_struct
*mm, pmd_t *pmdp,
static inline void pmd_populate(struct mm_struct *mm, pmd_t *pmdp,
pgtable_t pte_page)
{
- *pmdp = __pmd((page_to_pfn(pte_page) << PAGE_SHIFT) | _PMD_USER |
- _PMD_PRESENT);
+ *pmdp = __pmd(__pa(pte_page) | _PMD_USER | _PMD_PRESENT);
}
-#define pmd_pgtable(pmd) pmd_page(pmd)
+#define pmd_pgtable(pmd) ((pgtable_t)pmd_page_vaddr(pmd))
#else
static inline void pmd_populate_kernel(struct mm_struct *mm, pmd_t *pmdp,
@@ -75,49 +78,38 @@ static inline void pmd_populate_kernel(struct mm_struct
*mm, pmd_t *pmdp,
static inline void pmd_populate(struct mm_struct *mm, pmd_t *pmdp,
pgtable_t pte_page)
{
- *pmdp = __pmd((unsigned long)lowmem_page_address(pte_page) |
_PMD_PRESENT);
+ *pmdp = __pmd((unsigned long)pte_page | _PMD_PRESENT);
}
-#define pmd_pgtable(pmd) pmd_page(pmd)
+#define
[PATCH v6 17/20] powerpc/book3s32: Remove CONFIG_BOOKE dependent code
BOOK3S/32 cannot be BOOKE, so remove useless code
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/book3s/32/pgalloc.h | 18 --
arch/powerpc/include/asm/book3s/32/pgtable.h | 14 --
2 files changed, 32 deletions(-)
diff --git a/arch/powerpc/include/asm/book3s/32/pgalloc.h
b/arch/powerpc/include/asm/book3s/32/pgalloc.h
index a4cf0de10931..711a8b84e3ee 100644
--- a/arch/powerpc/include/asm/book3s/32/pgalloc.h
+++ b/arch/powerpc/include/asm/book3s/32/pgalloc.h
@@ -48,8 +48,6 @@ static inline void pgd_free(struct mm_struct *mm, pgd_t *pgd)
#define __pmd_free_tlb(tlb,x,a)do { } while (0)
/* #define pgd_populate(mm, pmd, pte) BUG() */
-#ifndef CONFIG_BOOKE
-
static inline void pmd_populate_kernel(struct mm_struct *mm, pmd_t *pmdp,
pte_t *pte)
{
@@ -63,22 +61,6 @@ static inline void pmd_populate(struct mm_struct *mm, pmd_t
*pmdp,
}
#define pmd_pgtable(pmd) pmd_page(pmd)
-#else
-
-static inline void pmd_populate_kernel(struct mm_struct *mm, pmd_t *pmdp,
- pte_t *pte)
-{
- *pmdp = __pmd((unsigned long)pte | _PMD_PRESENT);
-}
-
-static inline void pmd_populate(struct mm_struct *mm, pmd_t *pmdp,
- pgtable_t pte_page)
-{
- *pmdp = __pmd((unsigned long)lowmem_page_address(pte_page) |
_PMD_PRESENT);
-}
-
-#define pmd_pgtable(pmd) pmd_page(pmd)
-#endif
static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm, unsigned long
address)
{
diff --git a/arch/powerpc/include/asm/book3s/32/pgtable.h
b/arch/powerpc/include/asm/book3s/32/pgtable.h
index e61dd3ae5bc0..0d477fc573cd 100644
--- a/arch/powerpc/include/asm/book3s/32/pgtable.h
+++ b/arch/powerpc/include/asm/book3s/32/pgtable.h
@@ -334,24 +334,10 @@ static inline void __ptep_set_access_flags(struct
vm_area_struct *vma,
#define __HAVE_ARCH_PTE_SAME
#define pte_same(A,B) (((pte_val(A) ^ pte_val(B)) & ~_PAGE_HASHPTE) == 0)
-/*
- * Note that on Book E processors, the pmd contains the kernel virtual
- * (lowmem) address of the pte page. The physical address is less useful
- * because everything runs with translation enabled (even the TLB miss
- * handler). On everything else the pmd contains the physical address
- * of the pte page. -- paulus
- */
-#ifndef CONFIG_BOOKE
#define pmd_page_vaddr(pmd)\
((unsigned long) __va(pmd_val(pmd) & PAGE_MASK))
#define pmd_page(pmd) \
pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT)
-#else
-#define pmd_page_vaddr(pmd)\
- ((unsigned long) (pmd_val(pmd) & PAGE_MASK))
-#define pmd_page(pmd) \
- pfn_to_page((__pa(pmd_val(pmd)) >> PAGE_SHIFT))
-#endif
/* to find an entry in a kernel page-table-directory */
#define pgd_offset_k(address) pgd_offset(_mm, address)
--
2.13.3
[PATCH v6 16/20] powerpc/mm: inline pte_alloc_one() and pte_alloc_one_kernel() in PPC32
As in PPC64, inline pte_alloc_one() and pte_alloc_one_kernel()
in PPC32. This will allow to switch nohash/32 to pte_fragment
without impacting hash/32.
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/book3s/32/pgalloc.h | 22 --
arch/powerpc/include/asm/nohash/32/pgalloc.h | 22 --
arch/powerpc/mm/pgtable_32.c | 21 -
3 files changed, 40 insertions(+), 25 deletions(-)
diff --git a/arch/powerpc/include/asm/book3s/32/pgalloc.h
b/arch/powerpc/include/asm/book3s/32/pgalloc.h
index 4ddc7df20381..a4cf0de10931 100644
--- a/arch/powerpc/include/asm/book3s/32/pgalloc.h
+++ b/arch/powerpc/include/asm/book3s/32/pgalloc.h
@@ -80,8 +80,26 @@ static inline void pmd_populate(struct mm_struct *mm, pmd_t
*pmdp,
#define pmd_pgtable(pmd) pmd_page(pmd)
#endif
-extern pte_t *pte_alloc_one_kernel(struct mm_struct *mm, unsigned long addr);
-extern pgtable_t pte_alloc_one(struct mm_struct *mm, unsigned long addr);
+static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm, unsigned long
address)
+{
+ return (pte_t *)__get_free_page(GFP_KERNEL | __GFP_ZERO);
+}
+
+static inline pgtable_t pte_alloc_one(struct mm_struct *mm, unsigned long
address)
+{
+ struct page *ptepage;
+
+ gfp_t flags = GFP_KERNEL | __GFP_ZERO | __GFP_ACCOUNT;
+
+ ptepage = alloc_pages(flags, 0);
+ if (!ptepage)
+ return NULL;
+ if (!pgtable_page_ctor(ptepage)) {
+ __free_page(ptepage);
+ return NULL;
+ }
+ return ptepage;
+}
static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte)
{
diff --git a/arch/powerpc/include/asm/nohash/32/pgalloc.h
b/arch/powerpc/include/asm/nohash/32/pgalloc.h
index da8fdfc76418..78367855a4f3 100644
--- a/arch/powerpc/include/asm/nohash/32/pgalloc.h
+++ b/arch/powerpc/include/asm/nohash/32/pgalloc.h
@@ -81,8 +81,26 @@ static inline void pmd_populate(struct mm_struct *mm, pmd_t
*pmdp,
#define pmd_pgtable(pmd) pmd_page(pmd)
#endif
-extern pte_t *pte_alloc_one_kernel(struct mm_struct *mm, unsigned long addr);
-extern pgtable_t pte_alloc_one(struct mm_struct *mm, unsigned long addr);
+static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm, unsigned long
address)
+{
+ return (pte_t *)__get_free_page(GFP_KERNEL | __GFP_ZERO);
+}
+
+static inline pgtable_t pte_alloc_one(struct mm_struct *mm, unsigned long
address)
+{
+ struct page *ptepage;
+
+ gfp_t flags = GFP_KERNEL | __GFP_ZERO | __GFP_ACCOUNT;
+
+ ptepage = alloc_pages(flags, 0);
+ if (!ptepage)
+ return NULL;
+ if (!pgtable_page_ctor(ptepage)) {
+ __free_page(ptepage);
+ return NULL;
+ }
+ return ptepage;
+}
static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte)
{
diff --git a/arch/powerpc/mm/pgtable_32.c b/arch/powerpc/mm/pgtable_32.c
index ea4442dde0d5..745f2f30d4e9 100644
--- a/arch/powerpc/mm/pgtable_32.c
+++ b/arch/powerpc/mm/pgtable_32.c
@@ -43,27 +43,6 @@ EXPORT_SYMBOL(ioremap_bot); /* aka VMALLOC_END */
extern char etext[], _stext[], _sinittext[], _einittext[];
-pte_t *pte_alloc_one_kernel(struct mm_struct *mm, unsigned long address)
-{
- return (pte_t *)__get_free_page(GFP_KERNEL | __GFP_ZERO);
-}
-
-pgtable_t pte_alloc_one(struct mm_struct *mm, unsigned long address)
-{
- struct page *ptepage;
-
- gfp_t flags = GFP_KERNEL | __GFP_ZERO | __GFP_ACCOUNT;
-
- ptepage = alloc_pages(flags, 0);
- if (!ptepage)
- return NULL;
- if (!pgtable_page_ctor(ptepage)) {
- __free_page(ptepage);
- return NULL;
- }
- return ptepage;
-}
-
void __iomem *
ioremap(phys_addr_t addr, unsigned long size)
{
--
2.13.3
[PATCH v6 15/20] powerpc/mm: don't use pte_alloc_one_kernel() before slab is available
In the same way as PPC64, let's handle pte allocation directly
in kernel_map_page() when slab is not available.
The new function early_pte_alloc_kernel() is put in as inline in
platforms pgalloc.h, this will allow to have different ones later.
It is not an issue because early_pte_alloc_kernel() is called only
once from map_kernel_page() and is inlined anyway.
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/book3s/32/pgalloc.h | 15 +++
arch/powerpc/include/asm/nohash/32/pgalloc.h | 15 +++
arch/powerpc/mm/pgtable_32.c | 20 +++-
3 files changed, 37 insertions(+), 13 deletions(-)
diff --git a/arch/powerpc/include/asm/book3s/32/pgalloc.h
b/arch/powerpc/include/asm/book3s/32/pgalloc.h
index 96138ab3ddd6..4ddc7df20381 100644
--- a/arch/powerpc/include/asm/book3s/32/pgalloc.h
+++ b/arch/powerpc/include/asm/book3s/32/pgalloc.h
@@ -4,6 +4,7 @@
#include
#include
+#include
/*
* Functions that deal with pagetables that could be at any level of
@@ -137,4 +138,18 @@ static inline void __pte_free_tlb(struct mmu_gather *tlb,
pgtable_t table,
{
pgtable_free_tlb(tlb, page_address(table), 0);
}
+
+static inline pte_t *early_pte_alloc_kernel(pmd_t *pmdp, unsigned long va)
+{
+ if (!pmd_present(*pmdp)) {
+ pte_t *ptep = __va(memblock_alloc(PAGE_SIZE, PAGE_SIZE));
+
+ if (!ptep)
+ return NULL;
+
+ clear_page(ptep);
+ pmd_populate_kernel(_mm, pmdp, ptep);
+ }
+ return pte_offset_kernel(pmdp, va);
+}
#endif /* _ASM_POWERPC_BOOK3S_32_PGALLOC_H */
diff --git a/arch/powerpc/include/asm/nohash/32/pgalloc.h
b/arch/powerpc/include/asm/nohash/32/pgalloc.h
index 6fbbb90043c0..da8fdfc76418 100644
--- a/arch/powerpc/include/asm/nohash/32/pgalloc.h
+++ b/arch/powerpc/include/asm/nohash/32/pgalloc.h
@@ -4,6 +4,7 @@
#include
#include
+#include
/*
* Functions that deal with pagetables that could be at any level of
@@ -139,4 +140,18 @@ static inline void __pte_free_tlb(struct mmu_gather *tlb,
pgtable_t table,
tlb_flush_pgtable(tlb, address);
pgtable_free_tlb(tlb, page_address(table), 0);
}
+
+static inline pte_t *early_pte_alloc_kernel(pmd_t *pmdp, unsigned long va)
+{
+ if (!pmd_present(*pmdp)) {
+ pte_t *ptep = __va(memblock_alloc(PAGE_SIZE, PAGE_SIZE));
+
+ if (!ptep)
+ return NULL;
+
+ clear_page(ptep);
+ pmd_populate_kernel(_mm, pmdp, ptep);
+ }
+ return pte_offset_kernel(pmdp, va);
+}
#endif /* _ASM_POWERPC_PGALLOC_32_H */
diff --git a/arch/powerpc/mm/pgtable_32.c b/arch/powerpc/mm/pgtable_32.c
index 5877f5aa8f5d..ea4442dde0d5 100644
--- a/arch/powerpc/mm/pgtable_32.c
+++ b/arch/powerpc/mm/pgtable_32.c
@@ -43,18 +43,9 @@ EXPORT_SYMBOL(ioremap_bot); /* aka VMALLOC_END */
extern char etext[], _stext[], _sinittext[], _einittext[];
-__ref pte_t *pte_alloc_one_kernel(struct mm_struct *mm, unsigned long address)
+pte_t *pte_alloc_one_kernel(struct mm_struct *mm, unsigned long address)
{
- pte_t *pte;
-
- if (slab_is_available()) {
- pte = (pte_t *)__get_free_page(GFP_KERNEL|__GFP_ZERO);
- } else {
- pte = __va(memblock_alloc(PAGE_SIZE, PAGE_SIZE));
- if (pte)
- clear_page(pte);
- }
- return pte;
+ return (pte_t *)__get_free_page(GFP_KERNEL | __GFP_ZERO);
}
pgtable_t pte_alloc_one(struct mm_struct *mm, unsigned long address)
@@ -222,7 +213,7 @@ void iounmap(volatile void __iomem *addr)
}
EXPORT_SYMBOL(iounmap);
-int map_kernel_page(unsigned long va, phys_addr_t pa, pgprot_t prot)
+__ref int map_kernel_page(unsigned long va, phys_addr_t pa, pgprot_t prot)
{
pmd_t *pd;
pte_t *pg;
@@ -231,7 +222,10 @@ int map_kernel_page(unsigned long va, phys_addr_t pa,
pgprot_t prot)
/* Use upper 10 bits of VA to index the first level map */
pd = pmd_offset(pud_offset(pgd_offset_k(va), va), va);
/* Use middle 10 bits of VA to index the second-level map */
- pg = pte_alloc_kernel(pd, va);
+ if (slab_is_available())
+ pg = pte_alloc_kernel(pd, va);
+ else
+ pg = early_pte_alloc_kernel(pd, va);
if (pg != 0) {
err = 0;
/* The PTE should never be already set nor present in the
--
2.13.3
[PATCH v6 14/20] powerpc/8xx: regroup TLB handler routines
As this is running with MMU off, the CPU only does speculative fetch for code in the same page. Following the significant size reduction of TLB handler routines, the side handlers can be brought back close to the main part, ie in the same page. Signed-off-by: Christophe Leroy --- arch/powerpc/kernel/head_8xx.S | 112 - 1 file changed, 54 insertions(+), 58 deletions(-) diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S index d69c6e3d5cc1..3e38af7489a9 100644 --- a/arch/powerpc/kernel/head_8xx.S +++ b/arch/powerpc/kernel/head_8xx.S @@ -400,6 +400,23 @@ InstructionTLBMiss: rfi #endif +#ifndef CONFIG_PIN_TLB_TEXT +ITLBMissLinear: + mtcrr11 + /* Set 8M byte page and mark it valid */ + li r11, MI_PS8MEG | MI_SVALID + mtspr SPRN_MI_TWC, r11 + rlwinm r10, r10, 20, 0x0f80/* 8xx supports max 256Mb RAM */ + ori r10, r10, 0xf0 | MI_SPS16K | _PAGE_SH | _PAGE_DIRTY | \ + _PAGE_PRESENT + mtspr SPRN_MI_RPN, r10/* Update TLB entry */ + +0: mfspr r10, SPRN_SPRG_SCRATCH0 + mfspr r11, SPRN_SPRG_SCRATCH1 + rfi + patch_site 0b, patch__itlbmiss_exit_2 +#endif + . = 0x1200 DataStoreTLBMiss: mtspr SPRN_SPRG_SCRATCH0, r10 @@ -485,6 +502,43 @@ DataStoreTLBMiss: rfi #endif +DTLBMissIMMR: + mtcrr11 + /* Set 512k byte guarded page and mark it valid */ + li r10, MD_PS512K | MD_GUARDED | MD_SVALID + mtspr SPRN_MD_TWC, r10 + mfspr r10, SPRN_IMMR /* Get current IMMR */ + rlwinm r10, r10, 0, 0xfff8 /* Get 512 kbytes boundary */ + ori r10, r10, 0xf0 | MD_SPS16K | _PAGE_SH | _PAGE_DIRTY | \ + _PAGE_PRESENT | _PAGE_NO_CACHE + mtspr SPRN_MD_RPN, r10/* Update TLB entry */ + + li r11, RPN_PATTERN + mtspr SPRN_DAR, r11 /* Tag DAR */ + +0: mfspr r10, SPRN_SPRG_SCRATCH0 + mfspr r11, SPRN_SPRG_SCRATCH1 + rfi + patch_site 0b, patch__dtlbmiss_exit_2 + +DTLBMissLinear: + mtcrr11 + /* Set 8M byte page and mark it valid */ + li r11, MD_PS8MEG | MD_SVALID + mtspr SPRN_MD_TWC, r11 + rlwinm r10, r10, 20, 0x0f80/* 8xx supports max 256Mb RAM */ + ori r10, r10, 0xf0 | MD_SPS16K | _PAGE_SH | _PAGE_DIRTY | \ + _PAGE_PRESENT + mtspr SPRN_MD_RPN, r10/* Update TLB entry */ + + li r11, RPN_PATTERN + mtspr SPRN_DAR, r11 /* Tag DAR */ + +0: mfspr r10, SPRN_SPRG_SCRATCH0 + mfspr r11, SPRN_SPRG_SCRATCH1 + rfi + patch_site 0b, patch__dtlbmiss_exit_3 + /* This is an instruction TLB error on the MPC8xx. This could be due * to many reasons, such as executing guarded memory or illegal instruction * addresses. There is nothing to do but handle a big time error fault. @@ -584,64 +638,6 @@ InstructionBreakpoint: . = 0x2000 -/* - * Bottom part of DataStoreTLBMiss handlers for IMMR area and linear RAM. - * not enough space in the DataStoreTLBMiss area. - */ -DTLBMissIMMR: - mtcrr11 - /* Set 512k byte guarded page and mark it valid */ - li r10, MD_PS512K | MD_GUARDED | MD_SVALID - mtspr SPRN_MD_TWC, r10 - mfspr r10, SPRN_IMMR /* Get current IMMR */ - rlwinm r10, r10, 0, 0xfff8 /* Get 512 kbytes boundary */ - ori r10, r10, 0xf0 | MD_SPS16K | _PAGE_SH | _PAGE_DIRTY | \ - _PAGE_PRESENT | _PAGE_NO_CACHE - mtspr SPRN_MD_RPN, r10/* Update TLB entry */ - - li r11, RPN_PATTERN - mtspr SPRN_DAR, r11 /* Tag DAR */ - -0: mfspr r10, SPRN_SPRG_SCRATCH0 - mfspr r11, SPRN_SPRG_SCRATCH1 - rfi - patch_site 0b, patch__dtlbmiss_exit_2 - -DTLBMissLinear: - mtcrr11 - /* Set 8M byte page and mark it valid */ - li r11, MD_PS8MEG | MD_SVALID - mtspr SPRN_MD_TWC, r11 - rlwinm r10, r10, 20, 0x0f80/* 8xx supports max 256Mb RAM */ - ori r10, r10, 0xf0 | MD_SPS16K | _PAGE_SH | _PAGE_DIRTY | \ - _PAGE_PRESENT - mtspr SPRN_MD_RPN, r10/* Update TLB entry */ - - li r11, RPN_PATTERN - mtspr SPRN_DAR, r11 /* Tag DAR */ - -0: mfspr r10, SPRN_SPRG_SCRATCH0 - mfspr r11, SPRN_SPRG_SCRATCH1 - rfi - patch_site 0b, patch__dtlbmiss_exit_3 - -#ifndef CONFIG_PIN_TLB_TEXT -ITLBMissLinear: - mtcrr11 - /* Set 8M byte page and mark it valid */ - li r11, MI_PS8MEG | MI_SVALID - mtspr SPRN_MI_TWC, r11 - rlwinm r10, r10, 20, 0x0f80/* 8xx supports max 256Mb RAM */ - ori r10, r10, 0xf0 | MI_SPS16K | _PAGE_SH | _PAGE_DIRTY | \ -
[PATCH v6 13/20] powerpc/8xx: don't use r12/SPRN_SPRG_SCRATCH2 in TLB Miss handlers
This patch reworks the TLB Miss handler in order to not use r12 register, hence avoiding having to save it into SPRN_SPRG_SCRATCH2. In the DAR Fixup code we can now use SPRN_M_TW, freeing SPRN_SPRG_SCRATCH2. Then SPRN_SPRG_SCRATCH2 may be used for something else in the future. Signed-off-by: Christophe Leroy --- arch/powerpc/kernel/head_8xx.S | 110 ++--- 1 file changed, 49 insertions(+), 61 deletions(-) diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S index 50e97027b507..d69c6e3d5cc1 100644 --- a/arch/powerpc/kernel/head_8xx.S +++ b/arch/powerpc/kernel/head_8xx.S @@ -302,91 +302,88 @@ SystemCall: */ #ifdef CONFIG_8xx_CPU15 -#define INVALIDATE_ADJACENT_PAGES_CPU15(tmp, addr) \ - additmp, addr, PAGE_SIZE; \ - tlbie tmp;\ - additmp, addr, -PAGE_SIZE; \ - tlbie tmp +#define INVALIDATE_ADJACENT_PAGES_CPU15(addr) \ + addiaddr, addr, PAGE_SIZE; \ + tlbie addr; \ + addiaddr, addr, -(PAGE_SIZE << 1); \ + tlbie addr; \ + addiaddr, addr, PAGE_SIZE #else -#define INVALIDATE_ADJACENT_PAGES_CPU15(tmp, addr) +#define INVALIDATE_ADJACENT_PAGES_CPU15(addr) #endif InstructionTLBMiss: mtspr SPRN_SPRG_SCRATCH0, r10 +#if defined(ITLB_MISS_KERNEL) || defined(CONFIG_SWAP) mtspr SPRN_SPRG_SCRATCH1, r11 -#ifdef ITLB_MISS_KERNEL - mtspr SPRN_SPRG_SCRATCH2, r12 #endif /* If we are faulting a kernel address, we have to use the * kernel page tables. */ mfspr r10, SPRN_SRR0 /* Get effective address of fault */ - INVALIDATE_ADJACENT_PAGES_CPU15(r11, r10) + INVALIDATE_ADJACENT_PAGES_CPU15(r10) mtspr SPRN_MD_EPN, r10 /* Only modules will cause ITLB Misses as we always * pin the first 8MB of kernel memory */ #ifdef ITLB_MISS_KERNEL - mfcrr12 + mfcrr11 #if defined(SIMPLE_KERNEL_ADDRESS) && defined(CONFIG_PIN_TLB_TEXT) - andis. r11, r10, 0x8000/* Address >= 0x8000 */ + cmpicr0, r10, 0 /* Address >= 0x8000 */ #else - rlwinm r11, r10, 16, 0xfff8 - cmpli cr0, r11, PAGE_OFFSET@h + rlwinm r10, r10, 16, 0xfff8 + cmpli cr0, r10, PAGE_OFFSET@h #ifndef CONFIG_PIN_TLB_TEXT /* It is assumed that kernel code fits into the first 8M page */ -0: cmpli cr7, r11, (PAGE_OFFSET + 0x080)@h +0: cmpli cr7, r10, (PAGE_OFFSET + 0x080)@h patch_site 0b, patch__itlbmiss_linmem_top #endif #endif #endif - mfspr r11, SPRN_M_TWB /* Get level 1 table */ + mfspr r10, SPRN_M_TWB /* Get level 1 table */ #ifdef ITLB_MISS_KERNEL #if defined(SIMPLE_KERNEL_ADDRESS) && defined(CONFIG_PIN_TLB_TEXT) - beq+3f + bge+3f #else blt+3f #endif #ifndef CONFIG_PIN_TLB_TEXT blt cr7, ITLBMissLinear #endif - rlwinm r11, r11, 0, 20, 31 - orisr11, r11, (swapper_pg_dir - PAGE_OFFSET)@ha + rlwinm r10, r10, 0, 20, 31 + orisr10, r10, (swapper_pg_dir - PAGE_OFFSET)@ha 3: #endif - lwz r11, (swapper_pg_dir-PAGE_OFFSET)@l(r11)/* Get the level 1 entry */ + lwz r10, (swapper_pg_dir-PAGE_OFFSET)@l(r10)/* Get level 1 entry */ + mtspr SPRN_MI_TWC, r10/* Set segment attributes */ - mtspr SPRN_MD_TWC, r11 + mtspr SPRN_MD_TWC, r10 mfspr r10, SPRN_MD_TWC lwz r10, 0(r10) /* Get the pte */ #ifdef ITLB_MISS_KERNEL - mtcrr12 + mtcrr11 #endif - /* Load the MI_TWC with the attributes for this "segment." */ - mtspr SPRN_MI_TWC, r11/* Set segment attributes */ - #ifdef CONFIG_SWAP rlwinm r11, r10, 32-5, _PAGE_PRESENT and r11, r11, r10 rlwimi r10, r11, 0, _PAGE_PRESENT #endif - li r11, RPN_PATTERN | 0x200 /* The Linux PTE won't go exactly into the MMU TLB. * Software indicator bits 20 and 23 must be clear. * Software indicator bits 22, 24, 25, 26, and 27 must be * set. All other Linux PTE bits control the behavior * of the MMU. */ - rlwimi r11, r10, 4, 0x0400 /* Copy _PAGE_EXEC into bit 21 */ - rlwimi r10, r11, 0, 0x0ff0 /* Set 22, 24-27, clear 20,23 */ + rlwimi r10, r10, 0, 0x0f00 /* Clear bits 20-23 */ + rlwimi r10, r10, 4, 0x0400 /* Copy _PAGE_EXEC into bit 21 */ + ori r10, r10, RPN_PATTERN | 0x200 /* Set 22 and 24-27 */ mtspr SPRN_MI_RPN, r10/* Update TLB entry */ /* Restore registers */ 0: mfspr r10, SPRN_SPRG_SCRATCH0 +#if defined(ITLB_MISS_KERNEL) || defined(CONFIG_SWAP) mfspr r11, SPRN_SPRG_SCRATCH1 -#ifdef ITLB_MISS_KERNEL - mfspr r12, SPRN_SPRG_SCRATCH2 #endif rfi patch_site 0b,
[PATCH v6 12/20] powerpc/mm: Enable 512k hugepage support with HW assistance on the 8xx
For using 512k pages with hardware assistance, the PTEs have to be spread
every 128 bytes in the L2 table.
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/hugetlb.h | 4 +++-
arch/powerpc/mm/hugetlbpage.c | 13 +
arch/powerpc/mm/tlb_nohash.c | 3 +++
3 files changed, 19 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/include/asm/hugetlb.h
b/arch/powerpc/include/asm/hugetlb.h
index e13843556414..b22f164216ad 100644
--- a/arch/powerpc/include/asm/hugetlb.h
+++ b/arch/powerpc/include/asm/hugetlb.h
@@ -75,7 +75,9 @@ static inline pte_t *hugepte_offset(hugepd_t hpd, unsigned
long addr,
unsigned long idx = 0;
pte_t *dir = hugepd_page(hpd);
-#ifndef CONFIG_PPC_FSL_BOOK3E
+#ifdef CONFIG_PPC_8xx
+ idx = (addr & ((1UL << pdshift) - 1)) >> PAGE_SHIFT;
+#elif !defined(CONFIG_PPC_FSL_BOOK3E)
idx = (addr & ((1UL << pdshift) - 1)) >> hugepd_shift(hpd);
#endif
diff --git a/arch/powerpc/mm/hugetlbpage.c b/arch/powerpc/mm/hugetlbpage.c
index d56d92783295..75856a5b476b 100644
--- a/arch/powerpc/mm/hugetlbpage.c
+++ b/arch/powerpc/mm/hugetlbpage.c
@@ -67,7 +67,11 @@ static int __hugepte_alloc(struct mm_struct *mm, hugepd_t
*hpdp,
cachep = PGT_CACHE(PTE_T_ORDER);
num_hugepd = 1 << (pshift - pdshift);
} else {
+#ifdef CONFIG_PPC_8xx
+ cachep = PGT_CACHE(PTE_SHIFT);
+#else
cachep = PGT_CACHE(pdshift - pshift);
+#endif
num_hugepd = 1;
}
@@ -333,8 +337,13 @@ static void free_hugepd_range(struct mmu_gather *tlb,
hugepd_t *hpdp, int pdshif
if (shift >= pdshift)
hugepd_free(tlb, hugepte);
else
+#ifdef CONFIG_PPC_8xx
+ pgtable_free_tlb(tlb, hugepte,
+get_hugepd_cache_index(PTE_SHIFT));
+#else
pgtable_free_tlb(tlb, hugepte,
get_hugepd_cache_index(pdshift - shift));
+#endif
}
static void hugetlb_free_pmd_range(struct mmu_gather *tlb, pud_t *pud,
@@ -702,7 +711,11 @@ static int __init hugetlbpage_init(void)
* use pgt cache for hugepd.
*/
if (pdshift > shift)
+#ifdef CONFIG_PPC_8xx
+ pgtable_cache_add(PTE_SHIFT);
+#else
pgtable_cache_add(pdshift - shift);
+#endif
#if defined(CONFIG_PPC_FSL_BOOK3E) || defined(CONFIG_PPC_8xx)
else
pgtable_cache_add(PTE_T_ORDER);
diff --git a/arch/powerpc/mm/tlb_nohash.c b/arch/powerpc/mm/tlb_nohash.c
index 8ad7aab150b7..ae5d568e267f 100644
--- a/arch/powerpc/mm/tlb_nohash.c
+++ b/arch/powerpc/mm/tlb_nohash.c
@@ -97,6 +97,9 @@ struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT] = {
.shift = 14,
},
#endif
+ [MMU_PAGE_512K] = {
+ .shift = 19,
+ },
[MMU_PAGE_8M] = {
.shift = 23,
},
--
2.13.3
[PATCH v6 11/20] powerpc/mm: Use hardware assistance in TLB handlers on the 8xx
Today, on the 8xx the TLB handlers do SW tablewalk by doing all the calculation in ASM, in order to match with the Linux page table structure. The 8xx offers hardware assistance which allows significant size reduction of the TLB handlers, hence also reduces the time spent in the handlers. However, using this HW assistance implies some constraints on the page table structure: - Regardless of the main page size used (4k or 16k), the level 1 table (PGD) contains 1024 entries and each PGD entry covers a 4Mbytes area which is managed by a level 2 table (PTE) containing also 1024 entries each describing a 4k page. - 16k pages require 4 identifical entries in the L2 table - 512k pages PTE have to be spread every 128 bytes in the L2 table - 8M pages PTE are at the address pointed by the L1 entry and each 8M page require 2 identical entries in the PGD. This patch modifies the TLB handlers to use HW assistance for 4K PAGES. Before that patch, the mean time spent in TLB miss handlers is: - ITLB miss: 80 ticks - DTLB miss: 62 ticks After that patch, the mean time spent in TLB miss handlers is: - ITLB miss: 72 ticks - DTLB miss: 54 ticks So the improvement is 10% for ITLB and 13% for DTLB misses Signed-off-by: Christophe Leroy --- arch/powerpc/kernel/head_8xx.S | 97 +- arch/powerpc/mm/8xx_mmu.c | 4 +- 2 files changed, 32 insertions(+), 69 deletions(-) diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S index 9b31721b522c..50e97027b507 100644 --- a/arch/powerpc/kernel/head_8xx.S +++ b/arch/powerpc/kernel/head_8xx.S @@ -292,7 +292,7 @@ SystemCall: . = 0x1100 /* * For the MPC8xx, this is a software tablewalk to load the instruction - * TLB. The task switch loads the M_TW register with the pointer to the first + * TLB. The task switch loads the M_TWB register with the pointer to the first * level table. * If we discover there is no second level table (value is zero) or if there * is an invalid pte, we load that into the TLB, which causes another fault @@ -314,7 +314,7 @@ SystemCall: InstructionTLBMiss: mtspr SPRN_SPRG_SCRATCH0, r10 mtspr SPRN_SPRG_SCRATCH1, r11 -#if defined(ITLB_MISS_KERNEL) || defined(CONFIG_HUGETLB_PAGE) +#ifdef ITLB_MISS_KERNEL mtspr SPRN_SPRG_SCRATCH2, r12 #endif @@ -323,12 +323,11 @@ InstructionTLBMiss: */ mfspr r10, SPRN_SRR0 /* Get effective address of fault */ INVALIDATE_ADJACENT_PAGES_CPU15(r11, r10) + mtspr SPRN_MD_EPN, r10 /* Only modules will cause ITLB Misses as we always * pin the first 8MB of kernel memory */ -#if defined(ITLB_MISS_KERNEL) || defined(CONFIG_HUGETLB_PAGE) - mfcrr12 -#endif #ifdef ITLB_MISS_KERNEL + mfcrr12 #if defined(SIMPLE_KERNEL_ADDRESS) && defined(CONFIG_PIN_TLB_TEXT) andis. r11, r10, 0x8000/* Address >= 0x8000 */ #else @@ -341,7 +340,7 @@ InstructionTLBMiss: #endif #endif #endif - mfspr r11, SPRN_M_TW /* Get level 1 table */ + mfspr r11, SPRN_M_TWB /* Get level 1 table */ #ifdef ITLB_MISS_KERNEL #if defined(SIMPLE_KERNEL_ADDRESS) && defined(CONFIG_PIN_TLB_TEXT) beq+3f @@ -351,23 +350,17 @@ InstructionTLBMiss: #ifndef CONFIG_PIN_TLB_TEXT blt cr7, ITLBMissLinear #endif - lis r11, (swapper_pg_dir-PAGE_OFFSET)@ha + rlwinm r11, r11, 0, 20, 31 + orisr11, r11, (swapper_pg_dir - PAGE_OFFSET)@ha 3: #endif - /* Insert level 1 index */ - rlwimi r11, r10, 32 - ((PAGE_SHIFT - 2) << 1), (PAGE_SHIFT - 2) << 1, 29 lwz r11, (swapper_pg_dir-PAGE_OFFSET)@l(r11)/* Get the level 1 entry */ - /* Extract level 2 index */ - rlwinm r10, r10, 32 - (PAGE_SHIFT - 2), 32 - PAGE_SHIFT, 29 -#ifdef CONFIG_HUGETLB_PAGE - mtcrr11 - bt- 28, 10f /* bit 28 = Large page (8M) */ -#endif - rlwimi r10, r11, 0, 0, 32 - PAGE_SHIFT - 1 /* Add level 2 base */ + mtspr SPRN_MD_TWC, r11 + mfspr r10, SPRN_MD_TWC lwz r10, 0(r10) /* Get the pte */ -4: -#if defined(ITLB_MISS_KERNEL) || defined(CONFIG_HUGETLB_PAGE) + +#ifdef ITLB_MISS_KERNEL mtcrr12 #endif /* Load the MI_TWC with the attributes for this "segment." */ @@ -392,7 +385,7 @@ InstructionTLBMiss: /* Restore registers */ 0: mfspr r10, SPRN_SPRG_SCRATCH0 mfspr r11, SPRN_SPRG_SCRATCH1 -#if defined(ITLB_MISS_KERNEL) || defined(CONFIG_HUGETLB_PAGE) +#ifdef ITLB_MISS_KERNEL mfspr r12, SPRN_SPRG_SCRATCH2 #endif rfi @@ -405,20 +398,12 @@ InstructionTLBMiss: stw r10, (itlb_miss_counter - PAGE_OFFSET)@l(0) mfspr r10, SPRN_SPRG_SCRATCH0 mfspr r11, SPRN_SPRG_SCRATCH1 -#if defined(ITLB_MISS_KERNEL) || defined(CONFIG_HUGETLB_PAGE) +#ifdef ITLB_MISS_KERNEL mfspr r12, SPRN_SPRG_SCRATCH2 #endif rfi #endif -#ifdef CONFIG_HUGETLB_PAGE -10:
[PATCH v6 10/20] powerpc/8xx: Temporarily disable 16k pages and 512k hugepages
In preparation of making use of hardware assistance in TLB handlers,
this patch temporarily disables 16K pages and 512K pages. The reason
is that when using HW assistance in 4K pages mode, the linux model
fit with the HW model for 4K pages and 8M pages.
However for 16K pages and 512K mode some additional work is needed
to get linux model fit with HW model.
Therefore the 4K pages mode will be implemented first and without
support for 512k hugepages. Then the 512k hugepages will be brought
back. And the 16K pages will be implemented in further steps.
Signed-off-by: Christophe Leroy
---
arch/powerpc/Kconfig | 2 +-
arch/powerpc/kernel/head_8xx.S | 36
arch/powerpc/mm/tlb_nohash.c | 3 ---
3 files changed, 1 insertion(+), 40 deletions(-)
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 3d008115fe18..287befcf37ab 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -690,7 +690,7 @@ config PPC_4K_PAGES
config PPC_16K_PAGES
bool "16k page size"
- depends on 44x || PPC_8xx
+ depends on 44x
config PPC_64K_PAGES
bool "64k page size"
diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
index c203defe49a4..9b31721b522c 100644
--- a/arch/powerpc/kernel/head_8xx.S
+++ b/arch/powerpc/kernel/head_8xx.S
@@ -363,7 +363,6 @@ InstructionTLBMiss:
#ifdef CONFIG_HUGETLB_PAGE
mtcrr11
bt- 28, 10f /* bit 28 = Large page (8M) */
- bt- 29, 20f /* bit 29 = Large page (8M or 512k) */
#endif
rlwimi r10, r11, 0, 0, 32 - PAGE_SHIFT - 1 /* Add level 2 base */
lwz r10, 0(r10) /* Get the pte */
@@ -414,23 +413,8 @@ InstructionTLBMiss:
#ifdef CONFIG_HUGETLB_PAGE
10:/* 8M pages */
-#ifdef CONFIG_PPC_16K_PAGES
- /* Extract level 2 index */
- rlwinm r10, r10, 32 - (PAGE_SHIFT_8M - PAGE_SHIFT), 32 + PAGE_SHIFT_8M
- (PAGE_SHIFT << 1), 29
- /* Add level 2 base */
- rlwimi r10, r11, 0, 0, 32 + PAGE_SHIFT_8M - (PAGE_SHIFT << 1) - 1
-#else
/* Level 2 base */
rlwinm r10, r11, 0, ~HUGEPD_SHIFT_MASK
-#endif
- lwz r10, 0(r10) /* Get the pte */
- b 4b
-
-20:/* 512k pages */
- /* Extract level 2 index */
- rlwinm r10, r10, 32 - (PAGE_SHIFT_512K - PAGE_SHIFT), 32 +
PAGE_SHIFT_512K - (PAGE_SHIFT << 1), 29
- /* Add level 2 base */
- rlwimi r10, r11, 0, 0, 32 + PAGE_SHIFT_512K - (PAGE_SHIFT << 1) - 1
lwz r10, 0(r10) /* Get the pte */
b 4b
#endif
@@ -475,7 +459,6 @@ DataStoreTLBMiss:
#ifdef CONFIG_HUGETLB_PAGE
mtcrr11
bt- 28, 10f /* bit 28 = Large page (8M) */
- bt- 29, 20f /* bit 29 = Large page (8M or 512k) */
#endif
rlwimi r10, r11, 0, 0, 32 - PAGE_SHIFT - 1 /* Add level 2 base */
lwz r10, 0(r10) /* Get the pte */
@@ -537,22 +520,8 @@ DataStoreTLBMiss:
#ifdef CONFIG_HUGETLB_PAGE
10:/* 8M pages */
/* Extract level 2 index */
-#ifdef CONFIG_PPC_16K_PAGES
- rlwinm r10, r10, 32 - (PAGE_SHIFT_8M - PAGE_SHIFT), 32 + PAGE_SHIFT_8M
- (PAGE_SHIFT << 1), 29
- /* Add level 2 base */
- rlwimi r10, r11, 0, 0, 32 + PAGE_SHIFT_8M - (PAGE_SHIFT << 1) - 1
-#else
/* Level 2 base */
rlwinm r10, r11, 0, ~HUGEPD_SHIFT_MASK
-#endif
- lwz r10, 0(r10) /* Get the pte */
- b 4b
-
-20:/* 512k pages */
- /* Extract level 2 index */
- rlwinm r10, r10, 32 - (PAGE_SHIFT_512K - PAGE_SHIFT), 32 +
PAGE_SHIFT_512K - (PAGE_SHIFT << 1), 29
- /* Add level 2 base */
- rlwimi r10, r11, 0, 0, 32 + PAGE_SHIFT_512K - (PAGE_SHIFT << 1) - 1
lwz r10, 0(r10) /* Get the pte */
b 4b
#endif
@@ -773,12 +742,7 @@ FixupDAR:/* Entry point for dcbx workaround. */
/* concat physical page address(r11) and page offset(r10) */
200:
-#ifdef CONFIG_PPC_16K_PAGES
- rlwinm r11, r11, 0, 0, 32 + PAGE_SHIFT_8M - (PAGE_SHIFT << 1) - 1
- rlwimi r11, r10, 32 - (PAGE_SHIFT_8M - 2), 32 + PAGE_SHIFT_8M -
(PAGE_SHIFT << 1), 29
-#else
rlwinm r11, r10, 0, ~HUGEPD_SHIFT_MASK
-#endif
lwz r11, 0(r11) /* Get the pte */
/* concat physical page address(r11) and page offset(r10) */
rlwimi r11, r10, 0, 32 - PAGE_SHIFT_8M, 31
diff --git a/arch/powerpc/mm/tlb_nohash.c b/arch/powerpc/mm/tlb_nohash.c
index ae5d568e267f..8ad7aab150b7 100644
--- a/arch/powerpc/mm/tlb_nohash.c
+++ b/arch/powerpc/mm/tlb_nohash.c
@@ -97,9 +97,6 @@ struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT] = {
.shift = 14,
},
#endif
- [MMU_PAGE_512K] = {
- .shift = 19,
- },
[MMU_PAGE_8M] = {
.shift = 23,
},
--
2.13.3
[PATCH v6 09/20] powerpc/8xx: Move SW perf counters in first 32kb of memory
In order to simplify time critical exceptions handling 8xx specific SW perf counters, this patch moves the counters into the beginning of memory. This is possible because .text is readable and the counters are never modified outside of the handlers. By doing this, we avoid having to set a second register with the upper part of the address of the counters. Signed-off-by: Christophe Leroy --- arch/powerpc/kernel/head_8xx.S | 58 -- 1 file changed, 28 insertions(+), 30 deletions(-) diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S index 3b67b9533c82..c203defe49a4 100644 --- a/arch/powerpc/kernel/head_8xx.S +++ b/arch/powerpc/kernel/head_8xx.S @@ -106,6 +106,23 @@ turn_on_mmu: mtspr SPRN_SRR0,r0 rfi /* enables MMU */ + +#ifdef CONFIG_PERF_EVENTS + .align 4 + + .globl itlb_miss_counter +itlb_miss_counter: + .space 4 + + .globl dtlb_miss_counter +dtlb_miss_counter: + .space 4 + + .globl instruction_counter +instruction_counter: + .space 4 +#endif + /* * Exception entry code. This code runs with address translation * turned off, i.e. using physical addresses. @@ -384,17 +401,16 @@ InstructionTLBMiss: #ifdef CONFIG_PERF_EVENTS patch_site 0f, patch__itlbmiss_perf -0: lis r10, (itlb_miss_counter - PAGE_OFFSET)@ha - lwz r11, (itlb_miss_counter - PAGE_OFFSET)@l(r10) - addir11, r11, 1 - stw r11, (itlb_miss_counter - PAGE_OFFSET)@l(r10) -#endif +0: lwz r10, (itlb_miss_counter - PAGE_OFFSET)@l(0) + addir10, r10, 1 + stw r10, (itlb_miss_counter - PAGE_OFFSET)@l(0) mfspr r10, SPRN_SPRG_SCRATCH0 mfspr r11, SPRN_SPRG_SCRATCH1 #if defined(ITLB_MISS_KERNEL) || defined(CONFIG_HUGETLB_PAGE) mfspr r12, SPRN_SPRG_SCRATCH2 #endif rfi +#endif #ifdef CONFIG_HUGETLB_PAGE 10:/* 8M pages */ @@ -509,15 +525,14 @@ DataStoreTLBMiss: #ifdef CONFIG_PERF_EVENTS patch_site 0f, patch__dtlbmiss_perf -0: lis r10, (dtlb_miss_counter - PAGE_OFFSET)@ha - lwz r11, (dtlb_miss_counter - PAGE_OFFSET)@l(r10) - addir11, r11, 1 - stw r11, (dtlb_miss_counter - PAGE_OFFSET)@l(r10) -#endif +0: lwz r10, (dtlb_miss_counter - PAGE_OFFSET)@l(0) + addir10, r10, 1 + stw r10, (dtlb_miss_counter - PAGE_OFFSET)@l(0) mfspr r10, SPRN_SPRG_SCRATCH0 mfspr r11, SPRN_SPRG_SCRATCH1 mfspr r12, SPRN_SPRG_SCRATCH2 rfi +#endif #ifdef CONFIG_HUGETLB_PAGE 10:/* 8M pages */ @@ -625,16 +640,13 @@ DataBreakpoint: . = 0x1d00 InstructionBreakpoint: mtspr SPRN_SPRG_SCRATCH0, r10 - mtspr SPRN_SPRG_SCRATCH1, r11 - lis r10, (instruction_counter - PAGE_OFFSET)@ha - lwz r11, (instruction_counter - PAGE_OFFSET)@l(r10) - addir11, r11, -1 - stw r11, (instruction_counter - PAGE_OFFSET)@l(r10) + lwz r10, (instruction_counter - PAGE_OFFSET)@l(0) + addir10, r10, -1 + stw r10, (instruction_counter - PAGE_OFFSET)@l(0) lis r10, 0x ori r10, r10, 0x01 mtspr SPRN_COUNTA, r10 mfspr r10, SPRN_SPRG_SCRATCH0 - mfspr r11, SPRN_SPRG_SCRATCH1 rfi #else EXCEPTION(0x1d00, Trap_1d, unknown_exception, EXC_XFER_EE) @@ -1065,17 +1077,3 @@ swapper_pg_dir: */ abatron_pteptrs: .space 8 - -#ifdef CONFIG_PERF_EVENTS - .globl itlb_miss_counter -itlb_miss_counter: - .space 4 - - .globl dtlb_miss_counter -dtlb_miss_counter: - .space 4 - - .globl instruction_counter -instruction_counter: - .space 4 -#endif -- 2.13.3
[PATCH v6 08/20] powerpc/8xx: Use patch_site for perf counters setup
The 8xx TLB miss routines are patched when (de)activating perf counters. This patch uses the new patch_site functionality in order to get a better code readability and avoid a label mess when dumping the code with 'objdump -d' Signed-off-by: Christophe Leroy --- arch/powerpc/include/asm/nohash/32/mmu-8xx.h | 4 arch/powerpc/kernel/head_8xx.S | 33 arch/powerpc/perf/8xx-pmu.c | 27 ++- 3 files changed, 35 insertions(+), 29 deletions(-) diff --git a/arch/powerpc/include/asm/nohash/32/mmu-8xx.h b/arch/powerpc/include/asm/nohash/32/mmu-8xx.h index 3a15d6647d47..fa05aa566ece 100644 --- a/arch/powerpc/include/asm/nohash/32/mmu-8xx.h +++ b/arch/powerpc/include/asm/nohash/32/mmu-8xx.h @@ -234,6 +234,10 @@ extern s32 patch__itlbmiss_linmem_top; extern s32 patch__dtlbmiss_linmem_top, patch__dtlbmiss_immr_jmp; extern s32 patch__fixupdar_linmem_top; +extern s32 patch__itlbmiss_exit_1, patch__itlbmiss_exit_2; +extern s32 patch__dtlbmiss_exit_1, patch__dtlbmiss_exit_2, patch__dtlbmiss_exit_3; +extern s32 patch__itlbmiss_perf, patch__dtlbmiss_perf; + #endif /* !__ASSEMBLY__ */ #if defined(CONFIG_PPC_4K_PAGES) diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S index 0425571a533d..3b67b9533c82 100644 --- a/arch/powerpc/kernel/head_8xx.S +++ b/arch/powerpc/kernel/head_8xx.S @@ -374,16 +374,17 @@ InstructionTLBMiss: mtspr SPRN_MI_RPN, r10/* Update TLB entry */ /* Restore registers */ -_ENTRY(itlb_miss_exit_1) - mfspr r10, SPRN_SPRG_SCRATCH0 +0: mfspr r10, SPRN_SPRG_SCRATCH0 mfspr r11, SPRN_SPRG_SCRATCH1 #if defined(ITLB_MISS_KERNEL) || defined(CONFIG_HUGETLB_PAGE) mfspr r12, SPRN_SPRG_SCRATCH2 #endif rfi + patch_site 0b, patch__itlbmiss_exit_1 + #ifdef CONFIG_PERF_EVENTS -_ENTRY(itlb_miss_perf) - lis r10, (itlb_miss_counter - PAGE_OFFSET)@ha + patch_site 0f, patch__itlbmiss_perf +0: lis r10, (itlb_miss_counter - PAGE_OFFSET)@ha lwz r11, (itlb_miss_counter - PAGE_OFFSET)@l(r10) addir11, r11, 1 stw r11, (itlb_miss_counter - PAGE_OFFSET)@l(r10) @@ -499,14 +500,16 @@ DataStoreTLBMiss: /* Restore registers */ mtspr SPRN_DAR, r11 /* Tag DAR */ -_ENTRY(dtlb_miss_exit_1) - mfspr r10, SPRN_SPRG_SCRATCH0 + +0: mfspr r10, SPRN_SPRG_SCRATCH0 mfspr r11, SPRN_SPRG_SCRATCH1 mfspr r12, SPRN_SPRG_SCRATCH2 rfi + patch_site 0b, patch__dtlbmiss_exit_1 + #ifdef CONFIG_PERF_EVENTS -_ENTRY(dtlb_miss_perf) - lis r10, (dtlb_miss_counter - PAGE_OFFSET)@ha + patch_site 0f, patch__dtlbmiss_perf +0: lis r10, (dtlb_miss_counter - PAGE_OFFSET)@ha lwz r11, (dtlb_miss_counter - PAGE_OFFSET)@l(r10) addir11, r11, 1 stw r11, (dtlb_miss_counter - PAGE_OFFSET)@l(r10) @@ -658,11 +661,12 @@ DTLBMissIMMR: li r11, RPN_PATTERN mtspr SPRN_DAR, r11 /* Tag DAR */ -_ENTRY(dtlb_miss_exit_2) - mfspr r10, SPRN_SPRG_SCRATCH0 + +0: mfspr r10, SPRN_SPRG_SCRATCH0 mfspr r11, SPRN_SPRG_SCRATCH1 mfspr r12, SPRN_SPRG_SCRATCH2 rfi + patch_site 0b, patch__dtlbmiss_exit_2 DTLBMissLinear: mtcrr12 @@ -676,11 +680,12 @@ DTLBMissLinear: li r11, RPN_PATTERN mtspr SPRN_DAR, r11 /* Tag DAR */ -_ENTRY(dtlb_miss_exit_3) - mfspr r10, SPRN_SPRG_SCRATCH0 + +0: mfspr r10, SPRN_SPRG_SCRATCH0 mfspr r11, SPRN_SPRG_SCRATCH1 mfspr r12, SPRN_SPRG_SCRATCH2 rfi + patch_site 0b, patch__dtlbmiss_exit_3 #ifndef CONFIG_PIN_TLB_TEXT ITLBMissLinear: @@ -693,11 +698,11 @@ ITLBMissLinear: _PAGE_PRESENT mtspr SPRN_MI_RPN, r10/* Update TLB entry */ -_ENTRY(itlb_miss_exit_2) - mfspr r10, SPRN_SPRG_SCRATCH0 +0: mfspr r10, SPRN_SPRG_SCRATCH0 mfspr r11, SPRN_SPRG_SCRATCH1 mfspr r12, SPRN_SPRG_SCRATCH2 rfi + patch_site 0b, patch__itlbmiss_exit_2 #endif /* This is the procedure to calculate the data EA for buggy dcbx,dcbi instructions diff --git a/arch/powerpc/perf/8xx-pmu.c b/arch/powerpc/perf/8xx-pmu.c index 6c0020d1c561..808f1873de61 100644 --- a/arch/powerpc/perf/8xx-pmu.c +++ b/arch/powerpc/perf/8xx-pmu.c @@ -31,9 +31,6 @@ extern unsigned long itlb_miss_counter, dtlb_miss_counter; extern atomic_t instruction_counter; -extern unsigned int itlb_miss_perf, dtlb_miss_perf; -extern unsigned int itlb_miss_exit_1, itlb_miss_exit_2; -extern unsigned int dtlb_miss_exit_1, dtlb_miss_exit_2, dtlb_miss_exit_3; static atomic_t insn_ctr_ref; static atomic_t itlb_miss_ref; @@ -103,22 +100,22 @@ static int mpc8xx_pmu_add(struct perf_event *event, int flags) break; case PERF_8xx_ID_ITLB_LOAD_MISS:
[PATCH v6 07/20] powerpc/8xx: Use patch_site for memory setup patching
The 8xx TLB miss routines are patched at startup at several places.
This patch uses the new patch_site functionality in order
to get a better code readability and avoid a label mess when
dumping the code with 'objdump -d'
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/nohash/32/mmu-8xx.h | 5 +
arch/powerpc/kernel/head_8xx.S | 19 +++
arch/powerpc/mm/8xx_mmu.c| 23 +++
3 files changed, 23 insertions(+), 24 deletions(-)
diff --git a/arch/powerpc/include/asm/nohash/32/mmu-8xx.h
b/arch/powerpc/include/asm/nohash/32/mmu-8xx.h
index 193f53116c7a..3a15d6647d47 100644
--- a/arch/powerpc/include/asm/nohash/32/mmu-8xx.h
+++ b/arch/powerpc/include/asm/nohash/32/mmu-8xx.h
@@ -229,6 +229,11 @@ static inline unsigned int mmu_psize_to_shift(unsigned int
mmu_psize)
BUG();
}
+/* patch sites */
+extern s32 patch__itlbmiss_linmem_top;
+extern s32 patch__dtlbmiss_linmem_top, patch__dtlbmiss_immr_jmp;
+extern s32 patch__fixupdar_linmem_top;
+
#endif /* !__ASSEMBLY__ */
#if defined(CONFIG_PPC_4K_PAGES)
diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
index 12c92a483fb1..0425571a533d 100644
--- a/arch/powerpc/kernel/head_8xx.S
+++ b/arch/powerpc/kernel/head_8xx.S
@@ -31,6 +31,7 @@
#include
#include
#include
+#include
#if CONFIG_TASK_SIZE <= 0x8000 && CONFIG_PAGE_OFFSET >= 0x8000
/* By simply checking Address >= 0x8000, we know if its a kernel address */
@@ -318,8 +319,8 @@ InstructionTLBMiss:
cmpli cr0, r11, PAGE_OFFSET@h
#ifndef CONFIG_PIN_TLB_TEXT
/* It is assumed that kernel code fits into the first 8M page */
-_ENTRY(ITLBMiss_cmp)
- cmpli cr7, r11, (PAGE_OFFSET + 0x080)@h
+0: cmpli cr7, r11, (PAGE_OFFSET + 0x080)@h
+ patch_site 0b, patch__itlbmiss_linmem_top
#endif
#endif
#endif
@@ -436,11 +437,11 @@ DataStoreTLBMiss:
#ifndef CONFIG_PIN_TLB_IMMR
cmpli cr0, r11, VIRT_IMMR_BASE@h
#endif
-_ENTRY(DTLBMiss_cmp)
- cmpli cr7, r11, (PAGE_OFFSET + 0x180)@h
+0: cmpli cr7, r11, (PAGE_OFFSET + 0x180)@h
+ patch_site 0b, patch__dtlbmiss_linmem_top
#ifndef CONFIG_PIN_TLB_IMMR
-_ENTRY(DTLBMiss_jmp)
- beq-DTLBMissIMMR
+0: beq-DTLBMissIMMR
+ patch_site 0b, patch__dtlbmiss_immr_jmp
#endif
blt cr7, DTLBMissLinear
lis r11, (swapper_pg_dir-PAGE_OFFSET)@ha
@@ -714,8 +715,10 @@ FixupDAR:/* Entry point for dcbx workaround. */
mfspr r11, SPRN_M_TW /* Get level 1 table */
blt+3f
rlwinm r11, r10, 16, 0xfff8
-_ENTRY(FixupDAR_cmp)
- cmpli cr7, r11, (PAGE_OFFSET + 0x180)@h
+
+0: cmpli cr7, r11, (PAGE_OFFSET + 0x180)@h
+ patch_site 0b, patch__fixupdar_linmem_top
+
/* create physical page address from effective address */
tophys(r11, r10)
blt-cr7, 201f
diff --git a/arch/powerpc/mm/8xx_mmu.c b/arch/powerpc/mm/8xx_mmu.c
index fee599cf3bc3..d39f3af03221 100644
--- a/arch/powerpc/mm/8xx_mmu.c
+++ b/arch/powerpc/mm/8xx_mmu.c
@@ -97,22 +97,13 @@ static void __init mmu_mapin_immr(void)
map_kernel_page(v + offset, p + offset, PAGE_KERNEL_NCG);
}
-/* Address of instructions to patch */
-#ifndef CONFIG_PIN_TLB_IMMR
-extern unsigned int DTLBMiss_jmp;
-#endif
-extern unsigned int DTLBMiss_cmp, FixupDAR_cmp;
-#ifndef CONFIG_PIN_TLB_TEXT
-extern unsigned int ITLBMiss_cmp;
-#endif
-
-static void __init mmu_patch_cmp_limit(unsigned int *addr, unsigned long
mapped)
+static void __init mmu_patch_cmp_limit(s32 *site, unsigned long mapped)
{
- unsigned int instr = *addr;
+ unsigned int instr = *(unsigned int *)site_addr(site);
instr &= 0x;
instr |= (unsigned long)__va(mapped) >> 16;
- patch_instruction(addr, instr);
+ patch_instruction_site(site, instr);
}
unsigned long __init mmu_mapin_ram(unsigned long top)
@@ -123,17 +114,17 @@ unsigned long __init mmu_mapin_ram(unsigned long top)
mapped = 0;
mmu_mapin_immr();
#ifndef CONFIG_PIN_TLB_IMMR
- patch_instruction(_jmp, PPC_INST_NOP);
+ patch_instruction_site(__dtlbmiss_immr_jmp, PPC_INST_NOP);
#endif
#ifndef CONFIG_PIN_TLB_TEXT
- mmu_patch_cmp_limit(_cmp, 0);
+ mmu_patch_cmp_limit(__itlbmiss_linmem_top, 0);
#endif
} else {
mapped = top & ~(LARGE_PAGE_SIZE_8M - 1);
}
- mmu_patch_cmp_limit(_cmp, mapped);
- mmu_patch_cmp_limit(_cmp, mapped);
+ mmu_patch_cmp_limit(__dtlbmiss_linmem_top, mapped);
+ mmu_patch_cmp_limit(__fixupdar_linmem_top, mapped);
/* If the size of RAM is not an exact power of two, we may not
* have covered RAM in its entirety with 8 MiB
--
2.13.3
[PATCH v6 06/20] powerpc/code-patching: add a helper to get the address of a patch_site
This patch adds a helper to get the address of a patch_site
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/code-patching.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/powerpc/include/asm/code-patching.h
b/arch/powerpc/include/asm/code-patching.h
index 31733a95bbd0..bca48cc1b6ad 100644
--- a/arch/powerpc/include/asm/code-patching.h
+++ b/arch/powerpc/include/asm/code-patching.h
@@ -36,6 +36,11 @@ int raw_patch_instruction(unsigned int *addr, unsigned int
instr);
int patch_instruction_site(s32 *addr, unsigned int instr);
int patch_branch_site(s32 *site, unsigned long target, int flags);
+static inline unsigned long site_addr(s32 *site)
+{
+ return (unsigned long)site + *site;
+}
+
int instr_is_relative_branch(unsigned int instr);
int instr_is_relative_link_branch(unsigned int instr);
int instr_is_branch_to_addr(const unsigned int *instr, unsigned long addr);
--
2.13.3
[PATCH v6 05/20] powerpc/mm: Move pgtable_t into platform headers
This patch move pgtable_t into platform headers.
It gets rid of the CONFIG_PPC_64K_PAGES case for PPC64
as nohash/64 doesn't support CONFIG_PPC_64K_PAGES.
Reviewed-by: Aneesh Kumar K.V
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/book3s/32/mmu-hash.h | 2 ++
arch/powerpc/include/asm/book3s/64/mmu.h | 9 +
arch/powerpc/include/asm/nohash/32/mmu.h | 4
arch/powerpc/include/asm/nohash/64/mmu.h | 4
arch/powerpc/include/asm/page.h | 14 --
5 files changed, 19 insertions(+), 14 deletions(-)
diff --git a/arch/powerpc/include/asm/book3s/32/mmu-hash.h
b/arch/powerpc/include/asm/book3s/32/mmu-hash.h
index e38c91388c40..5bd26c218b94 100644
--- a/arch/powerpc/include/asm/book3s/32/mmu-hash.h
+++ b/arch/powerpc/include/asm/book3s/32/mmu-hash.h
@@ -42,6 +42,8 @@ struct ppc_bat {
u32 batu;
u32 batl;
};
+
+typedef struct page *pgtable_t;
#endif /* !__ASSEMBLY__ */
/*
diff --git a/arch/powerpc/include/asm/book3s/64/mmu.h
b/arch/powerpc/include/asm/book3s/64/mmu.h
index 6328857f259f..1ceee000c18d 100644
--- a/arch/powerpc/include/asm/book3s/64/mmu.h
+++ b/arch/powerpc/include/asm/book3s/64/mmu.h
@@ -2,6 +2,8 @@
#ifndef _ASM_POWERPC_BOOK3S_64_MMU_H_
#define _ASM_POWERPC_BOOK3S_64_MMU_H_
+#include
+
#ifndef __ASSEMBLY__
/*
* Page size definition
@@ -24,6 +26,13 @@ struct mmu_psize_def {
};
extern struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
+/*
+ * For BOOK3s 64 with 4k and 64K linux page size
+ * we want to use pointers, because the page table
+ * actually store pfn
+ */
+typedef pte_t *pgtable_t;
+
#endif /* __ASSEMBLY__ */
/* 64-bit classic hash table MMU */
diff --git a/arch/powerpc/include/asm/nohash/32/mmu.h
b/arch/powerpc/include/asm/nohash/32/mmu.h
index af0e8b54876a..f61f933a4cd8 100644
--- a/arch/powerpc/include/asm/nohash/32/mmu.h
+++ b/arch/powerpc/include/asm/nohash/32/mmu.h
@@ -16,4 +16,8 @@
#include
#endif
+#ifndef __ASSEMBLY__
+typedef struct page *pgtable_t;
+#endif
+
#endif /* _ASM_POWERPC_NOHASH_32_MMU_H_ */
diff --git a/arch/powerpc/include/asm/nohash/64/mmu.h
b/arch/powerpc/include/asm/nohash/64/mmu.h
index 87871d027b75..e6585480dfc4 100644
--- a/arch/powerpc/include/asm/nohash/64/mmu.h
+++ b/arch/powerpc/include/asm/nohash/64/mmu.h
@@ -5,4 +5,8 @@
/* Freescale Book-E software loaded TLB or Book-3e (ISA 2.06+) MMU */
#include
+#ifndef __ASSEMBLY__
+typedef struct page *pgtable_t;
+#endif
+
#endif /* _ASM_POWERPC_NOHASH_64_MMU_H_ */
diff --git a/arch/powerpc/include/asm/page.h b/arch/powerpc/include/asm/page.h
index f6a1265face2..ddfb4b965e5b 100644
--- a/arch/powerpc/include/asm/page.h
+++ b/arch/powerpc/include/asm/page.h
@@ -335,20 +335,6 @@ void arch_free_page(struct page *page, int order);
#endif
struct vm_area_struct;
-#ifdef CONFIG_PPC_BOOK3S_64
-/*
- * For BOOK3s 64 with 4k and 64K linux page size
- * we want to use pointers, because the page table
- * actually store pfn
- */
-typedef pte_t *pgtable_t;
-#else
-#if defined(CONFIG_PPC_64K_PAGES) && defined(CONFIG_PPC64)
-typedef pte_t *pgtable_t;
-#else
-typedef struct page *pgtable_t;
-#endif
-#endif
#include
#endif /* __ASSEMBLY__ */
--
2.13.3
[PATCH v6 04/20] powerpc/mm: move platform specific mmu-xxx.h in platform directories
The purpose of this patch is to move platform specific
mmu-xxx.h files in platform directories like pte-xxx.h files.
In the meantime this patch creates common nohash and
nohash/32 + nohash/64 mmu.h files for future common parts.
Reviewed-by: Aneesh Kumar K.V
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/mmu.h | 14 ++
arch/powerpc/include/asm/{ => nohash/32}/mmu-40x.h | 0
arch/powerpc/include/asm/{ => nohash/32}/mmu-44x.h | 0
arch/powerpc/include/asm/{ => nohash/32}/mmu-8xx.h | 0
arch/powerpc/include/asm/nohash/32/mmu.h | 19 +++
arch/powerpc/include/asm/nohash/64/mmu.h | 8
arch/powerpc/include/asm/{ => nohash}/mmu-book3e.h | 0
arch/powerpc/include/asm/nohash/mmu.h | 11 +++
arch/powerpc/kernel/cpu_setup_fsl_booke.S | 2 +-
arch/powerpc/kvm/e500.h| 2 +-
10 files changed, 42 insertions(+), 14 deletions(-)
rename arch/powerpc/include/asm/{ => nohash/32}/mmu-40x.h (100%)
rename arch/powerpc/include/asm/{ => nohash/32}/mmu-44x.h (100%)
rename arch/powerpc/include/asm/{ => nohash/32}/mmu-8xx.h (100%)
create mode 100644 arch/powerpc/include/asm/nohash/32/mmu.h
create mode 100644 arch/powerpc/include/asm/nohash/64/mmu.h
rename arch/powerpc/include/asm/{ => nohash}/mmu-book3e.h (100%)
create mode 100644 arch/powerpc/include/asm/nohash/mmu.h
diff --git a/arch/powerpc/include/asm/mmu.h b/arch/powerpc/include/asm/mmu.h
index eb20eb3b8fb0..2184021b0e1c 100644
--- a/arch/powerpc/include/asm/mmu.h
+++ b/arch/powerpc/include/asm/mmu.h
@@ -341,18 +341,8 @@ static inline void mmu_early_init_devtree(void) { }
#if defined(CONFIG_PPC_STD_MMU_32)
/* 32-bit classic hash table MMU */
#include
-#elif defined(CONFIG_40x)
-/* 40x-style software loaded TLB */
-# include
-#elif defined(CONFIG_44x)
-/* 44x-style software loaded TLB */
-# include
-#elif defined(CONFIG_PPC_BOOK3E_MMU)
-/* Freescale Book-E software loaded TLB or Book-3e (ISA 2.06+) MMU */
-# include
-#elif defined (CONFIG_PPC_8xx)
-/* Motorola/Freescale 8xx software loaded TLB */
-# include
+#elif defined(CONFIG_PPC_MMU_NOHASH)
+#include
#endif
#endif /* __KERNEL__ */
diff --git a/arch/powerpc/include/asm/mmu-40x.h
b/arch/powerpc/include/asm/nohash/32/mmu-40x.h
similarity index 100%
rename from arch/powerpc/include/asm/mmu-40x.h
rename to arch/powerpc/include/asm/nohash/32/mmu-40x.h
diff --git a/arch/powerpc/include/asm/mmu-44x.h
b/arch/powerpc/include/asm/nohash/32/mmu-44x.h
similarity index 100%
rename from arch/powerpc/include/asm/mmu-44x.h
rename to arch/powerpc/include/asm/nohash/32/mmu-44x.h
diff --git a/arch/powerpc/include/asm/mmu-8xx.h
b/arch/powerpc/include/asm/nohash/32/mmu-8xx.h
similarity index 100%
rename from arch/powerpc/include/asm/mmu-8xx.h
rename to arch/powerpc/include/asm/nohash/32/mmu-8xx.h
diff --git a/arch/powerpc/include/asm/nohash/32/mmu.h
b/arch/powerpc/include/asm/nohash/32/mmu.h
new file mode 100644
index ..af0e8b54876a
--- /dev/null
+++ b/arch/powerpc/include/asm/nohash/32/mmu.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _ASM_POWERPC_NOHASH_32_MMU_H_
+#define _ASM_POWERPC_NOHASH_32_MMU_H_
+
+#if defined(CONFIG_40x)
+/* 40x-style software loaded TLB */
+#include
+#elif defined(CONFIG_44x)
+/* 44x-style software loaded TLB */
+#include
+#elif defined(CONFIG_PPC_BOOK3E_MMU)
+/* Freescale Book-E software loaded TLB or Book-3e (ISA 2.06+) MMU */
+#include
+#elif defined (CONFIG_PPC_8xx)
+/* Motorola/Freescale 8xx software loaded TLB */
+#include
+#endif
+
+#endif /* _ASM_POWERPC_NOHASH_32_MMU_H_ */
diff --git a/arch/powerpc/include/asm/nohash/64/mmu.h
b/arch/powerpc/include/asm/nohash/64/mmu.h
new file mode 100644
index ..87871d027b75
--- /dev/null
+++ b/arch/powerpc/include/asm/nohash/64/mmu.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _ASM_POWERPC_NOHASH_64_MMU_H_
+#define _ASM_POWERPC_NOHASH_64_MMU_H_
+
+/* Freescale Book-E software loaded TLB or Book-3e (ISA 2.06+) MMU */
+#include
+
+#endif /* _ASM_POWERPC_NOHASH_64_MMU_H_ */
diff --git a/arch/powerpc/include/asm/mmu-book3e.h
b/arch/powerpc/include/asm/nohash/mmu-book3e.h
similarity index 100%
rename from arch/powerpc/include/asm/mmu-book3e.h
rename to arch/powerpc/include/asm/nohash/mmu-book3e.h
diff --git a/arch/powerpc/include/asm/nohash/mmu.h
b/arch/powerpc/include/asm/nohash/mmu.h
new file mode 100644
index ..a037cb1efb57
--- /dev/null
+++ b/arch/powerpc/include/asm/nohash/mmu.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _ASM_POWERPC_NOHASH_MMU_H_
+#define _ASM_POWERPC_NOHASH_MMU_H_
+
+#ifdef CONFIG_PPC64
+#include
+#else
+#include
+#endif
+
+#endif /* _ASM_POWERPC_NOHASH_MMU_H_ */
diff --git a/arch/powerpc/kernel/cpu_setup_fsl_booke.S
b/arch/powerpc/kernel/cpu_setup_fsl_booke.S
index 8d142e5d84cd..5fbc890d1094 100644
--- a/arch/powerpc/kernel/cpu_setup_fsl_booke.S
+++
[PATCH v6 03/20] powerpc/mm: Avoid useless lock with single page fragments
There is no point in taking the page table lock as pte_frag or
pmd_frag are always NULL when we have only one fragment.
Reviewed-by: Aneesh Kumar K.V
Signed-off-by: Christophe Leroy
---
arch/powerpc/mm/pgtable-book3s64.c | 3 +++
arch/powerpc/mm/pgtable-frag.c | 3 +++
2 files changed, 6 insertions(+)
diff --git a/arch/powerpc/mm/pgtable-book3s64.c
b/arch/powerpc/mm/pgtable-book3s64.c
index 84ff3403239c..9f78db7c8c2a 100644
--- a/arch/powerpc/mm/pgtable-book3s64.c
+++ b/arch/powerpc/mm/pgtable-book3s64.c
@@ -243,6 +243,9 @@ static pmd_t *get_pmd_from_cache(struct mm_struct *mm)
{
void *pmd_frag, *ret;
+ if (PMD_FRAG_NR == 1)
+ return NULL;
+
spin_lock(>page_table_lock);
ret = mm->context.pmd_frag;
if (ret) {
diff --git a/arch/powerpc/mm/pgtable-frag.c b/arch/powerpc/mm/pgtable-frag.c
index d61e7c2a9a79..7544d0d7177d 100644
--- a/arch/powerpc/mm/pgtable-frag.c
+++ b/arch/powerpc/mm/pgtable-frag.c
@@ -34,6 +34,9 @@ static pte_t *get_pte_from_cache(struct mm_struct *mm)
{
void *pte_frag, *ret;
+ if (PTE_FRAG_NR == 1)
+ return NULL;
+
spin_lock(>page_table_lock);
ret = mm->context.pte_frag;
if (ret) {
--
2.13.3
[PATCH v6 02/20] powerpc/mm: Move pte_fragment_alloc() to a common location
In preparation of next patch which generalises the use of
pte_fragment_alloc() for all, this patch moves the related functions
in a place that is common to all subarches.
The 8xx will need that for supporting 16k pages, as in that mode
page tables still have a size of 4k.
Since pte_fragment with only once fragment is not different
from what is done in the general case, we can easily migrate all
subarchs to pte fragments.
Reviewed-by: Aneesh Kumar K.V
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/book3s/64/pgalloc.h | 1 +
arch/powerpc/mm/Makefile | 4 +-
arch/powerpc/mm/mmu_context_book3s64.c | 15
arch/powerpc/mm/pgtable-book3s64.c | 85
arch/powerpc/mm/pgtable-frag.c | 116 +++
5 files changed, 120 insertions(+), 101 deletions(-)
create mode 100644 arch/powerpc/mm/pgtable-frag.c
diff --git a/arch/powerpc/include/asm/book3s/64/pgalloc.h
b/arch/powerpc/include/asm/book3s/64/pgalloc.h
index bfed4cf3b2f3..6c2808c0f052 100644
--- a/arch/powerpc/include/asm/book3s/64/pgalloc.h
+++ b/arch/powerpc/include/asm/book3s/64/pgalloc.h
@@ -39,6 +39,7 @@ extern struct vmemmap_backing *vmemmap_list;
extern struct kmem_cache *pgtable_cache[];
#define PGT_CACHE(shift) pgtable_cache[shift]
+void pte_frag_destroy(void *pte_frag);
extern pte_t *pte_fragment_alloc(struct mm_struct *, unsigned long, int);
extern pmd_t *pmd_fragment_alloc(struct mm_struct *, unsigned long);
extern void pte_fragment_free(unsigned long *, int);
diff --git a/arch/powerpc/mm/Makefile b/arch/powerpc/mm/Makefile
index ca96e7be4d0e..3cbb1acf0745 100644
--- a/arch/powerpc/mm/Makefile
+++ b/arch/powerpc/mm/Makefile
@@ -15,7 +15,9 @@ obj-$(CONFIG_PPC_MMU_NOHASH) += mmu_context_nohash.o
tlb_nohash.o \
obj-$(CONFIG_PPC_BOOK3E) += tlb_low_$(BITS)e.o
hash64-$(CONFIG_PPC_NATIVE):= hash_native_64.o
obj-$(CONFIG_PPC_BOOK3E_64) += pgtable-book3e.o
-obj-$(CONFIG_PPC_BOOK3S_64)+= pgtable-hash64.o hash_utils_64.o slb.o
$(hash64-y) mmu_context_book3s64.o pgtable-book3s64.o
+obj-$(CONFIG_PPC_BOOK3S_64)+= pgtable-hash64.o hash_utils_64.o slb.o \
+ $(hash64-y) mmu_context_book3s64.o \
+ pgtable-book3s64.o pgtable-frag.o
obj-$(CONFIG_PPC_RADIX_MMU)+= pgtable-radix.o tlb-radix.o
obj-$(CONFIG_PPC_STD_MMU_32) += ppc_mmu_32.o hash_low_32.o
mmu_context_hash32.o
obj-$(CONFIG_PPC_STD_MMU) += tlb_hash$(BITS).o
diff --git a/arch/powerpc/mm/mmu_context_book3s64.c
b/arch/powerpc/mm/mmu_context_book3s64.c
index 510f103d7813..f720c5cc0b5e 100644
--- a/arch/powerpc/mm/mmu_context_book3s64.c
+++ b/arch/powerpc/mm/mmu_context_book3s64.c
@@ -164,21 +164,6 @@ static void destroy_contexts(mm_context_t *ctx)
}
}
-static void pte_frag_destroy(void *pte_frag)
-{
- int count;
- struct page *page;
-
- page = virt_to_page(pte_frag);
- /* drop all the pending references */
- count = ((unsigned long)pte_frag & ~PAGE_MASK) >> PTE_FRAG_SIZE_SHIFT;
- /* We allow PTE_FRAG_NR fragments from a PTE page */
- if (atomic_sub_and_test(PTE_FRAG_NR - count, >pt_frag_refcount)) {
- pgtable_page_dtor(page);
- __free_page(page);
- }
-}
-
static void pmd_frag_destroy(void *pmd_frag)
{
int count;
diff --git a/arch/powerpc/mm/pgtable-book3s64.c
b/arch/powerpc/mm/pgtable-book3s64.c
index 43e99e1d947b..84ff3403239c 100644
--- a/arch/powerpc/mm/pgtable-book3s64.c
+++ b/arch/powerpc/mm/pgtable-book3s64.c
@@ -321,91 +321,6 @@ void pmd_fragment_free(unsigned long *pmd)
}
}
-static pte_t *get_pte_from_cache(struct mm_struct *mm)
-{
- void *pte_frag, *ret;
-
- spin_lock(>page_table_lock);
- ret = mm->context.pte_frag;
- if (ret) {
- pte_frag = ret + PTE_FRAG_SIZE;
- /*
-* If we have taken up all the fragments mark PTE page NULL
-*/
- if (((unsigned long)pte_frag & ~PAGE_MASK) == 0)
- pte_frag = NULL;
- mm->context.pte_frag = pte_frag;
- }
- spin_unlock(>page_table_lock);
- return (pte_t *)ret;
-}
-
-static pte_t *__alloc_for_ptecache(struct mm_struct *mm, int kernel)
-{
- void *ret = NULL;
- struct page *page;
-
- if (!kernel) {
- page = alloc_page(PGALLOC_GFP | __GFP_ACCOUNT);
- if (!page)
- return NULL;
- if (!pgtable_page_ctor(page)) {
- __free_page(page);
- return NULL;
- }
- } else {
- page = alloc_page(PGALLOC_GFP);
- if (!page)
- return NULL;
- }
-
- atomic_set(>pt_frag_refcount, 1);
-
- ret = page_address(page);
- /*
-* if we support only one fragment just return the
-* allocated page.
[PATCH v6 01/20] Revert "powerpc/8xx: Use L1 entry APG to handle _PAGE_ACCESSED for CONFIG_SWAP"
This reverts commit 4f94b2c7462d9720b2afa7e8e8d4c19446bb31ce.
That commit was buggy, as it used rlwinm instead of rlwimi.
Instead of fixing that bug, we revert the previous commit in order to
reduce the dependency between L1 entries and L2 entries
Fixes: 4f94b2c7462d9 ("powerpc/8xx: Use L1 entry APG to handle _PAGE_ACCESSED
for CONFIG_SWAP")
Cc: sta...@vger.kernel.org
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/mmu-8xx.h | 34 +---
arch/powerpc/kernel/head_8xx.S | 45 +++---
arch/powerpc/mm/8xx_mmu.c | 2 +-
3 files changed, 34 insertions(+), 47 deletions(-)
diff --git a/arch/powerpc/include/asm/mmu-8xx.h
b/arch/powerpc/include/asm/mmu-8xx.h
index 4f547752ae79..193f53116c7a 100644
--- a/arch/powerpc/include/asm/mmu-8xx.h
+++ b/arch/powerpc/include/asm/mmu-8xx.h
@@ -34,20 +34,12 @@
* respectively NA for All or X for Supervisor and no access for User.
* Then we use the APG to say whether accesses are according to Page rules or
* "all Supervisor" rules (Access to all)
- * We also use the 2nd APG bit for _PAGE_ACCESSED when having SWAP:
- * When that bit is not set access is done iaw "all user"
- * which means no access iaw page rules.
- * Therefore, we define 4 APG groups. lsb is _PMD_USER, 2nd is _PAGE_ACCESSED
- * 0x => No access => 11 (all accesses performed as user iaw page definition)
- * 10 => No user => 01 (all accesses performed according to page definition)
- * 11 => User => 00 (all accesses performed as supervisor iaw page definition)
+ * Therefore, we define 2 APG groups. lsb is _PMD_USER
+ * 0 => No user => 01 (all accesses performed according to page definition)
+ * 1 => User => 00 (all accesses performed as supervisor iaw page definition)
* We define all 16 groups so that all other bits of APG can take any value
*/
-#ifdef CONFIG_SWAP
-#define MI_APG_INIT0xf4f4f4f4
-#else
#define MI_APG_INIT0x
-#endif
/* The effective page number register. When read, contains the information
* about the last instruction TLB miss. When MI_RPN is written, bits in
@@ -115,20 +107,12 @@
* Supervisor and no access for user and NA for ALL.
* Then we use the APG to say whether accesses are according to Page rules or
* "all Supervisor" rules (Access to all)
- * We also use the 2nd APG bit for _PAGE_ACCESSED when having SWAP:
- * When that bit is not set access is done iaw "all user"
- * which means no access iaw page rules.
- * Therefore, we define 4 APG groups. lsb is _PMD_USER, 2nd is _PAGE_ACCESSED
- * 0x => No access => 11 (all accesses performed as user iaw page definition)
- * 10 => No user => 01 (all accesses performed according to page definition)
- * 11 => User => 00 (all accesses performed as supervisor iaw page definition)
+ * Therefore, we define 2 APG groups. lsb is _PMD_USER
+ * 0 => No user => 01 (all accesses performed according to page definition)
+ * 1 => User => 00 (all accesses performed as supervisor iaw page definition)
* We define all 16 groups so that all other bits of APG can take any value
*/
-#ifdef CONFIG_SWAP
-#define MD_APG_INIT0xf4f4f4f4
-#else
#define MD_APG_INIT0x
-#endif
/* The effective page number register. When read, contains the information
* about the last instruction TLB miss. When MD_RPN is written, bits in
@@ -180,12 +164,6 @@
*/
#define SPRN_M_TW 799
-/* APGs */
-#define M_APG0 0x
-#define M_APG1 0x0020
-#define M_APG2 0x0040
-#define M_APG3 0x0060
-
#ifdef CONFIG_PPC_MM_SLICES
#include
#define SLICE_ARRAY_SIZE (1 << (32 - SLICE_LOW_SHIFT - 1))
diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
index 134a573a9f2d..12c92a483fb1 100644
--- a/arch/powerpc/kernel/head_8xx.S
+++ b/arch/powerpc/kernel/head_8xx.S
@@ -353,13 +353,14 @@ _ENTRY(ITLBMiss_cmp)
#if defined(ITLB_MISS_KERNEL) || defined(CONFIG_HUGETLB_PAGE)
mtcrr12
#endif
-
-#ifdef CONFIG_SWAP
- rlwinm r11, r10, 31, _PAGE_ACCESSED >> 1
-#endif
/* Load the MI_TWC with the attributes for this "segment." */
mtspr SPRN_MI_TWC, r11/* Set segment attributes */
+#ifdef CONFIG_SWAP
+ rlwinm r11, r10, 32-5, _PAGE_PRESENT
+ and r11, r11, r10
+ rlwimi r10, r11, 0, _PAGE_PRESENT
+#endif
li r11, RPN_PATTERN | 0x200
/* The Linux PTE won't go exactly into the MMU TLB.
* Software indicator bits 20 and 23 must be clear.
@@ -470,14 +471,22 @@ _ENTRY(DTLBMiss_jmp)
* above.
*/
rlwimi r11, r10, 0, _PAGE_GUARDED
-#ifdef CONFIG_SWAP
- /* _PAGE_ACCESSED has to be set. We use second APG bit for that, 0
-* on that bit will represent a Non Access group
-*/
- rlwinm r11, r10, 31, _PAGE_ACCESSED >> 1
-#endif
mtspr SPRN_MD_TWC, r11
+ /* Both _PAGE_ACCESSED and _PAGE_PRESENT has to be set.
+* We also need to know if
[PATCH v6 00/20] Implement use of HW assistance on TLB table walk on 8xx
The purpose of this serie is to implement hardware assistance for TLB table walk on the 8xx. First part prepares for using HW assistance in TLB routines: - Reverts a former patch which broke SWAP on the 8xx - move book3s64 page fragment code in a common part for reusing it by the 8xx as 16k page size mode still uses 4k page tables. - switches to patch_site instead of patch_instruction, as it makes the code clearer and avoids pollution with global symbols. - Optimise access to perf counters (hence reducing number of registers used) Second part implements HW assistance in TLB routines in the following steps: - Disable 16k page size mode and 512k hugepages - Switch 4k to HW assistance - Bring back 512k hugepages - Bring back 16k page size mode. Tested successfully on 8xx. This serie applies after the two following series: - [v2 00/24] ban the use of _PAGE_XXX flags outside platform specific code (https://patchwork.ozlabs.org/project/linuxppc-dev/list/?series=65376) - [v2,1/4] powerpc/mm: enable the use of page table cache of order 0 (https://patchwork.ozlabs.org/project/linuxppc-dev/list/?series=60777) Successfull compilation on kisskb (v5) http://kisskb.ellerman.id.au/kisskb/head/555f5323c8d1459c9a452ae92c18048a4e29af94/ Successfull compilation on kisskb (v4) http://kisskb.ellerman.id.au/kisskb/branch/chleroy/head/cfdf3349e3877df4cbfa9193ad1f4f4e4ada52de/ Successfull compilation on following defconfigs (v3): ppc64_defconfig ppc64e_defconfig Successfull compilation on following defconfigs (v2): ppc64_defconfig ppc64e_defconfig pseries_defconfig pmac32_defconfig linkstation_defconfig corenet32_smp_defconfig ppc40x_defconfig storcenter_defconfig ppc44x_defconfig Changes in v6: - Droped the part related to handling GUARD attribute at PGD/PMD level. - Moved the commonalisation of page_fragment in the begining (this part has been reviewed by Aneesh) - Rebased on today merge branch (19 Oct) Changes in v5: - Also avoid useless lock in get_pmd_from_cache() - A new patch to relocate mmu headers in platform specific directories - A new patch to distribute pgtable_t typedefs in platform specific mmu headers instead of the uggly #ifdef - Moved early_pte_alloc_kernel() in platform specific pgalloc - Restricted definition of PTE_FRAG_SIZE and PTE_FRAG_NR to platforms using the pte fragmentation. - arch_exit_mmap() and destroy_pagetable_cache() are now platform specific. Changes in v4: - Reordered the serie to put at the end the modifications which makes L1 and L2 entries independant. - No modifications to ppc64 ioremap (we still have an opportunity to merge them, for a future patch serie) - 8xx code modified to use patch_site instead of patch_instruction to get a clearer code and avoid object pollution with global symbols - Moved perf counters in first 32kb of memory to optimise access - Split the big bang to HW assistance in several steps: 1. Temporarily removes support of 16k pages and 512k hugepages 2. Change TLB routines to use HW assistance for 4k pages and 8M hugepages 3. Add back support for 512k hugepages 4. Add back support for 16k pages (using pte_fragment as page tables are still 4k) Changes in v3: - Fixed an issue in the 09/14 when CONFIG_PIN_TLB_TEXT was not enabled - Added performance measurement in the 09/14 commit log - Rebased on latest 'powerpc/merge' tree, which conflicted with 13/14 Changes in v2: - Removed the 3 first patchs which have been applied already - Fixed compilation errors reported by Michael - Squashed the commonalisation of ioremap functions into a single patch - Fixed the use of pte_fragment - Added a patch optimising perf counting of TLB misses and instructions Christophe Leroy (20): Revert "powerpc/8xx: Use L1 entry APG to handle _PAGE_ACCESSED for CONFIG_SWAP" powerpc/mm: Move pte_fragment_alloc() to a common location powerpc/mm: Avoid useless lock with single page fragments powerpc/mm: move platform specific mmu-xxx.h in platform directories powerpc/mm: Move pgtable_t into platform headers powerpc/code-patching: add a helper to get the address of a patch_site powerpc/8xx: Use patch_site for memory setup patching powerpc/8xx: Use patch_site for perf counters setup powerpc/8xx: Move SW perf counters in first 32kb of memory powerpc/8xx: Temporarily disable 16k pages and 512k hugepages powerpc/mm: Use hardware assistance in TLB handlers on the 8xx powerpc/mm: Enable 512k hugepage support with HW assistance on the 8xx powerpc/8xx: don't use r12/SPRN_SPRG_SCRATCH2 in TLB Miss handlers powerpc/8xx: regroup TLB handler routines powerpc/mm: don't use pte_alloc_one_kernel() before slab is available powerpc/mm: inline pte_alloc_one() and pte_alloc_one_kernel() in PPC32 powerpc/book3s32: Remove CONFIG_BOOKE dependent code powerpc/mm: Extend pte_fragment functionality to nohash/32 powerpc/8xx: Remove PTE_ATOMIC_UPDATES powerpc/mm: reintroduce 16K pages with HW assistance on 8xx
Re: [PATCH kernel 3/3] vfio_pci: Add NVIDIA GV100GL [Tesla V100 SXM2] [10de:1db1] subdriver
On Thu, Oct 18, 2018 at 11:40:19AM -0700, Piotr Jaroszynski wrote: > GPUs are linked to NPU devices through device tree properties, I think. > Linux has a helper to look up linked NPU devices for a PCI device > pnv_pci_get_npu_dev() here: > https://elixir.bootlin.com/linux/latest/source/arch/powerpc/platforms/powernv/npu-dma.c#L86 FYI, all this code has never been used in the three years it was in the tree, so I'm going to remove it pretty soon.
Re: [PATCH] powerpc: Fix stack protector crashes on CPU hotplug
Le 19/10/2018 à 07:59, Michael Ellerman a écrit :
Recently in commit 7241d26e8175 ("powerpc/64: properly initialise
the stackprotector canary on SMP.") we fixed a crash with stack
protector on SMP by initialising the stack canary in
cpu_idle_thread_init().
But this can also causes crashes, when a CPU comes back online after
being offline:
Kernel panic - not syncing: stack-protector: Kernel stack is corrupted in:
pnv_smp_cpu_kill_self+0x2a0/0x2b0
CPU: 1 PID: 0 Comm: swapper/1 Not tainted
4.19.0-rc3-gcc-7.3.1-00168-g4ffe713b7587 #94
Call Trace:
dump_stack+0xb0/0xf4 (unreliable)
panic+0x144/0x328
__stack_chk_fail+0x2c/0x30
pnv_smp_cpu_kill_self+0x2a0/0x2b0
cpu_die+0x48/0x70
arch_cpu_idle_dead+0x20/0x40
do_idle+0x274/0x390
cpu_startup_entry+0x38/0x50
start_secondary+0x5e4/0x600
start_secondary_prolog+0x10/0x14
Looking at the stack we see that the canary value in the stack frame
doesn't match the canary in the task/paca. That is because we have
reinitialised the task/paca value, but then the CPU coming online has
returned into a function using the old canary value. That causes the
comparison to fail.
Instead we can call boot_init_stack_canary() from start_secondary()
which never returns. This is essentially what the generic code does in
cpu_startup_entry() under #ifdef X86, we should make that non-x86
specific in a future patch.
This shall not be done on arches that uses a global canary, so I think
it has to be kept arch specific. Indeed I think x86 should move it to
cpu_bringup_and_idle(). I'll propose them a patch for that.
Christophe
Fixes: 7241d26e8175 ("powerpc/64: properly initialise the stackprotector canary on
SMP.")
Reported-by: Joel Stanley
Signed-off-by: Michael Ellerman
Reviewed-by: Christophe Leroy
---
arch/powerpc/kernel/smp.c | 10 +++---
1 file changed, 3 insertions(+), 7 deletions(-)
diff --git a/arch/powerpc/kernel/smp.c b/arch/powerpc/kernel/smp.c
index 8e3a5da24d59..951c476faffc 100644
--- a/arch/powerpc/kernel/smp.c
+++ b/arch/powerpc/kernel/smp.c
@@ -61,6 +61,7 @@
#include
#include
#include
+#include
#ifdef DEBUG
#include
@@ -1014,16 +1015,9 @@ static void cpu_idle_thread_init(unsigned int cpu,
struct task_struct *idle)
{
struct thread_info *ti = task_thread_info(idle);
-#ifdef CONFIG_STACKPROTECTOR
- idle->stack_canary = get_random_canary();
-#endif
-
#ifdef CONFIG_PPC64
paca_ptrs[cpu]->__current = idle;
paca_ptrs[cpu]->kstack = (unsigned long)ti + THREAD_SIZE -
STACK_FRAME_OVERHEAD;
-#ifdef CONFIG_STACKPROTECTOR
- paca_ptrs[cpu]->canary = idle->stack_canary;
-#endif
#endif
ti->cpu = cpu;
secondary_ti = current_set[cpu] = ti;
@@ -1316,6 +1310,8 @@ void start_secondary(void *unused)
notify_cpu_starting(cpu);
set_cpu_online(cpu, true);
+ boot_init_stack_canary();
+
local_irq_enable();
/* We can enable ftrace for secondary cpus now */
[PATCH] powerpc/msi: Fix compile error on mpc83xx
mpic_get_primary_version() is not defined when not using MPIC.
The compile error log like:
arch/powerpc/sysdev/built-in.o: In function `fsl_of_msi_probe':
fsl_msi.c:(.text+0x150c): undefined reference to `fsl_mpic_primary_get_version'
Signed-off-by: Jia Hongtao
Signed-off-by: Scott Wood
Reported-by: Radu Rendec
Fixes: 807d38b73b6 ("powerpc/mpic: Add get_version API both for internal and
external use")
Cc: sta...@vger.kernel.org
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/mpic.h | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/powerpc/include/asm/mpic.h b/arch/powerpc/include/asm/mpic.h
index fad8ddd697ac..0abf2e7fd222 100644
--- a/arch/powerpc/include/asm/mpic.h
+++ b/arch/powerpc/include/asm/mpic.h
@@ -393,7 +393,14 @@ extern struct bus_type mpic_subsys;
#defineMPIC_REGSET_TSI108 MPIC_REGSET(1) /* Tsi108/109
PIC */
/* Get the version of primary MPIC */
+#ifdef CONFIG_MPIC
extern u32 fsl_mpic_primary_get_version(void);
+#else
+static inline u32 fsl_mpic_primary_get_version(void)
+{
+ return 0;
+}
+#endif
/* Allocate the controller structure and setup the linux irq descs
* for the range if interrupts passed in. No HW initialization is
--
2.13.3
[PATCH] powerpc: Fix stack protector crashes on CPU hotplug
Recently in commit 7241d26e8175 ("powerpc/64: properly initialise
the stackprotector canary on SMP.") we fixed a crash with stack
protector on SMP by initialising the stack canary in
cpu_idle_thread_init().
But this can also causes crashes, when a CPU comes back online after
being offline:
Kernel panic - not syncing: stack-protector: Kernel stack is corrupted in:
pnv_smp_cpu_kill_self+0x2a0/0x2b0
CPU: 1 PID: 0 Comm: swapper/1 Not tainted
4.19.0-rc3-gcc-7.3.1-00168-g4ffe713b7587 #94
Call Trace:
dump_stack+0xb0/0xf4 (unreliable)
panic+0x144/0x328
__stack_chk_fail+0x2c/0x30
pnv_smp_cpu_kill_self+0x2a0/0x2b0
cpu_die+0x48/0x70
arch_cpu_idle_dead+0x20/0x40
do_idle+0x274/0x390
cpu_startup_entry+0x38/0x50
start_secondary+0x5e4/0x600
start_secondary_prolog+0x10/0x14
Looking at the stack we see that the canary value in the stack frame
doesn't match the canary in the task/paca. That is because we have
reinitialised the task/paca value, but then the CPU coming online has
returned into a function using the old canary value. That causes the
comparison to fail.
Instead we can call boot_init_stack_canary() from start_secondary()
which never returns. This is essentially what the generic code does in
cpu_startup_entry() under #ifdef X86, we should make that non-x86
specific in a future patch.
Fixes: 7241d26e8175 ("powerpc/64: properly initialise the stackprotector canary
on SMP.")
Reported-by: Joel Stanley
Signed-off-by: Michael Ellerman
---
arch/powerpc/kernel/smp.c | 10 +++---
1 file changed, 3 insertions(+), 7 deletions(-)
diff --git a/arch/powerpc/kernel/smp.c b/arch/powerpc/kernel/smp.c
index 8e3a5da24d59..951c476faffc 100644
--- a/arch/powerpc/kernel/smp.c
+++ b/arch/powerpc/kernel/smp.c
@@ -61,6 +61,7 @@
#include
#include
#include
+#include
#ifdef DEBUG
#include
@@ -1014,16 +1015,9 @@ static void cpu_idle_thread_init(unsigned int cpu,
struct task_struct *idle)
{
struct thread_info *ti = task_thread_info(idle);
-#ifdef CONFIG_STACKPROTECTOR
- idle->stack_canary = get_random_canary();
-#endif
-
#ifdef CONFIG_PPC64
paca_ptrs[cpu]->__current = idle;
paca_ptrs[cpu]->kstack = (unsigned long)ti + THREAD_SIZE -
STACK_FRAME_OVERHEAD;
-#ifdef CONFIG_STACKPROTECTOR
- paca_ptrs[cpu]->canary = idle->stack_canary;
-#endif
#endif
ti->cpu = cpu;
secondary_ti = current_set[cpu] = ti;
@@ -1316,6 +1310,8 @@ void start_secondary(void *unused)
notify_cpu_starting(cpu);
set_cpu_online(cpu, true);
+ boot_init_stack_canary();
+
local_irq_enable();
/* We can enable ftrace for secondary cpus now */
--
2.17.2
