Re: [PATCH 0/3] System call table generation support

2018-11-29 Thread Satheesh Rajendran
On Thu, Nov 29, 2018 at 01:48:16PM +0530, Firoz Khan wrote: > Hi Sathish, > > Thanks for your email. > > On Thu, 29 Nov 2018 at 12:05, Satheesh Rajendran > wrote: > > > > On Fri, Sep 14, 2018 at 02:02:57PM +0530, Firoz Khan wrote: > > > The purpose of this patch series is: > > > 1. We can

Re: [PATCH 12/24] powerpc/mm: Fix reporting of kernel execute faults

2018-11-29 Thread Christophe LEROY
Le 30/11/2018 à 06:50, Aneesh Kumar K.V a écrit : Christophe LEROY writes: Hi Ben, I have an issue on the 8xx with this change Le 19/07/2017 à 06:49, Benjamin Herrenschmidt a écrit : We currently test for is_exec and DSISR_PROTFAULT but that doesn't make sense as this is the wrong error

[PATCH] powerpc: Look for "stdout-path" when setting up legacy consoles

2018-11-29 Thread Benjamin Herrenschmidt
Commit 78e5dfea8 "powerpc: dts: replace 'linux,stdout-path' with 'stdout-path'" broke the default console on a number of embedded PowerPC systems, because it failed to also update the code in arch/powerpc/kernel/legacy_serial.c to look for that property in addition to the old one. This fixes it.

Re: [PATCH v8 04/14] integrity: Introduce struct evm_xattr

2018-11-29 Thread Mimi Zohar
On Fri, 2018-11-16 at 18:07 -0200, Thiago Jung Bauermann wrote: > Even though struct evm_ima_xattr_data includes a fixed-size array to hold a > SHA1 digest, most of the code ignores the array and uses the struct to mean > "type indicator followed by data of unspecified size" and tracks the real >

Re: [PATCH v8 17/20] powerpc/8xx: Enable 512k hugepage support with HW assistance

2018-11-29 Thread kbuild test robot
Hi Christophe, Thank you for the patch! Yet something to improve: [auto build test ERROR on powerpc/next] [also build test ERROR on v4.20-rc4] [cannot apply to next-20181129] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system] url: https

[PATCH v1 13/13] powerpc/kconfig: make _etext and data areas alignment configurable on Book3s 32

2018-11-29 Thread Christophe Leroy
Depending on the number of available BATs for mapping the different kernel areas, it might be needed to increase the alignment of _etext and/or of data areas. This patchs allows the user to do it via Kconfig. Signed-off-by: Christophe Leroy --- arch/powerpc/Kconfig | 32

[PATCH v1 12/13] powerpc/mm/32s: Use BATs for STRICT_KERNEL_RWX

2018-11-29 Thread Christophe Leroy
Today, STRICT_KERNEL_RWX is based on the use of regular pages to map kernel pages. On Book3s 32, it has three consequences: - Using pages instead of BAT for mapping kernel linear memory severely impacts performance. - Exec protection is not effective because no-execute cannot be set at page level

[PATCH v1 10/13] powerpc/kconfig: define PAGE_SHIFT inside Kconfig

2018-11-29 Thread Christophe Leroy
Signed-off-by: Christophe Leroy --- arch/powerpc/Kconfig| 7 +++ arch/powerpc/include/asm/page.h | 13 ++--- 2 files changed, 9 insertions(+), 11 deletions(-) diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig index 8be31261aec8..4a81a80d0635 100644 ---

[PATCH v1 11/13] powerpc/kconfig: define CONFIG_DATA_SHIFT and CONFIG_ETEXT_SHIFT

2018-11-29 Thread Christophe Leroy
CONFIG_STRICT_KERNEL_RWX requires a special alignment for DATA for some subarches. Today it is just defined as an #ifdef in vmlinux.lds.S In order to get more flexibility, this patch moves the definition of this alignment in Kconfig On some subarches, CONFIG_STRICT_KERNEL_RWX will require a

[PATCH v1 09/13] powerpc/mmu: add is_strict_kernel_rwx() helper

2018-11-29 Thread Christophe Leroy
Add a helper to know whether STRICT_KERNEL_RWX is enabled. This is based on rodata_enabled flag which is defined only when CONFIG_STRICT_KERNEL_RWX is selected. Signed-off-by: Christophe Leroy --- arch/powerpc/include/asm/mmu.h | 11 +++ arch/powerpc/mm/init_32.c | 4 +--- 2

[PATCH v1 07/13] powerpc/mm/32s: add setibat() clearibat() and update_bats()

2018-11-29 Thread Christophe Leroy
setibat() and clearibat() allows to manipulate IBATs independently of DBATs. update_bats() allows to update bats after init. This is done with MMU off. Signed-off-by: Christophe Leroy --- arch/powerpc/include/asm/book3s/32/mmu-hash.h | 2 ++ arch/powerpc/kernel/head_32.S | 35

[PATCH v1 08/13] powerpc/32: add helper to write into segment registers

2018-11-29 Thread Christophe Leroy
This patch add an helper which wraps 'mtsrin' instruction to write into segment registers. Signed-off-by: Christophe Leroy --- arch/powerpc/include/asm/reg.h | 5 + 1 file changed, 5 insertions(+) diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h index

[PATCH v1 06/13] powerpc/mm/32s: use _PAGE_EXEC in setbat()

2018-11-29 Thread Christophe Leroy
Do not set IBAT when setbat() is called without _PAGE_EXEC Signed-off-by: Christophe Leroy --- arch/powerpc/mm/ppc_mmu_32.c | 10 ++ 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/arch/powerpc/mm/ppc_mmu_32.c b/arch/powerpc/mm/ppc_mmu_32.c index 61c10ee00ba2..1078095d9407

[PATCH v1 04/13] powerpc/mm/32s: use generic mmu_mapin_ram() for all blocks.

2018-11-29 Thread Christophe Leroy
Now that mmu_mapin_ram() is able to handle other blocks than the one starting at 0, the WII can use it for all its blocks. Signed-off-by: Christophe Leroy --- arch/powerpc/mm/pgtable_32.c | 25 +++-- 1 file changed, 7 insertions(+), 18 deletions(-) diff --git

[PATCH v1 05/13] powerpc/wii: remove wii_mmu_mapin_mem2()

2018-11-29 Thread Christophe Leroy
wii_mmu_mapin_mem2() is not used anymore, remove it. Signed-off-by: Christophe Leroy --- arch/powerpc/platforms/embedded6xx/wii.c | 24 1 file changed, 24 deletions(-) diff --git a/arch/powerpc/platforms/embedded6xx/wii.c b/arch/powerpc/platforms/embedded6xx/wii.c

[PATCH v1 03/13] powerpc/mm/32s: rework mmu_mapin_ram()

2018-11-29 Thread Christophe Leroy
This patch reworks mmu_mapin_ram() to be more generic and map as much blocks as possible. It now supports blocks not starting at address 0. It scans DBATs array to find free ones instead of forcing the use of BAT2 and BAT3. Signed-off-by: Christophe Leroy --- arch/powerpc/mm/ppc_mmu_32.c | 61

[PATCH v1 02/13] powerpc/mm/32: add base address to mmu_mapin_ram()

2018-11-29 Thread Christophe Leroy
At the time being, mmu_mapin_ram() always maps RAM from the beginning. But some platforms like the WII have to map a second block of RAM. This patch adds to mmu_mapin_ram() the base address of the block. At the moment, only base address 0 is supported. Signed-off-by: Christophe Leroy ---

[PATCH v1 01/13] powerpc/mm: add exec protection on powerpc 603

2018-11-29 Thread Christophe Leroy
The 603 doesn't have a HASH table, TLB misses are handled by software. It is then possible to generate page fault when _PAGE_EXEC is not set like in nohash/32. There is one "reserved" PTE bit available, this patch uses it for _PAGE_EXEC. In order to support it, set_pte_filter() and

[PATCH v1 00/13] powerpc/32s: Use BATs for STRICT_KERNEL_RWX

2018-11-29 Thread Christophe Leroy
The purpose of this serie is to use BATs with STRICT_KERNEL_RWX See patch 12 for details. Christophe Leroy (13): powerpc/mm: add exec protection on powerpc 603 powerpc/mm/32: add base address to mmu_mapin_ram() powerpc/mm/32s: rework mmu_mapin_ram() powerpc/mm/32s: use generic

Re: [PATCH v8 07/20] powerpc/mm: add helpers to get/set mm.context->pte_frag

2018-11-29 Thread kbuild test robot
Hi Christophe, Thank you for the patch! Yet something to improve: [auto build test ERROR on powerpc/next] [also build test ERROR on v4.20-rc4] [cannot apply to next-20181129] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system] url: https

Re: [PATCH v8 07/20] powerpc/mm: add helpers to get/set mm.context->pte_frag

2018-11-29 Thread kbuild test robot
Hi Christophe, Thank you for the patch! Perhaps something to improve: [auto build test WARNING on powerpc/next] [also build test WARNING on v4.20-rc4] [cannot apply to next-20181129] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system] url

Re: use generic DMA mapping code in powerpc V4

2018-11-29 Thread Christoph Hellwig
On Thu, Nov 29, 2018 at 01:05:23PM +0100, Christian Zigotzky wrote: > I compiled a test kernel from the following Git today. > > http://git.infradead.org/users/hch/misc.git/shortlog/refs/heads/powerpc-dma.4 > > Command: git clone git://git.infradead.org/users/hch/misc.git -b > powerpc-dma.4 a > >

Re: use generic DMA mapping code in powerpc V4

2018-11-29 Thread Christoph Hellwig
> > Please don't apply the new DMA mapping code if you don't be sure if it > > works on all supported PowerPC machines. Is the new DMA mapping code > > really necessary? It's not really nice, to rewrote code if the old code > > works perfect. We must not forget, that we work for the end users.

Re: use generic DMA mapping code in powerpc V4

2018-11-29 Thread Christoph Hellwig
On Wed, Nov 28, 2018 at 10:05:19PM +1100, Michael Ellerman wrote: > Is the plan that you take these via the dma-mapping tree or that they go > via powerpc? In principle either way is fine with me. If it goes through the powerpc tree we might run into a few minor conflicts with the dma-mapping

Re: use generic DMA mapping code in powerpc V4

2018-11-29 Thread Christian Zigotzky
On 29 November 2018 at 1:05PM, Christian Zigotzky wrote: On 28 November 2018 at 12:05PM, Michael Ellerman wrote: Christoph Hellwig writes: Any comments?  I'd like to at least get the ball moving on the easy bits. Nothing specific yet. I'm a bit worried it might break one of the many old

[PATCH v9 20/20] powerpc/8xx: regroup TLB handler routines

2018-11-29 Thread Christophe Leroy
As this is running with MMU off, the CPU only does speculative fetch for code in the same page. Following the significant size reduction of TLB handler routines, the side handlers can be brought back close to the main part, ie in the same page. Signed-off-by: Christophe Leroy ---

[PATCH v9 18/20] powerpc/8xx: reintroduce 16K pages with HW assistance

2018-11-29 Thread Christophe Leroy
Using this HW assistance implies some constraints on the page table structure: - Regardless of the main page size used (4k or 16k), the level 1 table (PGD) contains 1024 entries and each PGD entry covers a 4Mbytes area which is managed by a level 2 table (PTE) containing also 1024 entries each

[PATCH v9 19/20] powerpc/8xx: don't use r12/SPRN_SPRG_SCRATCH2 in TLB Miss handlers

2018-11-29 Thread Christophe Leroy
This patch reworks the TLB Miss handler in order to not use r12 register, hence avoiding having to save it into SPRN_SPRG_SCRATCH2. In the DAR Fixup code we can now use SPRN_M_TW, freeing SPRN_SPRG_SCRATCH2. Then SPRN_SPRG_SCRATCH2 may be used for something else in the future. Signed-off-by:

[PATCH v9 17/20] powerpc/8xx: Enable 512k hugepage support with HW assistance

2018-11-29 Thread Christophe Leroy
For using 512k pages with hardware assistance, the PTEs have to be spread every 128 bytes in the L2 table. Signed-off-by: Christophe Leroy --- arch/powerpc/include/asm/hugetlb.h | 4 +++- arch/powerpc/mm/hugetlbpage.c | 10 +- arch/powerpc/mm/tlb_nohash.c | 3 +++ 3 files

[PATCH v9 16/20] powerpc/8xx: Enable 8M hugepage support with HW assistance

2018-11-29 Thread Christophe Leroy
HW assistance naturally supports 8M huge pages without further modifications. Signed-off-by: Christophe Leroy --- arch/powerpc/mm/tlb_nohash.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/powerpc/mm/tlb_nohash.c b/arch/powerpc/mm/tlb_nohash.c index 4f79639e432f..8ad7aab150b7

[PATCH v9 15/20] powerpc/8xx: Use hardware assistance in TLB handlers

2018-11-29 Thread Christophe Leroy
Today, on the 8xx the TLB handlers do SW tablewalk by doing all the calculation in ASM, in order to match with the Linux page table structure. The 8xx offers hardware assistance which allows significant size reduction of the TLB handlers, hence also reduces the time spent in the handlers.

[PATCH v9 14/20] powerpc/8xx: Temporarily disable 16k pages and hugepages

2018-11-29 Thread Christophe Leroy
In preparation of making use of hardware assistance in TLB handlers, this patch temporarily disables 16K pages and hugepages. The reason is that when using HW assistance in 4K pages mode, the linux model fit with the HW model for 4K pages and 8M pages. However for 16K pages and 512K mode some

[PATCH v9 13/20] powerpc/8xx: Move SW perf counters in first 32kb of memory

2018-11-29 Thread Christophe Leroy
In order to simplify time critical exceptions handling 8xx specific SW perf counters, this patch moves the counters into the beginning of memory. This is possible because .text is readable and the counters are never modified outside of the handlers. By doing this, we avoid having to set a second

[PATCH v9 12/20] powerpc/mm: remove unnecessary test in pgtable_cache_init()

2018-11-29 Thread Christophe Leroy
pgtable_cache_add() gracefully handles the case when a cache that size already exists by returning early with the following test: if (PGT_CACHE(shift)) return; /* Already have a cache of this size */ It is then not needed to test the existence of the cache before.

[PATCH v9 10/20] powerpc/mm: replace hugetlb_cache by PGT_CACHE(PTE_T_ORDER)

2018-11-29 Thread Christophe Leroy
Instead of opencoding cache handling for the special case of hugepage tables having a single pte_t element, this patch makes use of the common pgtable_cache helpers Signed-off-by: Christophe Leroy --- arch/powerpc/include/asm/hugetlb.h | 2 -- arch/powerpc/mm/hugetlbpage.c | 26

[PATCH v9 11/20] powerpc/mm: fix a warning when a cache is common to PGD and hugepages

2018-11-29 Thread Christophe Leroy
While implementing TLB miss HW assistance on the 8xx, the following warning was encountered: [ 423.732965] WARNING: CPU: 0 PID: 345 at mm/slub.c:2412 ___slab_alloc.constprop.30+0x26c/0x46c [ 423.733033] CPU: 0 PID: 345 Comm: mmap Not tainted 4.18.0-rc8-00664-g2dfff9121c55 #671 [ 423.733075]

[PATCH v9 09/20] powerpc/mm: enable the use of page table cache of order 0

2018-11-29 Thread Christophe Leroy
hugepages uses a cache of order 0. Lets allow page tables of order 0 in the common part in order to avoid open coding in hugetlb Signed-off-by: Christophe Leroy --- arch/powerpc/include/asm/book3s/32/pgalloc.h | 5 + arch/powerpc/include/asm/book3s/64/pgalloc.h | 5 +

[PATCH v9 08/20] powerpc/mm: Extend pte_fragment functionality to PPC32

2018-11-29 Thread Christophe Leroy
In order to allow the 8xx to handle pte_fragments, this patch extends the use of pte_fragments to PPC32 platforms. Signed-off-by: Christophe Leroy --- arch/powerpc/include/asm/book3s/32/mmu-hash.h | 5 - arch/powerpc/include/asm/book3s/32/pgalloc.h | 17 +

[PATCH v9 07/20] powerpc/mm: add helpers to get/set mm.context->pte_frag

2018-11-29 Thread Christophe Leroy
In order to handle pte_fragment functions with single fragment without adding pte_frag in all mm_context_t, this patch creates two helpers which do nothing on platforms using a single fragment. Signed-off-by: Christophe Leroy --- arch/powerpc/include/asm/pgtable.h | 25 +

[PATCH v9 06/20] powerpc/mm: Move pgtable_t into platform headers

2018-11-29 Thread Christophe Leroy
This patch move pgtable_t into platform headers. It gets rid of the CONFIG_PPC_64K_PAGES case for PPC64 as nohash/64 doesn't support CONFIG_PPC_64K_PAGES. Reviewed-by: Aneesh Kumar K.V Signed-off-by: Christophe Leroy --- arch/powerpc/include/asm/book3s/32/mmu-hash.h | 2 ++

[PATCH v9 05/20] powerpc/mm: move platform specific mmu-xxx.h in platform directories

2018-11-29 Thread Christophe Leroy
The purpose of this patch is to move platform specific mmu-xxx.h files in platform directories like pte-xxx.h files. In the meantime this patch creates common nohash and nohash/32 + nohash/64 mmu.h files for future common parts. Reviewed-by: Aneesh Kumar K.V Signed-off-by: Christophe Leroy ---

[PATCH v9 04/20] powerpc/mm: Avoid useless lock with single page fragments

2018-11-29 Thread Christophe Leroy
There is no point in taking the page table lock as pte_frag or pmd_frag are always NULL when we have only one fragment. Reviewed-by: Aneesh Kumar K.V Signed-off-by: Christophe Leroy --- arch/powerpc/mm/pgtable-book3s64.c | 3 +++ arch/powerpc/mm/pgtable-frag.c | 3 +++ 2 files changed, 6

[PATCH v9 03/20] powerpc/mm: Move pte_fragment_alloc() to a common location

2018-11-29 Thread Christophe Leroy
In preparation of next patch which generalises the use of pte_fragment_alloc() for all, this patch moves the related functions in a place that is common to all subarches. The 8xx will need that for supporting 16k pages, as in that mode page tables still have a size of 4k. Since pte_fragment with

[PATCH v9 02/20] powerpc/8xx: Remove PTE_ATOMIC_UPDATES

2018-11-29 Thread Christophe Leroy
commit 1bc54c03117b9 ("powerpc: rework 4xx PTE access and TLB miss") introduced non atomic PTE updates and started the work of removing PTE updates in TLB miss handlers, but kept PTE_ATOMIC_UPDATES for the 8xx with the following comment: /* Until my rework is finished, 8xx still needs atomic PTE

[PATCH v9 01/20] powerpc/book3s32: Remove CONFIG_BOOKE dependent code

2018-11-29 Thread Christophe Leroy
BOOK3S/32 cannot be BOOKE, so remove useless code Signed-off-by: Christophe Leroy --- arch/powerpc/include/asm/book3s/32/pgalloc.h | 18 -- arch/powerpc/include/asm/book3s/32/pgtable.h | 14 -- 2 files changed, 32 deletions(-) diff --git

[PATCH v9 00/20] Implement use of HW assistance on TLB table walk on 8xx

2018-11-29 Thread Christophe Leroy
The purpose of this serie is to implement hardware assistance for TLB table walk on the 8xx. First part prepares for using HW assistance in TLB routines: - Trivial fixes: - Remove CONFIG_BOOKE stuff from book3S headers. - Removal of unneeded atomic PTE update requirement for 8xx.

[PATCH -next] powerpc/64s: Fix debugfs_simple_attr.cocci warnings

2018-11-29 Thread YueHaibing
Use DEFINE_DEBUGFS_ATTRIBUTE rather than DEFINE_SIMPLE_ATTRIBUTE for debugfs files. Semantic patch information: Rationale: DEFINE_SIMPLE_ATTRIBUTE + debugfs_create_file() imposes some significant overhead as compared to DEFINE_DEBUGFS_ATTRIBUTE + debugfs_create_file_unsafe(). Generated by:

Re: [PATCH v3] powerpc/mm: add exec protection on powerpc 603

2018-11-29 Thread Christophe LEROY
Le 28/11/2018 à 18:21, Christophe Leroy a écrit : The 603 doesn't have a HASH table, TLB misses are handled by software. It is then possible to generate page fault when _PAGE_EXEC is not set like in nohash/32. There is one "reserved" PTE bit available, this patch uses it for _PAGE_EXEC. In

Re: [PATCH] powerpc/mm: add exec protection on powerpc 603

2018-11-29 Thread Christophe LEROY
Le 29/11/2018 à 12:25, Aneesh Kumar K.V a écrit : On 11/16/18 10:50 PM, Christophe Leroy wrote: The 603 doesn't have a HASH table, TLB misses are handled by software. It is then possible to generate page fault when _PAGE_EXEC is not set like in nohash/32. In order to support it,

Re: use generic DMA mapping code in powerpc V4

2018-11-29 Thread Christian Zigotzky
On 28 November 2018 at 12:05PM, Michael Ellerman wrote: Christoph Hellwig writes: Any comments? I'd like to at least get the ball moving on the easy bits. Nothing specific yet. I'm a bit worried it might break one of the many old obscure platforms we have that aren't well tested. There's

Re: [PATCH] powerpc/boot: Copy serial.c in Makefile

2018-11-29 Thread Daniel Axtens
Hi mpe, >> Further analysis suggests that making with -j1 triggers the issue, but >> everything works with -j2 and above. That would make sense with the >> timeline of when I discovered the issue because I changed my build >> script to not build in parallel. > > I don't get why -j makes a

Re: pkeys: Reserve PKEY_DISABLE_READ

2018-11-29 Thread Florian Weimer
* Dave Hansen: > On 11/27/18 3:57 AM, Florian Weimer wrote: >> I would have expected something that translates PKEY_DISABLE_WRITE | >> PKEY_DISABLE_READ into PKEY_DISABLE_ACCESS, and also accepts >> PKEY_DISABLE_ACCESS | PKEY_DISABLE_READ, for consistency with POWER. >> >> (My understanding is

Re: [PATCH] powerpc/mm: add exec protection on powerpc 603

2018-11-29 Thread Aneesh Kumar K.V
On 11/16/18 10:50 PM, Christophe Leroy wrote: The 603 doesn't have a HASH table, TLB misses are handled by software. It is then possible to generate page fault when _PAGE_EXEC is not set like in nohash/32. In order to support it, set_pte_filter() and set_access_flags_filter() are made common,

Re: [PATCH] powerpc/boot: Copy serial.c in Makefile

2018-11-29 Thread Michael Ellerman
Hi dja, Daniel Axtens writes: > Right, so as both 0-day and snowpatch tell me, this patch is wrong. > > It turns out that this: >> $(obj)/serial.c: $(obj)/autoconf.h >> +$(Q)cp $< $@ > is identical to: > cp arch/powerpc/boot/autoconf.h arch/powerpc/boot/serial.c > > (Clearly my make mastery

Re: [PATCH v3 0/4] powerpc: system call table generation support

2018-11-29 Thread Firoz Khan
++ sathn...@linux.vnet.ibm.com On Thu, 29 Nov 2018 at 09:57, Firoz Khan wrote: > > The purpose of this patch series is, we can easily > add/modify/delete system call table support by cha- > nging entry in syscall.tbl file instead of manually > changing many files. The other goal is to unify the

Re: [PATCH 0/3] System call table generation support

2018-11-29 Thread Firoz Khan
Hi Sathish, Thanks for your email. On Thu, 29 Nov 2018 at 12:05, Satheesh Rajendran wrote: > > On Fri, Sep 14, 2018 at 02:02:57PM +0530, Firoz Khan wrote: > > The purpose of this patch series is: > > 1. We can easily add/modify/delete system call by changing entry > > in syscall.tbl file. No

[PATCH v8 20/20] powerpc/8xx: regroup TLB handler routines

2018-11-29 Thread Christophe Leroy
As this is running with MMU off, the CPU only does speculative fetch for code in the same page. Following the significant size reduction of TLB handler routines, the side handlers can be brought back close to the main part, ie in the same page. Signed-off-by: Christophe Leroy ---

[PATCH v8 19/20] powerpc/8xx: don't use r12/SPRN_SPRG_SCRATCH2 in TLB Miss handlers

2018-11-29 Thread Christophe Leroy
This patch reworks the TLB Miss handler in order to not use r12 register, hence avoiding having to save it into SPRN_SPRG_SCRATCH2. In the DAR Fixup code we can now use SPRN_M_TW, freeing SPRN_SPRG_SCRATCH2. Then SPRN_SPRG_SCRATCH2 may be used for something else in the future. Signed-off-by:

[PATCH v8 18/20] powerpc/8xx: reintroduce 16K pages with HW assistance

2018-11-29 Thread Christophe Leroy
Using this HW assistance implies some constraints on the page table structure: - Regardless of the main page size used (4k or 16k), the level 1 table (PGD) contains 1024 entries and each PGD entry covers a 4Mbytes area which is managed by a level 2 table (PTE) containing also 1024 entries each

[PATCH v8 17/20] powerpc/8xx: Enable 512k hugepage support with HW assistance

2018-11-29 Thread Christophe Leroy
For using 512k pages with hardware assistance, the PTEs have to be spread every 128 bytes in the L2 table. Signed-off-by: Christophe Leroy --- arch/powerpc/include/asm/hugetlb.h | 4 +++- arch/powerpc/mm/hugetlbpage.c | 10 +- arch/powerpc/mm/tlb_nohash.c | 3 +++ 3 files

[PATCH v8 16/20] powerpc/8xx: Enable 8M hugepage support with HW assistance

2018-11-29 Thread Christophe Leroy
HW assistance naturally supports 8M huge pages without further modifications. Signed-off-by: Christophe Leroy --- arch/powerpc/mm/tlb_nohash.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/powerpc/mm/tlb_nohash.c b/arch/powerpc/mm/tlb_nohash.c index 4f79639e432f..8ad7aab150b7

[PATCH v8 15/20] powerpc/8xx: Use hardware assistance in TLB handlers

2018-11-29 Thread Christophe Leroy
Today, on the 8xx the TLB handlers do SW tablewalk by doing all the calculation in ASM, in order to match with the Linux page table structure. The 8xx offers hardware assistance which allows significant size reduction of the TLB handlers, hence also reduces the time spent in the handlers.

[PATCH v8 14/20] powerpc/8xx: Temporarily disable 16k pages and hugepages

2018-11-29 Thread Christophe Leroy
In preparation of making use of hardware assistance in TLB handlers, this patch temporarily disables 16K pages and hugepages. The reason is that when using HW assistance in 4K pages mode, the linux model fit with the HW model for 4K pages and 8M pages. However for 16K pages and 512K mode some

[PATCH v8 13/20] powerpc/8xx: Move SW perf counters in first 32kb of memory

2018-11-29 Thread Christophe Leroy
In order to simplify time critical exceptions handling 8xx specific SW perf counters, this patch moves the counters into the beginning of memory. This is possible because .text is readable and the counters are never modified outside of the handlers. By doing this, we avoid having to set a second

[PATCH v8 12/20] powerpc/mm: remove unnecessary test in pgtable_cache_init()

2018-11-29 Thread Christophe Leroy
pgtable_cache_add() gracefully handles the case when a cache that size already exists by returning early with the following test: if (PGT_CACHE(shift)) return; /* Already have a cache of this size */ It is then not needed to test the existence of the cache before.

[PATCH v8 11/20] powerpc/mm: fix a warning when a cache is common to PGD and hugepages

2018-11-29 Thread Christophe Leroy
While implementing TLB miss HW assistance on the 8xx, the following warning was encountered: [ 423.732965] WARNING: CPU: 0 PID: 345 at mm/slub.c:2412 ___slab_alloc.constprop.30+0x26c/0x46c [ 423.733033] CPU: 0 PID: 345 Comm: mmap Not tainted 4.18.0-rc8-00664-g2dfff9121c55 #671 [ 423.733075]

[PATCH v8 10/20] powerpc/mm: replace hugetlb_cache by PGT_CACHE(PTE_T_ORDER)

2018-11-29 Thread Christophe Leroy
Instead of opencoding cache handling for the special case of hugepage tables having a single pte_t element, this patch makes use of the common pgtable_cache helpers Signed-off-by: Christophe Leroy --- arch/powerpc/include/asm/hugetlb.h | 2 -- arch/powerpc/mm/hugetlbpage.c | 26

[PATCH v8 09/20] powerpc/mm: enable the use of page table cache of order 0

2018-11-29 Thread Christophe Leroy
hugepages uses a cache of order 0. Lets allow page tables of order 0 in the common part in order to avoid open coding in hugetlb Signed-off-by: Christophe Leroy --- arch/powerpc/include/asm/book3s/32/pgalloc.h | 5 + arch/powerpc/include/asm/book3s/64/pgalloc.h | 5 +

[PATCH v8 08/20] powerpc/mm: Extend pte_fragment functionality to PPC32

2018-11-29 Thread Christophe Leroy
In order to allow the 8xx to handle pte_fragments, this patch extends the use of pte_fragments to PPC32 platforms. Signed-off-by: Christophe Leroy --- arch/powerpc/include/asm/book3s/32/mmu-hash.h | 5 - arch/powerpc/include/asm/book3s/32/pgalloc.h | 17 +

[PATCH v8 07/20] powerpc/mm: add helpers to get/set mm.context->pte_frag

2018-11-29 Thread Christophe Leroy
In order to handle pte_fragment functions with single fragment without adding pte_frag in all mm_context_t, this patch creates two helpers which do nothing on platforms using a single fragment. Signed-off-by: Christophe Leroy --- arch/powerpc/include/asm/pgtable.h | 31

[PATCH v8 06/20] powerpc/mm: Move pgtable_t into platform headers

2018-11-29 Thread Christophe Leroy
This patch move pgtable_t into platform headers. It gets rid of the CONFIG_PPC_64K_PAGES case for PPC64 as nohash/64 doesn't support CONFIG_PPC_64K_PAGES. Reviewed-by: Aneesh Kumar K.V Signed-off-by: Christophe Leroy --- arch/powerpc/include/asm/book3s/32/mmu-hash.h | 2 ++

[PATCH v8 05/20] powerpc/mm: move platform specific mmu-xxx.h in platform directories

2018-11-29 Thread Christophe Leroy
The purpose of this patch is to move platform specific mmu-xxx.h files in platform directories like pte-xxx.h files. In the meantime this patch creates common nohash and nohash/32 + nohash/64 mmu.h files for future common parts. Reviewed-by: Aneesh Kumar K.V Signed-off-by: Christophe Leroy ---

[PATCH v8 04/20] powerpc/mm: Avoid useless lock with single page fragments

2018-11-29 Thread Christophe Leroy
There is no point in taking the page table lock as pte_frag or pmd_frag are always NULL when we have only one fragment. Reviewed-by: Aneesh Kumar K.V Signed-off-by: Christophe Leroy --- arch/powerpc/mm/pgtable-book3s64.c | 3 +++ arch/powerpc/mm/pgtable-frag.c | 3 +++ 2 files changed, 6

[PATCH v8 03/20] powerpc/mm: Move pte_fragment_alloc() to a common location

2018-11-29 Thread Christophe Leroy
In preparation of next patch which generalises the use of pte_fragment_alloc() for all, this patch moves the related functions in a place that is common to all subarches. The 8xx will need that for supporting 16k pages, as in that mode page tables still have a size of 4k. Since pte_fragment with

[PATCH v8 02/20] powerpc/8xx: Remove PTE_ATOMIC_UPDATES

2018-11-29 Thread Christophe Leroy
commit 1bc54c03117b9 ("powerpc: rework 4xx PTE access and TLB miss") introduced non atomic PTE updates and started the work of removing PTE updates in TLB miss handlers, but kept PTE_ATOMIC_UPDATES for the 8xx with the following comment: /* Until my rework is finished, 8xx still needs atomic PTE

[PATCH v8 01/20] powerpc/book3s32: Remove CONFIG_BOOKE dependent code

2018-11-29 Thread Christophe Leroy
BOOK3S/32 cannot be BOOKE, so remove useless code Signed-off-by: Christophe Leroy --- arch/powerpc/include/asm/book3s/32/pgalloc.h | 18 -- arch/powerpc/include/asm/book3s/32/pgtable.h | 14 -- 2 files changed, 32 deletions(-) diff --git

[PATCH v8 00/20] Implement use of HW assistance on TLB table walk on 8xx

2018-11-29 Thread Christophe Leroy
The purpose of this serie is to implement hardware assistance for TLB table walk on the 8xx. First part prepares for using HW assistance in TLB routines: - Trivial fixes: - Remove CONFIG_BOOKE stuff from book3S headers. - Removal of unneeded atomic PTE update requirement for 8xx.