[PATCH kernel v3] powerpc/powernv: Isolate NVLinks between GV100GL on Witherspoon
The NVIDIA V100 SXM2 GPUs are connected to the CPU via PCIe links and
(on POWER9) NVLinks. In addition to that, GPUs themselves have direct
peer-to-peer NVLinks in groups of 2 to 4 GPUs with no buffers/latches
between GPUs.
Because of these interconnected NVLinks, the POWERNV platform puts such
interconnected GPUs to the same IOMMU group. However users want to pass
GPUs through individually which requires separate IOMMU groups.
Thankfully V100 GPUs implement an interface to disable arbitrary links
by programming link disabling mask via the GPU's BAR0. Once a link is
disabled, it only can be enabled after performing the secondary bus reset
(SBR) on the GPU. Since these GPUs do not advertise any other type of
reset, it is reset by the platform's SBR handler.
This adds an extra step to the POWERNV's SBR handler to block NVLinks to
GPUs which do not belong to the same group as the GPU being reset.
This adds a new "isolate_nvlink" kernel parameter to force GPU isolation;
when enabled, every GPU gets placed in its own IOMMU group. The new
parameter is off by default to preserve the existing behaviour.
Before isolating:
[nvdbg ~]$ nvidia-smi topo -m
GPU0GPU1GPU2CPU Affinity
GPU0 X NV2 NV2 0-0
GPU1NV2 X NV2 0-0
GPU2NV2 NV2 X 0-0
After isolating:
[nvdbg ~]$ nvidia-smi topo -m
GPU0GPU1GPU2CPU Affinity
GPU0 X PHB PHB 0-0
GPU1PHB X PHB 0-0
GPU2PHB PHB X 0-0
Where:
X= Self
PHB = Connection traversing PCIe as well as a PCIe Host Bridge (typically
the CPU)
NV# = Connection traversing a bonded set of # NVLinks
Signed-off-by: Alexey Kardashevskiy
---
Changes:
v3:
* added pci_err() for failed ioremap
* reworked commit log
v2:
* this is rework of [PATCH kernel RFC 0/2] vfio, powerpc/powernv: Isolate
GV100GL
but this time it is contained in the powernv platform
---
arch/powerpc/platforms/powernv/Makefile | 2 +-
arch/powerpc/platforms/powernv/pci.h | 1 +
arch/powerpc/platforms/powernv/eeh-powernv.c | 1 +
arch/powerpc/platforms/powernv/npu-dma.c | 24 +++-
arch/powerpc/platforms/powernv/nvlinkgpu.c | 137 +++
5 files changed, 162 insertions(+), 3 deletions(-)
create mode 100644 arch/powerpc/platforms/powernv/nvlinkgpu.c
diff --git a/arch/powerpc/platforms/powernv/Makefile
b/arch/powerpc/platforms/powernv/Makefile
index da2e99efbd04..60a10d3b36eb 100644
--- a/arch/powerpc/platforms/powernv/Makefile
+++ b/arch/powerpc/platforms/powernv/Makefile
@@ -6,7 +6,7 @@ obj-y += opal-msglog.o opal-hmi.o
opal-power.o opal-irqchip.o
obj-y += opal-kmsg.o opal-powercap.o opal-psr.o
opal-sensor-groups.o
obj-$(CONFIG_SMP) += smp.o subcore.o subcore-asm.o
-obj-$(CONFIG_PCI) += pci.o pci-ioda.o npu-dma.o pci-ioda-tce.o
+obj-$(CONFIG_PCI) += pci.o pci-ioda.o npu-dma.o pci-ioda-tce.o nvlinkgpu.o
obj-$(CONFIG_CXL_BASE) += pci-cxl.o
obj-$(CONFIG_EEH) += eeh-powernv.o
obj-$(CONFIG_PPC_SCOM) += opal-xscom.o
diff --git a/arch/powerpc/platforms/powernv/pci.h
b/arch/powerpc/platforms/powernv/pci.h
index 8e36da379252..9fd3f391482c 100644
--- a/arch/powerpc/platforms/powernv/pci.h
+++ b/arch/powerpc/platforms/powernv/pci.h
@@ -250,5 +250,6 @@ extern void pnv_pci_unlink_table_and_group(struct
iommu_table *tbl,
extern void pnv_pci_setup_iommu_table(struct iommu_table *tbl,
void *tce_mem, u64 tce_size,
u64 dma_offset, unsigned int page_shift);
+extern void pnv_try_isolate_nvidia_v100(struct pci_dev *gpdev);
#endif /* __POWERNV_PCI_H */
diff --git a/arch/powerpc/platforms/powernv/eeh-powernv.c
b/arch/powerpc/platforms/powernv/eeh-powernv.c
index f38078976c5d..464b097d9635 100644
--- a/arch/powerpc/platforms/powernv/eeh-powernv.c
+++ b/arch/powerpc/platforms/powernv/eeh-powernv.c
@@ -937,6 +937,7 @@ void pnv_pci_reset_secondary_bus(struct pci_dev *dev)
pnv_eeh_bridge_reset(dev, EEH_RESET_HOT);
pnv_eeh_bridge_reset(dev, EEH_RESET_DEACTIVATE);
}
+ pnv_try_isolate_nvidia_v100(dev);
}
static void pnv_eeh_wait_for_pending(struct pci_dn *pdn, const char *type,
diff --git a/arch/powerpc/platforms/powernv/npu-dma.c
b/arch/powerpc/platforms/powernv/npu-dma.c
index dc23d9d2a7d9..d4f9ee6222b5 100644
--- a/arch/powerpc/platforms/powernv/npu-dma.c
+++ b/arch/powerpc/platforms/powernv/npu-dma.c
@@ -22,6 +22,23 @@
#include "pci.h"
+static bool isolate_nvlink;
+
+static int __init parse_isolate_nvlink(char *p)
+{
+ bool val;
+
+ if (!p)
+ val = true;
+ else if (kstrtobool(p, &val))
+ return -EINVAL;
+
+ isolate_nvlink = val;
+
+ return 0;
+}
+early_param("isolate_nvlink", parse_isolate_nvlink);
+
/*
* spinlock to protect initialisation of an npu_context for a particular
* mm_struct.
@@ -549,7 +566,7 @@ struct iommu_table_group
*pnv_try_setup_npu
Re: [alsa-devel] [PATCH V4] ASoC: fsl_esai: Fix missing break in switch statement
Hi Shengjiu,
On Thu, Apr 11, 2019 at 6:06 AM S.j. Wang wrote:
>
> case ESAI_HCKT_EXTAL and case ESAI_HCKR_EXTAL should be
> independent of each other, so replace fall-through with break.
>
> Fixes: 43d24e76b698 ("ASoC: fsl_esai: Add ESAI CPU DAI driver")
>
Since it is obvious that you will need to send v5 please remove the new line
between Fixes and Signed-off-by. This is a common practice and some tools
might depend on this to parse the Fixes tag.
> Signed-off-by: Shengjiu Wang
> Acked-by: Nicolin Chen
> Cc:
Re: [PATCH v5 16/16] KVM: PPC: Book3S HV: XIVE: introduce a 'release' device operation
On 4/11/19 6:38 AM, David Gibson wrote:
> On Thu, Apr 11, 2019 at 01:16:25PM +1000, Paul Mackerras wrote:
>> On Wed, Apr 10, 2019 at 07:04:48PM +0200, Cédric Le Goater wrote:
>>> When a P9 sPAPR VM boots, the CAS negotiation process determines which
>>> interrupt mode to use (XICS legacy or XIVE native) and invokes a
>>> machine reset to activate the chosen mode.
>>>
>>> To be able to switch from one mode to another, we introduce the
>>> capability to release a KVM device without destroying the VM. The KVM
>>> device interface is extended with a new 'release' operation which is
>>> called when the file descriptor of the device is closed.
>>
>> I believe the release operation is not called until all of the mmaps
>> using the fd are unmapped - which is a good thing for us, since it
>> means the guest can't possibly be accessing the XIVE directly.
yes.
>> You might want to reword that last paragraph to mention that.
ok.
>>> Such operations are defined for the XICS-on-XIVE and the XIVE native
>>> KVM devices. They clear the vCPU interrupt presenters that could be
>>> attached and then destroy the device.
>>>
>>> This is not considered as a safe operation as the vCPUs are still
>>> running and could be referencing the KVM device through their
>>> presenters. To protect the system from any breakage, the kvmppc_xive
>>> objects representing both KVM devices are now stored in an array under
>>> the VM. Allocation is performed on first usage and memory is freed
>>> only when the VM exits.
>>
>> One quick comment below:
>>
>>> diff --git a/arch/powerpc/kvm/book3s_xive.c b/arch/powerpc/kvm/book3s_xive.c
>>> index 480a3fc6b9fd..064a9f2ae678 100644
>>> --- a/arch/powerpc/kvm/book3s_xive.c
>>> +++ b/arch/powerpc/kvm/book3s_xive.c
>>> @@ -1100,11 +1100,19 @@ void kvmppc_xive_disable_vcpu_interrupts(struct
>>> kvm_vcpu *vcpu)
>>> void kvmppc_xive_cleanup_vcpu(struct kvm_vcpu *vcpu)
>>> {
>>> struct kvmppc_xive_vcpu *xc = vcpu->arch.xive_vcpu;
>>> - struct kvmppc_xive *xive = xc->xive;
>>> + struct kvmppc_xive *xive;
>>> int i;
>>>
>>> + if (!kvmppc_xics_enabled(vcpu))
>>> + return;
>>
>> Should that be kvmppc_xive_enabled() rather than xics?
>
> I think I asked that on an earlier iteration, and the answer is no.
> The names are confusing, but this file is all about xics-on-xive
> rather than xive native. So here we're checking what's available from
> the guest's point of view, so "xics", but most of the surrounding
> functions are named "xive" because that's the backend.
>
yes.
The relevant part is at the end of the kvmppc_xive_connect_vcpu() routine :
int kvmppc_xive_connect_vcpu(struct kvm_device *dev,
struct kvm_vcpu *vcpu, u32 cpu)
{
...
vcpu->arch.irq_type = KVMPPC_IRQ_XICS;
return 0;
}
David suggested a few cleanups that we could do in the xics-on-xive
device. We might want to introduce a KVMPPC_IRQ_XICS_ON_XIVE flag also.
First, I would like to get rid of references to the kvmppc_xive struct
and remove some useless attributes to improve locking.
Once the XIVE native mode is merged, all kernels above 4.14 running on
a P9 sPAPR guest will switch to XIVE and the xics-on-xive device will
only be useful for nested.
C.
Re: [PATCH v1 03/27] powerpc/mm: don't BUG() in slice_mask_for_size()
Christophe Leroy writes: > When no mask is found for the page size, WARN() and return NULL > instead of BUG()ing. > > Signed-off-by: Christophe Leroy > --- > arch/powerpc/mm/slice.c | 6 -- > 1 file changed, 4 insertions(+), 2 deletions(-) > > diff --git a/arch/powerpc/mm/slice.c b/arch/powerpc/mm/slice.c > index aec91dbcdc0b..011d470ea340 100644 > --- a/arch/powerpc/mm/slice.c > +++ b/arch/powerpc/mm/slice.c > @@ -165,7 +165,8 @@ static struct slice_mask *slice_mask_for_size(struct > mm_struct *mm, int psize) > if (psize == MMU_PAGE_16G) > return &mm->context.mask_16g; > #endif > - BUG(); > + WARN_ON(true); > + return NULL; > } Same here. There are not catching runtime errors. We should never find that true. This is to catch mistakes during development changes. Switch to VM_BUG_ON? > #elif defined(CONFIG_PPC_8xx) > static struct slice_mask *slice_mask_for_size(struct mm_struct *mm, int > psize) > @@ -178,7 +179,8 @@ static struct slice_mask *slice_mask_for_size(struct > mm_struct *mm, int psize) > if (psize == MMU_PAGE_8M) > return &mm->context.mask_8m; > #endif > - BUG(); > + WARN_ON(true); > + return NULL; > } > #else > #error "Must define the slice masks for page sizes supported by the platform" > -- > 2.13.3
Re: [PATCH v1 02/27] powerpc/mm: don't BUG in add_huge_page_size()
Christophe Leroy writes: > No reason to BUG() in add_huge_page_size(). Just WARN and > reject the add. > > Signed-off-by: Christophe Leroy > --- > arch/powerpc/mm/hugetlbpage.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/arch/powerpc/mm/hugetlbpage.c b/arch/powerpc/mm/hugetlbpage.c > index 9e732bb2c84a..cf2978e235f3 100644 > --- a/arch/powerpc/mm/hugetlbpage.c > +++ b/arch/powerpc/mm/hugetlbpage.c > @@ -634,7 +634,8 @@ static int __init add_huge_page_size(unsigned long long > size) > } > #endif > > - BUG_ON(mmu_psize_defs[mmu_psize].shift != shift); > + if (WARN_ON(mmu_psize_defs[mmu_psize].shift != shift)) > + return -EINVAL; Same here. There are not catching runtime errors. We should never find that true. This is to catch mistakes during development changes. Switch to VM_BUG_ON? > > /* Return if huge page size has already been setup */ > if (size_to_hstate(size)) > -- > 2.13.3
Re: [PATCH v1 01/27] powerpc/mm: Don't BUG() in hugepd_page()
Christophe Leroy writes:
> Don't BUG(), just warn and return NULL.
> If the NULL value is not handled, it will get catched anyway.
>
> Signed-off-by: Christophe Leroy
> ---
> arch/powerpc/include/asm/hugetlb.h | 6 --
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/arch/powerpc/include/asm/hugetlb.h
> b/arch/powerpc/include/asm/hugetlb.h
> index 8d40565ad0c3..48c29686c78e 100644
> --- a/arch/powerpc/include/asm/hugetlb.h
> +++ b/arch/powerpc/include/asm/hugetlb.h
> @@ -14,7 +14,8 @@
> */
> static inline pte_t *hugepd_page(hugepd_t hpd)
> {
> - BUG_ON(!hugepd_ok(hpd));
> + if (WARN_ON(!hugepd_ok(hpd)))
> + return NULL;
We should not find that true. That BUG_ON was there to catch errors
when changing pte formats. May be switch that VM_BUG_ON()?
> /*
>* We have only four bits to encode, MMU page size
>*/
> @@ -42,7 +43,8 @@ static inline void flush_hugetlb_page(struct vm_area_struct
> *vma,
>
> static inline pte_t *hugepd_page(hugepd_t hpd)
> {
> - BUG_ON(!hugepd_ok(hpd));
> + if (WARN_ON(!hugepd_ok(hpd)))
> + return NULL;
> #ifdef CONFIG_PPC_8xx
> return (pte_t *)__va(hpd_val(hpd) & ~HUGEPD_SHIFT_MASK);
> #else
> --
> 2.13.3
Re: [PATCH v1 06/15] powerpc/Kconfig: select PPC_MM_SLICES from subarch type
Aneesh Kumar K.V writes: > Christophe Leroy writes: > >> Lets select PPC_MM_SLICES from the subarch config item instead of >> doing it via defaults declaration in the PPC_MM_SLICES item itself. >> > > Did we miss the book3s 64 default y here? > >> Signed-off-by: Christophe Leroy >> --- >> arch/powerpc/platforms/Kconfig.cputype | 4 ++-- >> 1 file changed, 2 insertions(+), 2 deletions(-) >> >> diff --git a/arch/powerpc/platforms/Kconfig.cputype >> b/arch/powerpc/platforms/Kconfig.cputype >> index 842b2c7e156a..a46a0adb634d 100644 >> --- a/arch/powerpc/platforms/Kconfig.cputype >> +++ b/arch/powerpc/platforms/Kconfig.cputype >> @@ -34,6 +34,7 @@ config PPC_8xx >> bool "Freescale 8xx" >> select FSL_SOC >> select SYS_SUPPORTS_HUGETLBFS >> +select PPC_MM_SLICES if HUGETLB_PAGE >> >> config 40x >> bool "AMCC 40x" >> @@ -75,6 +76,7 @@ config PPC_BOOK3S_64 >> select ARCH_ENABLE_THP_MIGRATION if TRANSPARENT_HUGEPAGE >> select ARCH_SUPPORTS_NUMA_BALANCING >> select IRQ_WORK >> +select PPC_MM_SLICES ok this takes care of BOOK3S_64. >> >> config PPC_BOOK3E_64 >> bool "Embedded processors" >> @@ -360,8 +362,6 @@ config PPC_BOOK3E_MMU >> >> config PPC_MM_SLICES >> bool >> -default y if PPC_BOOK3S_64 >> -default y if PPC_8xx && HUGETLB_PAGE >> >> config PPC_HAVE_PMU_SUPPORT >> bool >> -- >> 2.13.3
Re: [PATCH v1 00/15] Refactor pgalloc stuff
Christophe Leroy writes: > This series converts book3e64 to pte_fragment and refactor > things that are common among subarches. > > Christophe Leroy (15): > powerpc/mm: drop __bad_pte() > powerpc/mm: define __pud_free_tlb() at all time on nohash/64 > powerpc/mm: convert Book3E 64 to pte_fragment > powerpc/mm: move pgtable_t in asm/mmu.h > powerpc/mm: get rid of nohash/32/mmu.h and nohash/64/mmu.h > powerpc/Kconfig: select PPC_MM_SLICES from subarch type > powerpc/book3e: move early_alloc_pgtable() to init section > powerpc/mm: don't use pte_alloc_kernel() until slab is available on > PPC32 > powerpc/mm: inline pte_alloc_one_kernel() and pte_alloc_one() on PPC32 > powerpc/mm: refactor pte_alloc_one() and pte_free() families > definition. > powerpc/mm: refactor definition of pgtable_cache[] > powerpc/mm: Only keep one version of pmd_populate() functions on > nohash/32 > powerpc/mm: refactor pgtable freeing functions on nohash > powerpc/mm: refactor pmd_pgtable() > powerpc/mm: refactor pgd_alloc() and pgd_free() on nohash > > arch/powerpc/include/asm/book3s/32/mmu-hash.h | 4 - > arch/powerpc/include/asm/book3s/32/pgalloc.h | 41 - > arch/powerpc/include/asm/book3s/64/mmu.h | 8 -- > arch/powerpc/include/asm/book3s/64/pgalloc.h | 49 -- > arch/powerpc/include/asm/mmu.h| 3 + > arch/powerpc/include/asm/mmu_context.h| 6 -- > arch/powerpc/include/asm/nohash/32/mmu.h | 25 -- > arch/powerpc/include/asm/nohash/32/pgalloc.h | 123 > ++ > arch/powerpc/include/asm/nohash/64/mmu.h | 12 --- > arch/powerpc/include/asm/nohash/64/pgalloc.h | 117 +--- > arch/powerpc/include/asm/nohash/mmu.h | 16 +++- > arch/powerpc/include/asm/nohash/pgalloc.h | 56 > arch/powerpc/include/asm/pgalloc.h| 51 +++ > arch/powerpc/mm/Makefile | 4 +- > arch/powerpc/mm/mmu_context.c | 2 +- > arch/powerpc/mm/pgtable-book3e.c | 4 +- > arch/powerpc/mm/pgtable_32.c | 42 + > arch/powerpc/platforms/Kconfig.cputype| 4 +- > 18 files changed, 165 insertions(+), 402 deletions(-) > delete mode 100644 arch/powerpc/include/asm/nohash/32/mmu.h > delete mode 100644 arch/powerpc/include/asm/nohash/64/mmu.h > > -- > 2.13.3 Looks good. You can add for the series Reviewed-by: Aneesh Kumar K.V
Re: [PATCH v1 06/15] powerpc/Kconfig: select PPC_MM_SLICES from subarch type
Christophe Leroy writes: > Lets select PPC_MM_SLICES from the subarch config item instead of > doing it via defaults declaration in the PPC_MM_SLICES item itself. > Did we miss the book3s 64 default y here? > Signed-off-by: Christophe Leroy > --- > arch/powerpc/platforms/Kconfig.cputype | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/powerpc/platforms/Kconfig.cputype > b/arch/powerpc/platforms/Kconfig.cputype > index 842b2c7e156a..a46a0adb634d 100644 > --- a/arch/powerpc/platforms/Kconfig.cputype > +++ b/arch/powerpc/platforms/Kconfig.cputype > @@ -34,6 +34,7 @@ config PPC_8xx > bool "Freescale 8xx" > select FSL_SOC > select SYS_SUPPORTS_HUGETLBFS > + select PPC_MM_SLICES if HUGETLB_PAGE > > config 40x > bool "AMCC 40x" > @@ -75,6 +76,7 @@ config PPC_BOOK3S_64 > select ARCH_ENABLE_THP_MIGRATION if TRANSPARENT_HUGEPAGE > select ARCH_SUPPORTS_NUMA_BALANCING > select IRQ_WORK > + select PPC_MM_SLICES > > config PPC_BOOK3E_64 > bool "Embedded processors" > @@ -360,8 +362,6 @@ config PPC_BOOK3E_MMU > > config PPC_MM_SLICES > bool > - default y if PPC_BOOK3S_64 > - default y if PPC_8xx && HUGETLB_PAGE > > config PPC_HAVE_PMU_SUPPORT > bool > -- > 2.13.3
[PATCH] MAINTAINERS: Update remaining @linux.vnet.ibm.com addresses
Paul McKenney attempted to update all email addresses @linux.vnet.ibm.com
to @linux.ibm.com in commit 1dfddcdb95c4
("MAINTAINERS: Update from @linux.vnet.ibm.com to @linux.ibm.com"), but
some still remained.
We update the remaining email addresses in MAINTAINERS, hopefully finally
catching all cases for good.
Fixes: 1dfddcdb95c4 ("MAINTAINERS: Update from @linux.vnet.ibm.com to
@linux.ibm.com")
Signed-off-by: Lukas Bulwahn
---
Tyrel, please take this patch. Thanks.
MAINTAINERS | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 2359e12e4c41..454b3cf36aa4 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -7439,14 +7439,14 @@ F: drivers/crypto/vmx/ghash*
F: drivers/crypto/vmx/ppc-xlate.pl
IBM Power PCI Hotplug Driver for RPA-compliant PPC64 platform
-M: Tyrel Datwyler
+M: Tyrel Datwyler
L: linux-...@vger.kernel.org
L: linuxppc-dev@lists.ozlabs.org
S: Supported
F: drivers/pci/hotplug/rpaphp*
IBM Power IO DLPAR Driver for RPA-compliant PPC64 platform
-M: Tyrel Datwyler
+M: Tyrel Datwyler
L: linux-...@vger.kernel.org
L: linuxppc-dev@lists.ozlabs.org
S: Supported
@@ -10388,7 +10388,7 @@ F: arch/arm/mach-mmp/
MMU GATHER AND TLB INVALIDATION
M: Will Deacon
-M: "Aneesh Kumar K.V"
+M: "Aneesh Kumar K.V"
M: Andrew Morton
M: Nick Piggin
M: Peter Zijlstra
--
2.17.1
Re: [PATCH v5 16/16] KVM: PPC: Book3S HV: XIVE: introduce a 'release' device operation
On Thu, Apr 11, 2019 at 01:16:25PM +1000, Paul Mackerras wrote:
> On Wed, Apr 10, 2019 at 07:04:48PM +0200, Cédric Le Goater wrote:
> > When a P9 sPAPR VM boots, the CAS negotiation process determines which
> > interrupt mode to use (XICS legacy or XIVE native) and invokes a
> > machine reset to activate the chosen mode.
> >
> > To be able to switch from one mode to another, we introduce the
> > capability to release a KVM device without destroying the VM. The KVM
> > device interface is extended with a new 'release' operation which is
> > called when the file descriptor of the device is closed.
>
> I believe the release operation is not called until all of the mmaps
> using the fd are unmapped - which is a good thing for us, since it
> means the guest can't possibly be accessing the XIVE directly.
> You might want to reword that last paragraph to mention that.
>
> > Such operations are defined for the XICS-on-XIVE and the XIVE native
> > KVM devices. They clear the vCPU interrupt presenters that could be
> > attached and then destroy the device.
> >
> > This is not considered as a safe operation as the vCPUs are still
> > running and could be referencing the KVM device through their
> > presenters. To protect the system from any breakage, the kvmppc_xive
> > objects representing both KVM devices are now stored in an array under
> > the VM. Allocation is performed on first usage and memory is freed
> > only when the VM exits.
>
> One quick comment below:
>
> > diff --git a/arch/powerpc/kvm/book3s_xive.c b/arch/powerpc/kvm/book3s_xive.c
> > index 480a3fc6b9fd..064a9f2ae678 100644
> > --- a/arch/powerpc/kvm/book3s_xive.c
> > +++ b/arch/powerpc/kvm/book3s_xive.c
> > @@ -1100,11 +1100,19 @@ void kvmppc_xive_disable_vcpu_interrupts(struct
> > kvm_vcpu *vcpu)
> > void kvmppc_xive_cleanup_vcpu(struct kvm_vcpu *vcpu)
> > {
> > struct kvmppc_xive_vcpu *xc = vcpu->arch.xive_vcpu;
> > - struct kvmppc_xive *xive = xc->xive;
> > + struct kvmppc_xive *xive;
> > int i;
> >
> > + if (!kvmppc_xics_enabled(vcpu))
> > + return;
>
> Should that be kvmppc_xive_enabled() rather than xics?
I think I asked that on an earlier iteration, and the answer is no.
The names are confusing, but this file is all about xics-on-xive
rather than xive native. So here we're checking what's available from
the guest's point of view, so "xics", but most of the surrounding
functions are named "xive" because that's the backend.
--
David Gibson| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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Re: [PATCH 1/6] mm: change locked_vm's type from unsigned long to atomic64_t
On 03/04/2019 07:41, Daniel Jordan wrote:
> Taking and dropping mmap_sem to modify a single counter, locked_vm, is
> overkill when the counter could be synchronized separately.
>
> Make mmap_sem a little less coarse by changing locked_vm to an atomic,
> the 64-bit variety to avoid issues with overflow on 32-bit systems.
>
> Signed-off-by: Daniel Jordan
> Cc: Alan Tull
> Cc: Alexey Kardashevskiy
> Cc: Alex Williamson
> Cc: Andrew Morton
> Cc: Benjamin Herrenschmidt
> Cc: Christoph Lameter
> Cc: Davidlohr Bueso
> Cc: Michael Ellerman
> Cc: Moritz Fischer
> Cc: Paul Mackerras
> Cc: Wu Hao
> Cc:
> Cc:
> Cc:
> Cc:
> Cc:
> Cc:
> ---
> arch/powerpc/kvm/book3s_64_vio.c| 14 --
> arch/powerpc/mm/mmu_context_iommu.c | 15 ---
> drivers/fpga/dfl-afu-dma-region.c | 18 ++
> drivers/vfio/vfio_iommu_spapr_tce.c | 17 +
> drivers/vfio/vfio_iommu_type1.c | 10 ++
> fs/proc/task_mmu.c | 2 +-
> include/linux/mm_types.h| 2 +-
> kernel/fork.c | 2 +-
> mm/debug.c | 5 +++--
> mm/mlock.c | 4 ++--
> mm/mmap.c | 18 +-
> mm/mremap.c | 6 +++---
> 12 files changed, 61 insertions(+), 52 deletions(-)
>
> diff --git a/arch/powerpc/kvm/book3s_64_vio.c
> b/arch/powerpc/kvm/book3s_64_vio.c
> index f02b04973710..e7fdb6d10eeb 100644
> --- a/arch/powerpc/kvm/book3s_64_vio.c
> +++ b/arch/powerpc/kvm/book3s_64_vio.c
> @@ -59,32 +59,34 @@ static unsigned long kvmppc_stt_pages(unsigned long
> tce_pages)
> static long kvmppc_account_memlimit(unsigned long stt_pages, bool inc)
> {
> long ret = 0;
> + s64 locked_vm;
>
> if (!current || !current->mm)
> return ret; /* process exited */
>
> down_write(¤t->mm->mmap_sem);
>
> + locked_vm = atomic64_read(¤t->mm->locked_vm);
> if (inc) {
> unsigned long locked, lock_limit;
>
> - locked = current->mm->locked_vm + stt_pages;
> + locked = locked_vm + stt_pages;
> lock_limit = rlimit(RLIMIT_MEMLOCK) >> PAGE_SHIFT;
> if (locked > lock_limit && !capable(CAP_IPC_LOCK))
> ret = -ENOMEM;
> else
> - current->mm->locked_vm += stt_pages;
> + atomic64_add(stt_pages, ¤t->mm->locked_vm);
> } else {
> - if (WARN_ON_ONCE(stt_pages > current->mm->locked_vm))
> - stt_pages = current->mm->locked_vm;
> + if (WARN_ON_ONCE(stt_pages > locked_vm))
> + stt_pages = locked_vm;
>
> - current->mm->locked_vm -= stt_pages;
> + atomic64_sub(stt_pages, ¤t->mm->locked_vm);
> }
>
> pr_debug("[%d] RLIMIT_MEMLOCK KVM %c%ld %ld/%ld%s\n", current->pid,
> inc ? '+' : '-',
> stt_pages << PAGE_SHIFT,
> - current->mm->locked_vm << PAGE_SHIFT,
> + atomic64_read(¤t->mm->locked_vm) << PAGE_SHIFT,
> rlimit(RLIMIT_MEMLOCK),
> ret ? " - exceeded" : "");
>
> diff --git a/arch/powerpc/mm/mmu_context_iommu.c
> b/arch/powerpc/mm/mmu_context_iommu.c
> index e7a9c4f6bfca..8038ac24a312 100644
> --- a/arch/powerpc/mm/mmu_context_iommu.c
> +++ b/arch/powerpc/mm/mmu_context_iommu.c
> @@ -55,30 +55,31 @@ static long mm_iommu_adjust_locked_vm(struct mm_struct
> *mm,
> unsigned long npages, bool incr)
> {
> long ret = 0, locked, lock_limit;
> + s64 locked_vm;
>
> if (!npages)
> return 0;
>
> down_write(&mm->mmap_sem);
> -
> + locked_vm = atomic64_read(&mm->locked_vm);
> if (incr) {
> - locked = mm->locked_vm + npages;
> + locked = locked_vm + npages;
> lock_limit = rlimit(RLIMIT_MEMLOCK) >> PAGE_SHIFT;
> if (locked > lock_limit && !capable(CAP_IPC_LOCK))
> ret = -ENOMEM;
> else
> - mm->locked_vm += npages;
> + atomic64_add(npages, &mm->locked_vm);
> } else {
> - if (WARN_ON_ONCE(npages > mm->locked_vm))
> - npages = mm->locked_vm;
> - mm->locked_vm -= npages;
> + if (WARN_ON_ONCE(npages > locked_vm))
> + npages = locked_vm;
> + atomic64_sub(npages, &mm->locked_vm);
> }
>
> pr_debug("[%d] RLIMIT_MEMLOCK HASH64 %c%ld %ld/%ld\n",
> current ? current->pid : 0,
> incr ? '+' : '-',
> npages << PAGE_SHIFT,
> - mm->locked_vm << PAGE_SHIFT,
> + atomic64_read(&mm->locked_vm) << PAGE_SHIFT,
> rlimit(RLIMIT_MEMLOCK));
> up_write(&mm->mmap_sem);
Re: [PATCH RFC 3/5] powerpc/speculation: Add support for 'cpu_spec_mitigations=' cmdline options
On Wed, Apr 10, 2019 at 04:06:50PM +1000, Michael Ellerman wrote: > Josh Poimboeuf writes: > > Configure powerpc CPU runtime speculation bug mitigations in accordance > > with the 'cpu_spec_mitigations=' cmdline options. This affects > > Meltdown, Spectre v1, Spectre v2, and Speculative Store Bypass. > > > > The default behavior is unchanged. > > > > Signed-off-by: Josh Poimboeuf > > --- > > Documentation/admin-guide/kernel-parameters.txt | 9 + > > arch/powerpc/kernel/security.c | 6 +++--- > > arch/powerpc/kernel/setup_64.c | 2 +- > > 3 files changed, 9 insertions(+), 8 deletions(-) > > > > diff --git a/Documentation/admin-guide/kernel-parameters.txt > > b/Documentation/admin-guide/kernel-parameters.txt > > index 29dc03971630..0e8eae1e8a25 100644 > > --- a/Documentation/admin-guide/kernel-parameters.txt > > +++ b/Documentation/admin-guide/kernel-parameters.txt > > @@ -2552,10 +2552,11 @@ > > > > off > > Disable all speculative CPU mitigations. > > - Equivalent to: nopti [x86] > > + Equivalent to: nopti [x86, powerpc] > > + nospectre_v1 [powerpc] > >nospectre_v2 [x86] > > Not sure if you meant to omit powerpc from nospectre_v2? > > You have patched it in the code below. Oops. I'll update the documentation. > >spectre_v2_user=off [x86] > > - spec_store_bypass_disable=off > > [x86] > > + spec_store_bypass_disable=off > > [x86, powerpc] > >l1tf=off [x86] > > > > auto (default) > > @@ -2568,7 +2569,7 @@ > > Equivalent to: pti=auto [x86] > >spectre_v2=auto [x86] > >spectre_v2_user=auto [x86] > > - spec_store_bypass_disable=auto > > [x86] > > + spec_store_bypass_disable=auto > > [x86, powerpc] > >l1tf=flush [x86] > > > > auto,nosmt > > @@ -2579,7 +2580,7 @@ > > Equivalent to: pti=auto [x86] > >spectre_v2=auto [x86] > >spectre_v2_user=auto [x86] > > - spec_store_bypass_disable=auto > > [x86] > > + spec_store_bypass_disable=auto > > [x86, powerpc] > >l1tf=flush,nosmt [x86] > > > > mminit_loglevel= > > diff --git a/arch/powerpc/kernel/security.c b/arch/powerpc/kernel/security.c > > index b33bafb8fcea..5aed4ad729ba 100644 > > --- a/arch/powerpc/kernel/security.c > > +++ b/arch/powerpc/kernel/security.c > > @@ -57,7 +57,7 @@ void setup_barrier_nospec(void) > > enable = security_ftr_enabled(SEC_FTR_FAVOUR_SECURITY) && > > security_ftr_enabled(SEC_FTR_BNDS_CHK_SPEC_BAR); > > > > - if (!no_nospec) > > + if (!no_nospec && cpu_spec_mitigations != CPU_SPEC_MITIGATIONS_OFF) > > enable_barrier_nospec(enable); > > Adding a wrapper func that checks for CPU_SPEC_MITIGATIONS_OFF would > make these a little less verbose, eg: > > if (!no_nospec && !cpu_spec_mitigations_off()) > enable_barrier_nospec(enable); > > But that's a nitpick. Yes, that would be much nicer. I'll probably do something like that in the next version. Thanks. -- Josh
[PATCH V3] powernv: sensor-groups: Add debugfs file to enable/disable sensor groups
This patch provides support to disable and enable platform specific
sensor groups like performance, utilization and frequency which are
not supported in hwmon.
Signed-off-by: Shilpasri G Bhat
---
Changes from V2:
- Rebase on master
Changes from V1:
- As per Michael Ellerman's suggestion, adding the "enable" files to debugfs.
The original code had been written in mind to accomodate the "enable" file
in the same path as "clear" attribute. As this is not required anymore
the code is cleaned up to bifurcate the functions adding "enable" and
"clear" attribute.
.../powerpc/platforms/powernv/opal-sensor-groups.c | 292 ++---
1 file changed, 194 insertions(+), 98 deletions(-)
diff --git a/arch/powerpc/platforms/powernv/opal-sensor-groups.c
b/arch/powerpc/platforms/powernv/opal-sensor-groups.c
index 1796092..1208538 100644
--- a/arch/powerpc/platforms/powernv/opal-sensor-groups.c
+++ b/arch/powerpc/platforms/powernv/opal-sensor-groups.c
@@ -15,22 +15,21 @@
#include
#include
+#include
#include
-DEFINE_MUTEX(sg_mutex);
+#define SENSOR_GROUPS_DIR_STR "sensor_groups"
static struct kobject *sg_kobj;
-struct sg_attr {
- u32 handle;
- struct kobj_attribute attr;
-};
-
static struct sensor_group {
- char name[20];
+ struct kobj_attribute sattr;
struct attribute_group sg;
- struct sg_attr *sgattrs;
-} *sgs;
+ struct mutex mutex;
+ char name[20];
+ u32 handle;
+ u32 enable;
+} *sgroups;
int sensor_group_enable(u32 handle, bool enable)
{
@@ -60,10 +59,12 @@ int sensor_group_enable(u32 handle, bool enable)
}
EXPORT_SYMBOL_GPL(sensor_group_enable);
-static ssize_t sg_store(struct kobject *kobj, struct kobj_attribute *attr,
- const char *buf, size_t count)
+static ssize_t sgroup_clear_store(struct kobject *kobj,
+ struct kobj_attribute *attr,
+ const char *buf, size_t count)
{
- struct sg_attr *sattr = container_of(attr, struct sg_attr, attr);
+ struct sensor_group *sgroup = container_of(attr, struct sensor_group,
+ sattr);
struct opal_msg msg;
u32 data;
int ret, token;
@@ -81,11 +82,11 @@ static ssize_t sg_store(struct kobject *kobj, struct
kobj_attribute *attr,
return token;
}
- ret = mutex_lock_interruptible(&sg_mutex);
+ ret = mutex_lock_interruptible(&sgroup->mutex);
if (ret)
goto out_token;
- ret = opal_sensor_group_clear(sattr->handle, token);
+ ret = opal_sensor_group_clear(sgroup->handle, token);
switch (ret) {
case OPAL_ASYNC_COMPLETION:
ret = opal_async_wait_response(token, &msg);
@@ -106,135 +107,230 @@ static ssize_t sg_store(struct kobject *kobj, struct
kobj_attribute *attr,
}
out:
- mutex_unlock(&sg_mutex);
+ mutex_unlock(&sgroup->mutex);
out_token:
opal_async_release_token(token);
return ret;
}
-static struct sg_ops_info {
- int opal_no;
- const char *attr_name;
- ssize_t (*store)(struct kobject *kobj, struct kobj_attribute *attr,
- const char *buf, size_t count);
-} ops_info[] = {
- { OPAL_SENSOR_GROUP_CLEAR, "clear", sg_store },
-};
+static int find_nr_groups(struct device_node *sensor_group_node, int opal_no)
+{
+ struct device_node *node;
+ int count = 0;
+
+ for_each_child_of_node(sensor_group_node, node) {
+ u32 sgid, op;
+
+ if (of_device_is_compatible(node, "ibm,opal-sensor"))
+ continue;
+
+ if (of_property_read_u32(node, "ops", &op))
+ continue;
+
+ if (op != opal_no)
+ continue;
+
+ if (of_property_read_u32(node, "sensor-group-id", &sgid))
+ continue;
+ count++;
+ }
-static void add_attr(int handle, struct sg_attr *attr, int index)
+ return count;
+}
+
+#ifdef CONFIG_DEBUG_FS
+static int sgroup_enable_get(void *data, u64 *val)
{
- attr->handle = handle;
- sysfs_attr_init(&attr->attr.attr);
- attr->attr.attr.name = ops_info[index].attr_name;
- attr->attr.attr.mode = 0220;
- attr->attr.store = ops_info[index].store;
+ struct sensor_group *sgroup = (struct sensor_group *)data;
+ int rc;
+
+ rc = mutex_lock_interruptible(&sgroup->mutex);
+ if (rc)
+ return rc;
+
+ *val = sgroup->enable;
+ mutex_unlock(&sgroup->mutex);
+
+ return 0;
}
-static int add_attr_group(const __be32 *ops, int len, struct sensor_group *sg,
- u32 handle)
+static int sgroup_enable_set(void *data, u64 val)
{
- int i, j;
- int count = 0;
+ struct sensor_group *sgroup = (struct sensor_group *)data;
+ int rc;
+
+ if
Re: [PATCH V4] ASoC: fsl_esai: Fix missing break in switch statement
On 4/10/19 10:24 PM, Gustavo A. R. Silva wrote:
> [+cc lkml]
>
> On 4/10/19 10:05 PM, S.j. Wang wrote:
>> case ESAI_HCKT_EXTAL and case ESAI_HCKR_EXTAL should be
>> independent of each other, so replace fall-through with break.
>>
>> Fixes: 43d24e76b698 ("ASoC: fsl_esai: Add ESAI CPU DAI driver")
>>
>> Signed-off-by: Shengjiu Wang
>> Acked-by: Nicolin Chen
>> Cc:
>> ---
>> Change in v4
>> - Add Acked-by and cc stable
>> - change the subject
>>
>
> You should preserve the changelog of what has changed in each version, not
> only
> the last changes, so that there is a logical flow and the maintainers do not
> have to dig up previous versions:
>
> Changes in v3:
> - Update subject line.
>
> Changes in v2:
> - Fix "Fixes" tag.
>
>
> Also, for this type of fixes, make sure to always Cc lkml:
> linux-ker...@vger.kernel.org
>
See, these are all the people and lists you should Cc:
$ scripts/get_maintainer.pl --nokeywords --nogit --nogit-fallback -f
sound/soc/fsl/fsl_esai.c
Timur Tabi (maintainer:FREESCALE SOC SOUND DRIVERS)
Nicolin Chen (maintainer:FREESCALE SOC SOUND DRIVERS)
Xiubo Li (maintainer:FREESCALE SOC SOUND DRIVERS)
Fabio Estevam (reviewer:FREESCALE SOC SOUND DRIVERS)
Liam Girdwood (supporter:SOUND - SOC LAYER / DYNAMIC
AUDIO POWER MANAGEM...)
Mark Brown (supporter:SOUND - SOC LAYER / DYNAMIC AUDIO
POWER MANAGEM...)
Jaroslav Kysela (maintainer:SOUND)
Takashi Iwai (maintainer:SOUND)
alsa-de...@alsa-project.org (moderated list:FREESCALE SOC SOUND DRIVERS)
linuxppc-dev@lists.ozlabs.org (open list:FREESCALE SOC SOUND DRIVERS)
linux-ker...@vger.kernel.org (open list)
Thanks
--
Gustavo
>
>> sound/soc/fsl/fsl_esai.c | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/sound/soc/fsl/fsl_esai.c b/sound/soc/fsl/fsl_esai.c
>> index 3623aa9a6f2e..15202a637197 100644
>> --- a/sound/soc/fsl/fsl_esai.c
>> +++ b/sound/soc/fsl/fsl_esai.c
>> @@ -251,7 +251,7 @@ static int fsl_esai_set_dai_sysclk(struct snd_soc_dai
>> *dai, int clk_id,
>> break;
>> case ESAI_HCKT_EXTAL:
>> ecr |= ESAI_ECR_ETI;
>> -/* fall through */
>> +break;
>> case ESAI_HCKR_EXTAL:
>> ecr |= ESAI_ECR_ERI;
>> break;
>>
Re: [PATCH V4] ASoC: fsl_esai: Fix missing break in switch statement
[+cc lkml]
On 4/10/19 10:05 PM, S.j. Wang wrote:
> case ESAI_HCKT_EXTAL and case ESAI_HCKR_EXTAL should be
> independent of each other, so replace fall-through with break.
>
> Fixes: 43d24e76b698 ("ASoC: fsl_esai: Add ESAI CPU DAI driver")
>
> Signed-off-by: Shengjiu Wang
> Acked-by: Nicolin Chen
> Cc:
> ---
> Change in v4
> - Add Acked-by and cc stable
> - change the subject
>
You should preserve the changelog of what has changed in each version, not only
the last changes, so that there is a logical flow and the maintainers do not
have to dig up previous versions:
Changes in v3:
- Update subject line.
Changes in v2:
- Fix "Fixes" tag.
Also, for this type of fixes, make sure to always Cc lkml:
linux-ker...@vger.kernel.org
Thanks
--
Gustavo
> sound/soc/fsl/fsl_esai.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/sound/soc/fsl/fsl_esai.c b/sound/soc/fsl/fsl_esai.c
> index 3623aa9a6f2e..15202a637197 100644
> --- a/sound/soc/fsl/fsl_esai.c
> +++ b/sound/soc/fsl/fsl_esai.c
> @@ -251,7 +251,7 @@ static int fsl_esai_set_dai_sysclk(struct snd_soc_dai
> *dai, int clk_id,
> break;
> case ESAI_HCKT_EXTAL:
> ecr |= ESAI_ECR_ETI;
> - /* fall through */
> + break;
> case ESAI_HCKR_EXTAL:
> ecr |= ESAI_ECR_ERI;
> break;
>
[PATCH v2 5/5] nohz_full: Allow the boot CPU to be nohz_full
Allow the boot CPU / CPU0 to be nohz_full. Have the boot CPU take the
do_timer duty during boot until a housekeeping CPU can take over.
This is supported when CONFIG_PM_SLEEP_SMP is not configured, or when
it is configured and the arch allows suspend on non-zero CPUs.
nohz_full has been trialed at a large supercomputer site and found to
significantly reduce jitter. In order to deploy it in production, they
need CPU0 to be nohz_full because their job control system requires
the application CPUs to start from 0, and the housekeeping CPUs are
placed higher. An equivalent job scheduling that uses CPU0 for
housekeeping could be achieved by modifying their system, but it is
preferable if nohz_full can support their environment without
modification.
Signed-off-by: Nicholas Piggin
---
kernel/time/tick-common.c | 50 +++
kernel/time/tick-sched.c | 34 ++
2 files changed, 70 insertions(+), 14 deletions(-)
diff --git a/kernel/time/tick-common.c b/kernel/time/tick-common.c
index 529143b4c8d2..31146c13226e 100644
--- a/kernel/time/tick-common.c
+++ b/kernel/time/tick-common.c
@@ -46,6 +46,14 @@ ktime_t tick_period;
*procedure also covers cpu hotplug.
*/
int tick_do_timer_cpu __read_mostly = TICK_DO_TIMER_BOOT;
+#ifdef CONFIG_NO_HZ_FULL
+/*
+ * tick_do_timer_boot_cpu indicates the boot CPU temporarily owns
+ * tick_do_timer_cpu and it should be taken over by an eligible secondary
+ * when one comes online.
+ */
+static int tick_do_timer_boot_cpu __read_mostly = -1;
+#endif
/*
* Debugging: see timer_list.c
@@ -167,6 +175,26 @@ void tick_setup_periodic(struct clock_event_device *dev,
int broadcast)
}
}
+#ifdef CONFIG_NO_HZ_FULL
+static void giveup_do_timer(void *info)
+{
+ int cpu = *(unsigned int *)info;
+
+ WARN_ON(tick_do_timer_cpu != smp_processor_id());
+
+ tick_do_timer_cpu = cpu;
+}
+
+static void tick_take_do_timer_from_boot(void)
+{
+ int cpu = smp_processor_id();
+ int from = tick_do_timer_boot_cpu;
+
+ if (from >= 0 && from != cpu)
+ smp_call_function_single(from, giveup_do_timer, &cpu, 1);
+}
+#endif
+
/*
* Setup the tick device
*/
@@ -186,12 +214,26 @@ static void tick_setup_device(struct tick_device *td,
* this cpu:
*/
if (tick_do_timer_cpu == TICK_DO_TIMER_BOOT) {
- if (!tick_nohz_full_cpu(cpu))
- tick_do_timer_cpu = cpu;
- else
- tick_do_timer_cpu = TICK_DO_TIMER_NONE;
+ tick_do_timer_cpu = cpu;
+
tick_next_period = ktime_get();
tick_period = NSEC_PER_SEC / HZ;
+#ifdef CONFIG_NO_HZ_FULL
+ /*
+* The boot CPU may be nohz_full, in which case set
+* tick_do_timer_boot_cpu so the first housekeeping
+* secondary that comes up will take do_timer from
+* us.
+*/
+ if (tick_nohz_full_cpu(cpu))
+ tick_do_timer_boot_cpu = cpu;
+
+ } else if (tick_do_timer_boot_cpu != -1 &&
+ !tick_nohz_full_cpu(cpu)) {
+ tick_take_do_timer_from_boot();
+ tick_do_timer_boot_cpu = -1;
+ WARN_ON(tick_do_timer_cpu != cpu);
+#endif
}
/*
diff --git a/kernel/time/tick-sched.c b/kernel/time/tick-sched.c
index 6fa52cd6df0b..4aa917acbe1c 100644
--- a/kernel/time/tick-sched.c
+++ b/kernel/time/tick-sched.c
@@ -121,10 +121,16 @@ static void tick_sched_do_timer(struct tick_sched *ts,
ktime_t now)
* into a long sleep. If two CPUs happen to assign themselves to
* this duty, then the jiffies update is still serialized by
* jiffies_lock.
+*
+* If nohz_full is enabled, this should not happen because the
+* tick_do_timer_cpu never relinquishes.
*/
- if (unlikely(tick_do_timer_cpu == TICK_DO_TIMER_NONE)
- && !tick_nohz_full_cpu(cpu))
+ if (unlikely(tick_do_timer_cpu == TICK_DO_TIMER_NONE)) {
+#ifdef CONFIG_NO_HZ_FULL
+ WARN_ON(tick_nohz_full_running);
+#endif
tick_do_timer_cpu = cpu;
+ }
#endif
/* Check, if the jiffies need an update */
@@ -395,8 +401,8 @@ void __init tick_nohz_full_setup(cpumask_var_t cpumask)
static int tick_nohz_cpu_down(unsigned int cpu)
{
/*
-* The boot CPU handles housekeeping duty (unbound timers,
-* workqueues, timekeeping, ...) on behalf of full dynticks
+* The tick_do_timer_cpu CPU handles housekeeping duty (unbound
+* timers, workqueues, timekeeping, ...) on behalf of full dynticks
* CPUs. It must remain online when nohz full is enabled
[PATCH v2 4/5] kernel/sched/isolation: require a present CPU in housekeeping mask
During housekeeping mask setup, currently a possible CPU is required.
That does not guarantee the CPU would be available at boot time, so
check to ensure that at least one present CPU is in the mask.
Signed-off-by: Nicholas Piggin
---
kernel/sched/isolation.c | 18 +-
1 file changed, 13 insertions(+), 5 deletions(-)
diff --git a/kernel/sched/isolation.c b/kernel/sched/isolation.c
index b02d148e7672..687302051a27 100644
--- a/kernel/sched/isolation.c
+++ b/kernel/sched/isolation.c
@@ -65,6 +65,7 @@ void __init housekeeping_init(void)
static int __init housekeeping_setup(char *str, enum hk_flags flags)
{
cpumask_var_t non_housekeeping_mask;
+ cpumask_var_t tmp;
int err;
alloc_bootmem_cpumask_var(&non_housekeeping_mask);
@@ -75,16 +76,23 @@ static int __init housekeeping_setup(char *str, enum
hk_flags flags)
return 0;
}
+ alloc_bootmem_cpumask_var(&tmp);
if (!housekeeping_flags) {
alloc_bootmem_cpumask_var(&housekeeping_mask);
cpumask_andnot(housekeeping_mask,
cpu_possible_mask, non_housekeeping_mask);
- if (cpumask_empty(housekeeping_mask))
+
+ cpumask_andnot(tmp, cpu_present_mask, non_housekeeping_mask);
+ if (cpumask_empty(tmp)) {
+ pr_warn("Housekeeping: must include one present CPU, "
+ "using boot CPU:%d\n", smp_processor_id());
__cpumask_set_cpu(smp_processor_id(),
housekeeping_mask);
+ __cpumask_clear_cpu(smp_processor_id(),
non_housekeeping_mask);
+ }
} else {
- cpumask_var_t tmp;
-
- alloc_bootmem_cpumask_var(&tmp);
+ cpumask_andnot(tmp, cpu_present_mask, non_housekeeping_mask);
+ if (cpumask_empty(tmp))
+ __cpumask_clear_cpu(smp_processor_id(),
non_housekeeping_mask);
cpumask_andnot(tmp, cpu_possible_mask, non_housekeeping_mask);
if (!cpumask_equal(tmp, housekeeping_mask)) {
pr_warn("Housekeeping: nohz_full= must match
isolcpus=\n");
@@ -92,8 +100,8 @@ static int __init housekeeping_setup(char *str, enum
hk_flags flags)
free_bootmem_cpumask_var(non_housekeeping_mask);
return 0;
}
- free_bootmem_cpumask_var(tmp);
}
+ free_bootmem_cpumask_var(tmp);
if ((flags & HK_FLAG_TICK) && !(housekeeping_flags & HK_FLAG_TICK)) {
if (IS_ENABLED(CONFIG_NO_HZ_FULL)) {
--
2.20.1
[PATCH v2 3/5] kernel/cpu: Allow non-zero CPU to be primary for suspend / kexec freeze
This patch provides an arch option, ARCH_SUSPEND_NONZERO_CPU, to
opt-in to allowing suspend to occur on one of the housekeeping CPUs
rather than hardcoded CPU0.
This will allow CPU0 to be a nohz_full CPU with a later change.
It may be possible for platforms with hardware/firmware restrictions
on suspend/wake effectively support this by handing off the final
stage to CPU0 when kernel housekeeping is no longer required. Another
option is to make housekeeping / nohz_full mask dynamic at runtime,
but the complexity could not be justified at this time.
Signed-off-by: Nicholas Piggin
---
arch/powerpc/Kconfig | 4
include/linux/cpu.h | 7 ++-
kernel/cpu.c | 10 +-
kernel/power/Kconfig | 9 +
4 files changed, 28 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 2d0be82c3061..bc98b0e37a10 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -318,6 +318,10 @@ config ARCH_SUSPEND_POSSIBLE
(PPC_85xx && !PPC_E500MC) || PPC_86xx || PPC_PSERIES \
|| 44x || 40x
+config ARCH_SUSPEND_NONZERO_CPU
+ def_bool y
+ depends on PPC_POWERNV || PPC_PSERIES
+
config PPC_DCR_NATIVE
bool
diff --git a/include/linux/cpu.h b/include/linux/cpu.h
index 563e697e7779..dd3813959d62 100644
--- a/include/linux/cpu.h
+++ b/include/linux/cpu.h
@@ -140,7 +140,12 @@ extern void enable_nonboot_cpus(void);
static inline int suspend_disable_secondary_cpus(void)
{
- return freeze_secondary_cpus(0);
+ int cpu = 0;
+
+ if (IS_ENABLED(CONFIG_PM_SLEEP_SMP_NONZERO_CPU))
+ cpu = -1;
+
+ return freeze_secondary_cpus(cpu);
}
static inline void suspend_enable_secondary_cpus(void)
{
diff --git a/kernel/cpu.c b/kernel/cpu.c
index 6754f3ecfd94..d1bf6e2b4752 100644
--- a/kernel/cpu.c
+++ b/kernel/cpu.c
@@ -9,6 +9,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -1199,8 +1200,15 @@ int freeze_secondary_cpus(int primary)
int cpu, error = 0;
cpu_maps_update_begin();
- if (!cpu_online(primary))
+ if (primary == -1) {
primary = cpumask_first(cpu_online_mask);
+ if (!housekeeping_cpu(primary, HK_FLAG_TIMER))
+ primary = housekeeping_any_cpu(HK_FLAG_TIMER);
+ } else {
+ if (!cpu_online(primary))
+ primary = cpumask_first(cpu_online_mask);
+ }
+
/*
* We take down all of the non-boot CPUs in one shot to avoid races
* with the userspace trying to use the CPU hotplug at the same time
diff --git a/kernel/power/Kconfig b/kernel/power/Kconfig
index f8fe57d1022e..9bbaaab14b36 100644
--- a/kernel/power/Kconfig
+++ b/kernel/power/Kconfig
@@ -114,6 +114,15 @@ config PM_SLEEP_SMP
depends on PM_SLEEP
select HOTPLUG_CPU
+config PM_SLEEP_SMP_NONZERO_CPU
+ def_bool y
+ depends on PM_SLEEP_SMP
+ depends on ARCH_SUSPEND_NONZERO_CPU
+ ---help---
+ If an arch can suspend (for suspend, hibernate, kexec, etc) on a
+ non-zero numbered CPU, it may define ARCH_SUSPEND_NONZERO_CPU. This
+ will allow nohz_full mask to include CPU0.
+
config PM_AUTOSLEEP
bool "Opportunistic sleep"
depends on PM_SLEEP
--
2.20.1
[PATCH v2 2/5] PM / suspend: add function to disable secondaries for suspend
This adds a function to disable secondary CPUs for suspend that are
not necessarily non-zero / non-boot CPUs. Platforms will be able to
use this to suspend using non-zero CPUs.
Cc: Rafael J. Wysocki
Signed-off-by: Nicholas Piggin
---
include/linux/cpu.h | 10 ++
kernel/kexec_core.c | 4 ++--
kernel/power/hibernate.c | 12 ++--
kernel/power/suspend.c | 4 ++--
4 files changed, 20 insertions(+), 10 deletions(-)
diff --git a/include/linux/cpu.h b/include/linux/cpu.h
index 5041357d0297..563e697e7779 100644
--- a/include/linux/cpu.h
+++ b/include/linux/cpu.h
@@ -137,6 +137,16 @@ static inline int disable_nonboot_cpus(void)
return freeze_secondary_cpus(0);
}
extern void enable_nonboot_cpus(void);
+
+static inline int suspend_disable_secondary_cpus(void)
+{
+ return freeze_secondary_cpus(0);
+}
+static inline void suspend_enable_secondary_cpus(void)
+{
+ return enable_nonboot_cpus();
+}
+
#else /* !CONFIG_PM_SLEEP_SMP */
static inline int disable_nonboot_cpus(void) { return 0; }
static inline void enable_nonboot_cpus(void) {}
diff --git a/kernel/kexec_core.c b/kernel/kexec_core.c
index d7140447be75..fd5c95ff9251 100644
--- a/kernel/kexec_core.c
+++ b/kernel/kexec_core.c
@@ -1150,7 +1150,7 @@ int kernel_kexec(void)
error = dpm_suspend_end(PMSG_FREEZE);
if (error)
goto Resume_devices;
- error = disable_nonboot_cpus();
+ error = suspend_disable_secondary_cpus();
if (error)
goto Enable_cpus;
local_irq_disable();
@@ -1183,7 +1183,7 @@ int kernel_kexec(void)
Enable_irqs:
local_irq_enable();
Enable_cpus:
- enable_nonboot_cpus();
+ suspend_enable_secondary_cpus();
dpm_resume_start(PMSG_RESTORE);
Resume_devices:
dpm_resume_end(PMSG_RESTORE);
diff --git a/kernel/power/hibernate.c b/kernel/power/hibernate.c
index abef759de7c8..cfc7a57049e4 100644
--- a/kernel/power/hibernate.c
+++ b/kernel/power/hibernate.c
@@ -281,7 +281,7 @@ static int create_image(int platform_mode)
if (error || hibernation_test(TEST_PLATFORM))
goto Platform_finish;
- error = disable_nonboot_cpus();
+ error = suspend_disable_secondary_cpus();
if (error || hibernation_test(TEST_CPUS))
goto Enable_cpus;
@@ -323,7 +323,7 @@ static int create_image(int platform_mode)
local_irq_enable();
Enable_cpus:
- enable_nonboot_cpus();
+ suspend_enable_secondary_cpus();
Platform_finish:
platform_finish(platform_mode);
@@ -417,7 +417,7 @@ int hibernation_snapshot(int platform_mode)
int __weak hibernate_resume_nonboot_cpu_disable(void)
{
- return disable_nonboot_cpus();
+ return suspend_disable_secondary_cpus();
}
/**
@@ -486,7 +486,7 @@ static int resume_target_kernel(bool platform_mode)
local_irq_enable();
Enable_cpus:
- enable_nonboot_cpus();
+ suspend_enable_secondary_cpus();
Cleanup:
platform_restore_cleanup(platform_mode);
@@ -564,7 +564,7 @@ int hibernation_platform_enter(void)
if (error)
goto Platform_finish;
- error = disable_nonboot_cpus();
+ error = suspend_disable_secondary_cpus();
if (error)
goto Enable_cpus;
@@ -586,7 +586,7 @@ int hibernation_platform_enter(void)
local_irq_enable();
Enable_cpus:
- enable_nonboot_cpus();
+ suspend_enable_secondary_cpus();
Platform_finish:
hibernation_ops->finish();
diff --git a/kernel/power/suspend.c b/kernel/power/suspend.c
index 0bd595a0b610..59b6def23046 100644
--- a/kernel/power/suspend.c
+++ b/kernel/power/suspend.c
@@ -428,7 +428,7 @@ static int suspend_enter(suspend_state_t state, bool
*wakeup)
if (suspend_test(TEST_PLATFORM))
goto Platform_wake;
- error = disable_nonboot_cpus();
+ error = suspend_disable_secondary_cpus();
if (error || suspend_test(TEST_CPUS))
goto Enable_cpus;
@@ -458,7 +458,7 @@ static int suspend_enter(suspend_state_t state, bool
*wakeup)
BUG_ON(irqs_disabled());
Enable_cpus:
- enable_nonboot_cpus();
+ suspend_enable_secondary_cpus();
Platform_wake:
platform_resume_noirq(state);
--
2.20.1
[PATCH v2 1/5] sched/core: allow the remote scheduler tick to be started on CPU0
This has no effect yet because CPU0 will always be a housekeeping CPU
until a later change.
Signed-off-by: Nicholas Piggin
---
kernel/sched/core.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/kernel/sched/core.c b/kernel/sched/core.c
index 4778c48a7fda..10e05ec049b6 100644
--- a/kernel/sched/core.c
+++ b/kernel/sched/core.c
@@ -5918,7 +5918,7 @@ void __init sched_init_smp(void)
static int __init migration_init(void)
{
- sched_rq_cpu_starting(smp_processor_id());
+ sched_cpu_starting(smp_processor_id());
return 0;
}
early_initcall(migration_init);
--
2.20.1
[PATCH v2 0/5] Allow CPU0 to be nohz full
Since last time, I added a compile time option to opt-out of this if the platform does not support suspend on non-zero, and tried to improve legibility of changelogs and explain the justification better. I have been testing this on powerpc/pseries and it seems to work fine (the firmware call to suspend can be called on any CPU and resumes where it left off), but not included here because the code has some bitrot unrelated to this series which I hacked to fix. I will discuss it and either send an acked patch to go with this series if it is small, or fix it in powerpc tree. Thanks, Nick Nicholas Piggin (5): sched/core: allow the remote scheduler tick to be started on CPU0 PM / suspend: add function to disable secondaries for suspend kernel/cpu: Allow non-zero CPU to be primary for suspend / kexec freeze kernel/sched/isolation: require a present CPU in housekeeping mask nohz_full: Allow the boot CPU to be nohz_full include/linux/cpu.h | 15 kernel/cpu.c | 10 +++- kernel/kexec_core.c | 4 ++-- kernel/power/Kconfig | 9 +++ kernel/power/hibernate.c | 12 +- kernel/power/suspend.c| 4 ++-- kernel/sched/core.c | 2 +- kernel/sched/isolation.c | 18 ++ kernel/time/tick-common.c | 50 +++ kernel/time/tick-sched.c | 34 ++ 11 files changed, 131 insertions(+), 31 deletions(-) -- 2.20.1
Re: [PATCH v2] powerpc/watchdog: Use hrtimers for per-CPU heartbeat
On 4/9/19 10:10 AM, Nicholas Piggin wrote: > Using a jiffies timer creates a dependency on the tick_do_timer_cpu > incrementing jiffies. If that CPU has locked up and jiffies is not > incrementing, the watchdog heartbeat timer for all CPUs stops and > creates false positives and confusing warnings on local CPUs, and > also causes the SMP detector to stop, so the root cause is never > detected. > > Fix this by using hrtimer based timers for the watchdog heartbeat, > like the generic kernel hardlockup detector. > > Cc: Gautham R. Shenoy > Reported-by: Ravikumar Bangoria > Signed-off-by: Nicholas Piggin This one is giving me a proper backtrace when hardlockup happens with perf_fuzzer so, Tested-by: Ravi Bangoria Neat: Reported-by: Ravi Bangoria
Re: [PATCH v5 16/16] KVM: PPC: Book3S HV: XIVE: introduce a 'release' device operation
On Wed, Apr 10, 2019 at 07:04:48PM +0200, Cédric Le Goater wrote:
> When a P9 sPAPR VM boots, the CAS negotiation process determines which
> interrupt mode to use (XICS legacy or XIVE native) and invokes a
> machine reset to activate the chosen mode.
>
> To be able to switch from one mode to another, we introduce the
> capability to release a KVM device without destroying the VM. The KVM
> device interface is extended with a new 'release' operation which is
> called when the file descriptor of the device is closed.
I believe the release operation is not called until all of the mmaps
using the fd are unmapped - which is a good thing for us, since it
means the guest can't possibly be accessing the XIVE directly.
You might want to reword that last paragraph to mention that.
> Such operations are defined for the XICS-on-XIVE and the XIVE native
> KVM devices. They clear the vCPU interrupt presenters that could be
> attached and then destroy the device.
>
> This is not considered as a safe operation as the vCPUs are still
> running and could be referencing the KVM device through their
> presenters. To protect the system from any breakage, the kvmppc_xive
> objects representing both KVM devices are now stored in an array under
> the VM. Allocation is performed on first usage and memory is freed
> only when the VM exits.
One quick comment below:
> diff --git a/arch/powerpc/kvm/book3s_xive.c b/arch/powerpc/kvm/book3s_xive.c
> index 480a3fc6b9fd..064a9f2ae678 100644
> --- a/arch/powerpc/kvm/book3s_xive.c
> +++ b/arch/powerpc/kvm/book3s_xive.c
> @@ -1100,11 +1100,19 @@ void kvmppc_xive_disable_vcpu_interrupts(struct
> kvm_vcpu *vcpu)
> void kvmppc_xive_cleanup_vcpu(struct kvm_vcpu *vcpu)
> {
> struct kvmppc_xive_vcpu *xc = vcpu->arch.xive_vcpu;
> - struct kvmppc_xive *xive = xc->xive;
> + struct kvmppc_xive *xive;
> int i;
>
> + if (!kvmppc_xics_enabled(vcpu))
> + return;
Should that be kvmppc_xive_enabled() rather than xics?
Paul.
RE: [EXT] Re: [PATCH V2] ASoC: fsl_esai: replace fall-through with break
Hi Mark > > On Wed, Apr 10, 2019 at 02:42:45AM +, S.j. Wang wrote: > > case ESAI_HCKT_EXTAL and case ESAI_HCKR_EXTAL should be independent > of > > each other, so replace fall-through with break. > > This doesn't apply against current code, please check and resend. Thanks, have sent v4 for update subject according to Gustavo's comments. [PATCH V4] ASoC: fsl_esai: Fix missing break in switch statement Best regards Wang shengjiu
[PATCH V4] ASoC: fsl_esai: Fix missing break in switch statement
case ESAI_HCKT_EXTAL and case ESAI_HCKR_EXTAL should be
independent of each other, so replace fall-through with break.
Fixes: 43d24e76b698 ("ASoC: fsl_esai: Add ESAI CPU DAI driver")
Signed-off-by: Shengjiu Wang
Acked-by: Nicolin Chen
Cc:
---
Change in v4
- Add Acked-by and cc stable
- change the subject
sound/soc/fsl/fsl_esai.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/sound/soc/fsl/fsl_esai.c b/sound/soc/fsl/fsl_esai.c
index 3623aa9a6f2e..15202a637197 100644
--- a/sound/soc/fsl/fsl_esai.c
+++ b/sound/soc/fsl/fsl_esai.c
@@ -251,7 +251,7 @@ static int fsl_esai_set_dai_sysclk(struct snd_soc_dai *dai,
int clk_id,
break;
case ESAI_HCKT_EXTAL:
ecr |= ESAI_ECR_ETI;
- /* fall through */
+ break;
case ESAI_HCKR_EXTAL:
ecr |= ESAI_ECR_ERI;
break;
--
1.9.1
RE: [EXT] [alsa-devel] [PATCH V3] ASoC: fsl_esai: Fix missing break in switch statement
Hi
>
>
> case ESAI_HCKT_EXTAL and case ESAI_HCKR_EXTAL should be independent
> of each other, so replace fall-through with break.
>
> Fixes: 43d24e76b698 ("ASoC: fsl_esai: Add ESAI CPU DAI driver")
>
> Signed-off-by: Shengjiu Wang
> Cc:
Forget to add Acked-by: Nicolin Chen , will send v4,
sorry.
> ---
> changes in v3
> - add cc stable
> - change the subject
>
> sound/soc/fsl/fsl_esai.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/sound/soc/fsl/fsl_esai.c b/sound/soc/fsl/fsl_esai.c index
> 3623aa9a6f2e..15202a637197 100644
> --- a/sound/soc/fsl/fsl_esai.c
> +++ b/sound/soc/fsl/fsl_esai.c
> @@ -251,7 +251,7 @@ static int fsl_esai_set_dai_sysclk(struct snd_soc_dai
> *dai, int clk_id,
> break;
> case ESAI_HCKT_EXTAL:
> ecr |= ESAI_ECR_ETI;
> - /* fall through */
> + break;
> case ESAI_HCKR_EXTAL:
> ecr |= ESAI_ECR_ERI;
> break;
> --
[PATCH V3] ASoC: fsl_esai: Fix missing break in switch statement
case ESAI_HCKT_EXTAL and case ESAI_HCKR_EXTAL should be
independent of each other, so replace fall-through with break.
Fixes: 43d24e76b698 ("ASoC: fsl_esai: Add ESAI CPU DAI driver")
Signed-off-by: Shengjiu Wang
Cc:
---
changes in v3
- add cc stable
- change the subject
sound/soc/fsl/fsl_esai.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/sound/soc/fsl/fsl_esai.c b/sound/soc/fsl/fsl_esai.c
index 3623aa9a6f2e..15202a637197 100644
--- a/sound/soc/fsl/fsl_esai.c
+++ b/sound/soc/fsl/fsl_esai.c
@@ -251,7 +251,7 @@ static int fsl_esai_set_dai_sysclk(struct snd_soc_dai *dai,
int clk_id,
break;
case ESAI_HCKT_EXTAL:
ecr |= ESAI_ECR_ETI;
- /* fall through */
+ break;
case ESAI_HCKR_EXTAL:
ecr |= ESAI_ECR_ERI;
break;
--
1.9.1
RE: [EXT] Re: [PATCH V2] ASoC: fsl_esai: replace fall-through with break
Hi
>
>
> On 4/9/19 9:42 PM, S.j. Wang wrote:
> > case ESAI_HCKT_EXTAL and case ESAI_HCKR_EXTAL should be independent
> of
> > each other, so replace fall-through with break.
> >
> I think you should change the subject line to:
>
> fix missing break in switch statement
>
> ...because you are fixing a bug, and it's important to put emphasis on that in
> the subject line.
>
> Also, notice that this bug has been out there for more than 5 years now, so
> you should also tag this for stable.
>
> Thanks
> --
> Gustavo
>
Ok, will send v3.
>
> > Fixes: 43d24e76b698 ("ASoC: fsl_esai: Add ESAI CPU DAI driver")
> >
> > Signed-off-by: Shengjiu Wang
> > ---
> > Changes in v2
> > - fix the fixes tag.
> >
> > sound/soc/fsl/fsl_esai.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/sound/soc/fsl/fsl_esai.c b/sound/soc/fsl/fsl_esai.c index
> > c7410bbfd2af..bad0dfed6b68 100644
> > --- a/sound/soc/fsl/fsl_esai.c
> > +++ b/sound/soc/fsl/fsl_esai.c
> > @@ -251,7 +251,7 @@ static int fsl_esai_set_dai_sysclk(struct snd_soc_dai
> *dai, int clk_id,
> > break;
> > case ESAI_HCKT_EXTAL:
> > ecr |= ESAI_ECR_ETI;
> > - /* fall through */
> > + break;
> > case ESAI_HCKR_EXTAL:
> > ecr |= esai_priv->synchronous ? ESAI_ECR_ETI : ESAI_ECR_ERI;
> > break;
> >
MAINTAINERS: Remove non-existent VAS file
The file arch/powerpc/include/uapi/asm/vas.h was considered but never merged and should be removed from the MAINTAINERS file. While here, add missing email address. Reported-by: Joe Perches Signed-off-by: Sukadev Bhattiprolu --- MAINTAINERS | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 3671fde..e3bf3d5 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -7386,13 +7386,12 @@ S: Supported F: drivers/net/ethernet/ibm/ibmvnic.* IBM Power Virtual Accelerator Switchboard -M: Sukadev Bhattiprolu +M: Sukadev Bhattiprolu L: linuxppc-dev@lists.ozlabs.org S: Supported F: arch/powerpc/platforms/powernv/vas* F: arch/powerpc/platforms/powernv/copy-paste.h F: arch/powerpc/include/asm/vas.h -F: arch/powerpc/include/uapi/asm/vas.h IBM Power Virtual Ethernet Device Driver M: Thomas Falcon -- 1.8.3.1
Re: [RFC PATCH v2 10/14] kernel/watchdog: Add a function to obtain the watchdog_allowed_mask
On Tue, Apr 09, 2019 at 01:34:21PM +0200, Peter Zijlstra wrote: > On Wed, Feb 27, 2019 at 08:05:14AM -0800, Ricardo Neri wrote: > > diff --git a/kernel/watchdog.c b/kernel/watchdog.c > > index 8fbfda94a67b..367aa81294ef 100644 > > --- a/kernel/watchdog.c > > +++ b/kernel/watchdog.c > > @@ -44,7 +44,7 @@ int __read_mostly soft_watchdog_user_enabled = 1; > > int __read_mostly watchdog_thresh = 10; > > int __read_mostly nmi_watchdog_available; > > > > -struct cpumask watchdog_allowed_mask __read_mostly; > > +static struct cpumask watchdog_allowed_mask __read_mostly; > > > > struct cpumask watchdog_cpumask __read_mostly; > > unsigned long *watchdog_cpumask_bits = cpumask_bits(&watchdog_cpumask); > > Hurmph, more struct cpumask, ideally this would get converted to > cpumask_var_t, I don't think we need this before the allocators work, do > we? I see mm_init() is called before lockup_detector_init(); both from start_kernel(). Thus, IMHO, kzalloc should work at this point. Thanks and BR, Ricardo
Re: [PATCH v3] powerpc/pseries: Only wait for dying CPU after call to rtas_stop_self()
Hello,
Ping?
--
Thiago Jung Bauermann
IBM Linux Technology Center
Thiago Jung Bauermann writes:
> When testing DLPAR CPU add/remove on a system under stress,
> pseries_cpu_die() doesn't wait long enough for a CPU to die:
>
> [ 446.983944] cpu 148 (hwid 148) Ready to die...
> [ 446.984062] cpu 149 (hwid 149) Ready to die...
> [ 446.993518] cpu 150 (hwid 150) Ready to die...
> [ 446.993543] Querying DEAD? cpu 150 (150) shows 2
> [ 446.994098] cpu 151 (hwid 151) Ready to die...
> [ 447.133726] cpu 136 (hwid 136) Ready to die...
> [ 447.403532] cpu 137 (hwid 137) Ready to die...
> [ 447.403772] cpu 138 (hwid 138) Ready to die...
> [ 447.403839] cpu 139 (hwid 139) Ready to die...
> [ 447.403887] cpu 140 (hwid 140) Ready to die...
> [ 447.403937] cpu 141 (hwid 141) Ready to die...
> [ 447.403979] cpu 142 (hwid 142) Ready to die...
> [ 447.404038] cpu 143 (hwid 143) Ready to die...
> [ 447.513546] cpu 128 (hwid 128) Ready to die...
> [ 447.693533] cpu 129 (hwid 129) Ready to die...
> [ 447.693999] cpu 130 (hwid 130) Ready to die...
> [ 447.703530] cpu 131 (hwid 131) Ready to die...
> [ 447.704087] Querying DEAD? cpu 132 (132) shows 2
> [ 447.704102] cpu 132 (hwid 132) Ready to die...
> [ 447.713534] cpu 133 (hwid 133) Ready to die...
> [ 447.714064] Querying DEAD? cpu 134 (134) shows 2
>
> This is a race between one CPU stopping and another one calling
> pseries_cpu_die() to wait for it to stop. That function does a short busy
> loop calling RTAS query-cpu-stopped-state on the stopping CPU to verify
> that it is stopped, but I think there's a lot for the stopping CPU to do
> which may take longer than this loop allows.
>
> As can be seen in the dmesg right before or after the "Querying DEAD?"
> messages, if pseries_cpu_die() waited a little longer it would have seen
> the CPU in the stopped state.
>
> What I think is going on is that CPU 134 was inactive at the time it was
> unplugged. In that case, dlpar_offline_cpu() calls H_PROD on that CPU and
> immediately calls pseries_cpu_die(). Meanwhile, the prodded CPU activates
> and start the process of stopping itself. The busy loop is not long enough
> to allow for the CPU to wake up and complete the stopping process.
>
> This can be a problem because if the busy loop finishes too early, then the
> kernel may offline another CPU before the previous one finished dying,
> which would lead to two concurrent calls to rtas-stop-self, which is
> prohibited by the PAPR.
>
> We can make the race a lot more even if we only start querying if the CPU
> is stopped when the stopping CPU is close to call rtas_stop_self(). Since
> pseries_mach_cpu_die() sets the CPU current state to offline almost
> immediately before calling rtas_stop_self(), we use that as a signal that
> it is either already stopped or very close to that point, and we can start
> the busy loop.
>
> As suggested by Michael Ellerman, this patch also changes the busy loop to
> wait for a fixed amount of wall time. Based on the measurements that
> Gautham did on a POWER9 system, in successful cases of
> smp_query_cpu_stopped(cpu) returning affirmative, the maximum time spent
> inside the loop was was 10 ms. This patch loops for 20 ms just be sure.
>
> Signed-off-by: Thiago Jung Bauermann
> Analyzed-by: Gautham R Shenoy
> ---
> arch/powerpc/platforms/pseries/hotplug-cpu.c | 13 +++--
> 1 file changed, 11 insertions(+), 2 deletions(-)
>
> I have seen this problem since v4.8. Should this patch go to stable as
> well?
>
> Changes since v2:
> - Increaded busy loop to 200 iterations so that it can last up to 20 ms
> (suggested by Gautham).
> - Changed commit message to include Gautham's remarks.
>
> diff --git a/arch/powerpc/platforms/pseries/hotplug-cpu.c
> b/arch/powerpc/platforms/pseries/hotplug-cpu.c
> index 97feb6e79f1a..ac6dc35ab829 100644
> --- a/arch/powerpc/platforms/pseries/hotplug-cpu.c
> +++ b/arch/powerpc/platforms/pseries/hotplug-cpu.c
> @@ -214,13 +214,22 @@ static void pseries_cpu_die(unsigned int cpu)
> msleep(1);
> }
> } else if (get_preferred_offline_state(cpu) == CPU_STATE_OFFLINE) {
> + /*
> + * If the current state is not offline yet, it means that the
> + * dying CPU (which is either in pseries_mach_cpu_die() or in
> + * the process of getting there) didn't have a chance yet to
> + * call rtas_stop_self() and therefore it's too early to query
> + * if the CPU is stopped.
> + */
> + spin_event_timeout(get_cpu_current_state(cpu) ==
> CPU_STATE_OFFLINE,
> +10, 100);
>
> - for (tries = 0; tries < 25; tries++) {
> + for (tries = 0; tries < 200; tries++) {
> cpu_status = smp_query_cpu_stopped(pcpu);
> if (cpu_status == QCSS_STOPPED ||
> cpu_status == QCSS_HARDWARE_ERROR)
>
Re: [PATCH] Linux: Define struct termios2 in under _GNU_SOURCE [BZ #10339]
On 09/04/2019 07:47, Florian Weimer wrote:
> struct termios2 is required for setting arbitrary baud rates on serial
> ports. and have conflicting
> definitions in the existing termios definitions, which means that it
> is currently very difficult to use TCGETS2/TCSETS2 and struct termios2
> with glibc. Providing a definition within glibc resolves this problem.
>
> This does not completely address bug 10339, but it at least exposes
> the current kernel functionality in this area.
>
> Support for struct termios2 is architecture-specific in the kernel.
> Support on alpha was only added in Linux 4.20. POWER support is
> currently missing. The expectation is that the kernel will eventually
> use the generic UAPI definition for struct termios2.
I still think the better strategy, from both BZ#10339 and recent thread
discussion about the issue on libc-alpha, is rather to:
1. Start to use termios2 ioctl kabi instead of termios1. The only
missing spot is alpha pre linux 4.20.
2. Adjust sparc and mips to add c_ispeed and c_ospeed along with
compat symbols to use termios1. This will allow also some cleanup
to remove _HAVE_STRUCT_TERMIOS_C_{O,I}SPEED.
3. Use the compat symbols for alpha pre-4.20.
4. With termios Linux ABI being essentially the same for all supported
architectures (with support for c_ospeed and c_ispeed) we can move
forward to adapt the current cfgetospeed, cfgetispeed, cfsetospeed,
cfsetispeed to work with arbitrary values.
The POSIX and Linux extended BXX values will need to be handled
exceptionally. It means their integers values will be reserved and
mapped to the termios2 values. The code resulting code for cfsetospeed,
for instance, would be:
---
static inline speed_t
c_ispeed (tcflag_t c_cflag)
{
return (c_cflag >> IBSHIFT) & CBAUD;
}
/*
* The top four bits in speed_t are reserved for future use, and
*currently*
* the equivalent values are the only valid baud_t values.
*/
static inline bool
invalid_speed (speed_t x)
{
return x > 0x0fff;
}
/* Set the output baud rate stored in *TERMIOS_P to the symbol SPEED */
int
cfsetospeed (struct termios *termios_p, speed_t speed)
{
if (invalid_speed (speed))
{
__set_errno (EINVAL);
return -1;
}
termios_p->c_ospeed = speed_kernel_from_user (speed);
if ( c_ispeed (termios_p->c_cflag) == B0 )
termios_p->c_ispeed = termios_p->c_ospeed;
if ( (speed & ~CBAUD) != 0 || speed > _MAX_BAUD )
speed = BOTHER;
/*
* Don't set the input flags here; the B0 in c_cflag indicates that
* the input speed is tied to the output speed.
*/
termios_p->c_cflag = (termios_p->c_cflag & ~CBAUD) | speed;
return 0;
}
---
This allows us to adjust the baud rates to non-standard values using termios
interfaces without to resorting to add new headers and use a different API
(ioctl).
As Peter Anvin has indicated, he create a POC [1] with the aforementioned
new interfaces. It has not been rebased against master, more specially against
my termios refactor to simplify the multiple architecture header definitions,
but I intend to use as a base.
>
> 2019-04-09 Florian Weimer
>
> [BZ #10339]
> Linux: Define struct termios2 in under _GNU_SOURCE.
> * sysdeps/unix/sysv/linux/Makefile [$(subdir) == termios] (tests):
> Add tst-termios2.
> * sysdeps/unix/sysv/linux/tst-termios2.c: New file.
> * sysdeps/unix/sysv/linux/bits/termios2-struct.h: Likewise.
> * sysdeps/unix/sysv/linux/bits/termios.h [__USE_GNU]: Include it.
> * sysdeps/unix/sysv/linux/alpha/bits/termios2-struct.h: New file.
> * sysdeps/unix/sysv/linux/sparc/bits/termios2-struct.h: Likewise.
>
> diff --git a/NEWS b/NEWS
> index b58e2469d4..5e6ecb9c7d 100644
> --- a/NEWS
> +++ b/NEWS
> @@ -18,6 +18,9 @@ Major new features:
>
> * On Linux, the gettid function has been added.
>
> +* On Linux, now provides a definition of struct termios2 with
> + the _GNU_SOURCE feature test macro.
> +
> * Minguo (Republic of China) calendar support has been added as an
>alternative calendar for the following locales: zh_TW, cmn_TW, hak_TW,
>nan_TW, lzh_TW.
> diff --git a/sysdeps/unix/sysv/linux/Makefile
> b/sysdeps/unix/sysv/linux/Makefile
> index 52ac6ad484..4cb5e4f0d2 100644
> --- a/sysdeps/unix/sysv/linux/Makefile
> +++ b/sysdeps/unix/sysv/linux/Makefile
> @@ -156,6 +156,7 @@ endif
>
> ifeq ($(subdir),termios)
> sysdep_headers += termio.h
> +tests += tst-termios2
> endif
>
> ifeq ($(subdir),posix)
> diff --git a/sysdeps/unix/sysv/linux/alpha/bits/termios2-struct.h
> b/sysdeps/unix/sysv/linux/alpha/bits/termios2-struct.h
> new file mode 100644
> index 00..5f09445e23
> --- /dev/null
> +++ b/sysdeps/unix/sysv/linux/alpha/bits/ter
[PATCH v2 21/21] docs: hwmon: Add an index file and rename docs to *.rst
Now that all files were converted to ReST format, rename them
and add an index.
Signed-off-by: Mauro Carvalho Chehab
---
.../devicetree/bindings/hwmon/g762.txt| 2 +-
Documentation/hwmon/{ab8500 => ab8500.rst}| 2 +-
...guru-datasheet => abituguru-datasheet.rst} | 0
.../hwmon/{abituguru => abituguru.rst}| 0
.../hwmon/{abituguru3 => abituguru3.rst} | 0
Documentation/hwmon/{abx500 => abx500.rst}| 0
...{acpi_power_meter => acpi_power_meter.rst} | 2 +-
Documentation/hwmon/{ad7314 => ad7314.rst}| 0
.../hwmon/{adc128d818 => adc128d818.rst} | 0
Documentation/hwmon/{adm1021 => adm1021.rst} | 0
Documentation/hwmon/{adm1025 => adm1025.rst} | 0
Documentation/hwmon/{adm1026 => adm1026.rst} | 0
Documentation/hwmon/{adm1031 => adm1031.rst} | 0
Documentation/hwmon/{adm1275 => adm1275.rst} | 4 +-
Documentation/hwmon/{adm9240 => adm9240.rst} | 0
Documentation/hwmon/{ads1015 => ads1015.rst} | 0
Documentation/hwmon/{ads7828 => ads7828.rst} | 0
Documentation/hwmon/{adt7410 => adt7410.rst} | 0
Documentation/hwmon/{adt7411 => adt7411.rst} | 0
Documentation/hwmon/{adt7462 => adt7462.rst} | 0
Documentation/hwmon/{adt7470 => adt7470.rst} | 0
Documentation/hwmon/{adt7475 => adt7475.rst} | 0
Documentation/hwmon/{amc6821 => amc6821.rst} | 0
Documentation/hwmon/{asb100 => asb100.rst}| 0
Documentation/hwmon/{asc7621 => asc7621.rst} | 0
...{aspeed-pwm-tacho => aspeed-pwm-tacho.rst} | 0
.../hwmon/{coretemp => coretemp.rst} | 0
Documentation/hwmon/{da9052 => da9052.rst}| 0
Documentation/hwmon/{da9055 => da9055.rst}| 0
Documentation/hwmon/{dme1737 => dme1737.rst} | 0
Documentation/hwmon/{ds1621 => ds1621.rst}| 0
Documentation/hwmon/{ds620 => ds620.rst} | 0
Documentation/hwmon/{emc1403 => emc1403.rst} | 0
Documentation/hwmon/{emc2103 => emc2103.rst} | 0
.../hwmon/{emc6w201 => emc6w201.rst} | 0
Documentation/hwmon/{f71805f => f71805f.rst} | 0
.../hwmon/{f71882fg => f71882fg.rst} | 0
.../hwmon/{fam15h_power => fam15h_power.rst} | 0
.../hwmon/{ftsteutates => ftsteutates.rst}| 0
Documentation/hwmon/{g760a => g760a.rst} | 0
Documentation/hwmon/{g762 => g762.rst}| 2 +-
Documentation/hwmon/{gl518sm => gl518sm.rst} | 0
Documentation/hwmon/{hih6130 => hih6130.rst} | 0
...on-kernel-api.txt => hwmon-kernel-api.rst} | 4 +-
.../hwmon/{ibm-cffps => ibm-cffps.rst}| 0
Documentation/hwmon/{ibmaem => ibmaem.rst}| 0
.../hwmon/{ibmpowernv => ibmpowernv.rst} | 0
Documentation/hwmon/{ina209 => ina209.rst}| 0
Documentation/hwmon/{ina2xx => ina2xx.rst}| 2 +-
Documentation/hwmon/{ina3221 => ina3221.rst} | 0
Documentation/hwmon/index.rst | 179 ++
Documentation/hwmon/{ir35221 => ir35221.rst} | 0
Documentation/hwmon/{it87 => it87.rst}| 0
Documentation/hwmon/{jc42 => jc42.rst}| 0
Documentation/hwmon/{k10temp => k10temp.rst} | 0
Documentation/hwmon/{k8temp => k8temp.rst}| 0
.../hwmon/{lineage-pem => lineage-pem.rst}| 0
Documentation/hwmon/{lm25066 => lm25066.rst} | 2 +-
Documentation/hwmon/{lm63 => lm63.rst}| 0
Documentation/hwmon/{lm70 => lm70.rst}| 0
Documentation/hwmon/{lm73 => lm73.rst}| 0
Documentation/hwmon/{lm75 => lm75.rst}| 0
Documentation/hwmon/{lm77 => lm77.rst}| 0
Documentation/hwmon/{lm78 => lm78.rst}| 0
Documentation/hwmon/{lm80 => lm80.rst}| 0
Documentation/hwmon/{lm83 => lm83.rst}| 0
Documentation/hwmon/{lm85 => lm85.rst}| 0
Documentation/hwmon/{lm87 => lm87.rst}| 0
Documentation/hwmon/{lm90 => lm90.rst}| 0
Documentation/hwmon/{lm92 => lm92.rst}| 0
Documentation/hwmon/{lm93 => lm93.rst}| 0
Documentation/hwmon/{lm95234 => lm95234.rst} | 0
Documentation/hwmon/{lm95245 => lm95245.rst} | 0
Documentation/hwmon/{ltc2945 => ltc2945.rst} | 0
Documentation/hwmon/{ltc2978 => ltc2978.rst} | 0
Documentation/hwmon/{ltc2990 => ltc2990.rst} | 0
Documentation/hwmon/{ltc3815 => ltc3815.rst} | 0
Documentation/hwmon/{ltc4151 => ltc4151.rst} | 0
Documentation/hwmon/{ltc4215 => ltc4215.rst} | 0
Documentation/hwmon/{ltc4245 => ltc4245.rst} | 0
Documentation/hwmon/{ltc4260 => ltc4260.rst} | 0
Documentation/hwmon/{ltc4261 => ltc4261.rst} | 0
.../hwmon/{max16064 => max16064.rst} | 2 +-
.../hwmon/{max16065 => max16065.rst} | 0
Documentation/hwmon/{max1619 => max1619.rst} | 0
Documentation/hwmon/{max1668 => max1668.rst} | 0
Documentation/hwmon/{max197 => max197.rst}| 0
.../hwmon/{max20751 => max20751.rst} | 2 +-
.../hwmon/{max31722 => max31722.rst} | 0
.../hwmon/{max31785 => max31785.rst} | 0
.../hwmon/{max31790 => max31790.rst} | 0
...
[PATCH v2 00/21] Convert hwmon documentation to ReST
This series converts the contents of Documentation/hwmon to ReST
format.
PS.: I opted to group the conversion files per groups of maintainer
set, as, if I were to generate one patch per file, it would give around
160 patches.
I also added those patches to my development tree at:
https://git.linuxtv.org/mchehab/experimental.git/log/?h=hwmon
If you want to see the results, they're at:
https://www.infradead.org/~mchehab/hwmon/
Version 2:
- Fixed broken SOB lines;
- changed submitting-patches.rst to mention that drivers should be
documented as Documentation/hwmon/.rst,
as suggested by Jonathan Neusch�fer.
Mauro Carvalho Chehab (21):
docs: hwmon: k10temp: convert to ReST format
docs: hwmon: vexpress: convert to ReST format
docs: hwmon: menf21bmc: convert to ReST format
docs: hwmon: sch5627: convert to ReST format
docs: hwmon: emc2103: convert to ReST format
docs: hwmon: pc87360: convert to ReST format
docs: hwmon: fam15h_power: convert to ReST format
docs: hwmon: w83791d: convert to ReST format
docs: hwmon: coretemp: convert to ReST format
docs: hwmon: aspeed-pwm-tacho: convert to ReST format
docs: hwmon: ibmpowernv: convert to ReST format
docs: hwmon: asc7621: convert to ReST format
docs: hwmon: ads1015: convert to ReST format
docs: hwmon: dme1737, vt1211: convert to ReST format
docs: hwmon: wm831x, wm8350: convert to ReST format
docs: hwmon: da9052, da9055: convert to ReST format
docs: hwmon: k8temp, w83793: convert to ReST format
docs: hwmon: pmbus files: convert to ReST format
docs: hwmon: misc files: convert to ReST format
docs: hwmon: convert remaining files to ReST format
docs: hwmon: Add an index file and rename docs to *.rst
.../devicetree/bindings/hwmon/g762.txt| 2 +-
Documentation/hwmon/{ab8500 => ab8500.rst}| 10 +-
Documentation/hwmon/abituguru | 92 ---
...guru-datasheet => abituguru-datasheet.rst} | 160 ++--
Documentation/hwmon/abituguru.rst | 113 +++
.../hwmon/{abituguru3 => abituguru3.rst} | 36 +-
Documentation/hwmon/{abx500 => abx500.rst}| 8 +-
...{acpi_power_meter => acpi_power_meter.rst} | 25 +-
Documentation/hwmon/{ad7314 => ad7314.rst}| 9 +
.../hwmon/{adc128d818 => adc128d818.rst} | 7 +-
Documentation/hwmon/{adm1021 => adm1021.rst} | 44 +-
Documentation/hwmon/{adm1025 => adm1025.rst} | 13 +-
Documentation/hwmon/{adm1026 => adm1026.rst} | 24 +-
Documentation/hwmon/{adm1031 => adm1031.rst} | 16 +-
Documentation/hwmon/{adm1275 => adm1275.rst} | 30 +-
Documentation/hwmon/{adm9240 => adm9240.rst} | 50 +-
Documentation/hwmon/{ads1015 => ads1015.rst} | 72 +-
Documentation/hwmon/{ads7828 => ads7828.rst} | 29 +-
Documentation/hwmon/{adt7410 => adt7410.rst} | 49 +-
Documentation/hwmon/{adt7411 => adt7411.rst} | 20 +-
Documentation/hwmon/{adt7462 => adt7462.rst} | 10 +-
Documentation/hwmon/{adt7470 => adt7470.rst} | 8 +-
Documentation/hwmon/{adt7475 => adt7475.rst} | 38 +-
Documentation/hwmon/{amc6821 => amc6821.rst} | 19 +-
Documentation/hwmon/{asb100 => asb100.rst}| 50 +-
Documentation/hwmon/{asc7621 => asc7621.rst} | 146 ++--
...{aspeed-pwm-tacho => aspeed-pwm-tacho.rst} | 2 +
.../hwmon/{coretemp => coretemp.rst} | 46 +-
Documentation/hwmon/{da9052 => da9052.rst}| 40 +-
Documentation/hwmon/{da9055 => da9055.rst}| 20 +-
Documentation/hwmon/{dme1737 => dme1737.rst} | 88 ++-
Documentation/hwmon/{ds1621 => ds1621.rst}| 154 ++--
Documentation/hwmon/{ds620 => ds620.rst} | 12 +-
Documentation/hwmon/{emc1403 => emc1403.rst} | 33 +-
Documentation/hwmon/{emc2103 => emc2103.rst} | 6 +-
.../hwmon/{emc6w201 => emc6w201.rst} | 5 +
Documentation/hwmon/{f71805f => f71805f.rst} | 36 +-
.../hwmon/{f71882fg => f71882fg.rst} | 56 +-
.../hwmon/{fam15h_power => fam15h_power.rst} | 85 ++-
.../hwmon/{ftsteutates => ftsteutates.rst}| 14 +-
Documentation/hwmon/{g760a => g760a.rst} | 4 +
Documentation/hwmon/{g762 => g762.rst}| 67 +-
Documentation/hwmon/{gl518sm => gl518sm.rst} | 21 +-
Documentation/hwmon/{hih6130 => hih6130.rst} | 14 +-
...on-kernel-api.txt => hwmon-kernel-api.rst} | 298
.../hwmon/{ibm-cffps => ibm-cffps.rst}| 3 +
Documentation/hwmon/{ibmaem => ibmaem.rst}| 10 +-
.../hwmon/{ibmpowernv => ibmpowernv.rst} | 3 +
Documentation/hwmon/{ina209 => ina209.rst}| 18 +-
Documentation/hwmon/{ina2xx => ina2xx.rst}| 41 +-
Documentation/hwmon/{ina3221 => ina3221.rst} | 17 +-
Documentation/hwmon/index.rst | 179 +
Documentation/hwmon/{ir35221 => ir35221.rst} | 12 +-
Documentation/hwmon/{it87 => it87.rst}| 102 ++-
Documentation/hwmon/{jc42 => jc42.rst}| 55 +-
Documentation/hwmon/{k10temp => k10temp.rst} | 37 +-
Documentation/hwmon/{k8temp => k8temp.rst}| 17 +-
.../hwmon/{lineage-pem => lineage-pem.rst}| 16 +-
Documentat
[PATCH v2 11/21] docs: hwmon: ibmpowernv: convert to ReST format
Convert ibmpowernv to ReST format, in order to allow it to be parsed by Sphinx. Signed-off-by: Mauro Carvalho Chehab --- Documentation/hwmon/ibmpowernv | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/hwmon/ibmpowernv b/Documentation/hwmon/ibmpowernv index 56468258711f..3f1feae3901c 100644 --- a/Documentation/hwmon/ibmpowernv +++ b/Documentation/hwmon/ibmpowernv @@ -2,6 +2,7 @@ Kernel Driver IBMPOWERNV Supported systems: + * Any recent IBM P servers based on POWERNV platform Author: Neelesh Gupta @@ -29,6 +30,7 @@ CONFIG_SENSORS_IBMPOWERNV. It can also be built as module 'ibmpowernv'. Sysfs attributes +=== === fanX_input Measured RPM value. fanX_min Threshold RPM for alert generation. fanX_fault 0: No fail condition @@ -78,3 +80,4 @@ currX_enable Enable/disable all current sensors belonging to the 0: Disable energyX_input Cumulative energy (microJoule) +=== === -- 2.20.1
Re: [EXT] Re: [PATCH] ASoC: fsl_asrc: replace the process_option table with function
On Wed, Apr 10, 2019 at 10:34:05AM +, S.j. Wang wrote: > > On Wed, Apr 10, 2019 at 08:26:59AM +, S.j. Wang wrote: > > > > Is it possible to update the table? It'd be way quicker to use > > > > lookup table than real-time calculation all the time. I believe you > > > > can simply calculate all the values out for 12KHz and 24KHz since > > > > you have the function. If there are certain combinations of these > > > > two not being supported, then we could mark it with a special value and > > add an if-check to error out. > > > > > > > > > > Yes, but I think the function should be more flexible, if someday we > > > need to support Other sample rate, only need to update the list. > > > > Given the fact that the owner of the function cannot give more comments, I > > feel the function wouldn't be very maintainable as none of us understands it > > well. On the other hand, you'll need to update the supported I/O rate lists > > anyway, so why not just update the table as well? The supported sample > > rates from ALSA are limited too. Overall, I think that continue using a > > lookup > > table wins. > > Alsa support SNDRV_PCM_RATE_KNOT, we can define the rate that we want > To support, and use function is more flexible, and we have use the function > Internally for long time, it is stable😊 OK. I will try to indulge it. Let's see your next version first.
Re: [EXT] Re: [PATCH v2 1/3] ASoC: fsl_audmix: remove "model" attribute
On Wed, Apr 10, 2019 at 10:34:57AM +, Viorel Suman wrote: > Hi Nicolin, > > On Ma, 2019-04-09 at 21:29 -0700, Nicolin Chen wrote: > > WARNING: This email was created outside of NXP. DO NOT CLICK links or > > attachments unless you recognize the sender and know the content is > > safe. > > > > > > > > On Tue, Apr 09, 2019 at 11:27:39AM +, Viorel Suman wrote: > > > > > > Use "of_device_id.data" to specify the machine driver > > > instead of "model" DTS attribute. > > > > > > Signed-off-by: Viorel Suman > > Acked-by: Nicolin Chen > > > > > > > > --- > > > sound/soc/fsl/fsl_audmix.c | 43 +++--- > > > - > > > 1 file changed, 23 insertions(+), 20 deletions(-) > > > > > > + priv->pdev = platform_device_register_data(&pdev->dev, mdrv, > > > 0, NULL, > > > +0); > > Would you please send a separate patch to replace "pdev->dev"? > > Thank you for review. Yes, will send V3. Ah...when I said that, I was literally saying that you should send a separate patch individually, not resend the series. Now I see you sent v3/v4 almost at the same time as "Applied" mails from Mark. And I am totally confused which version got applied Please rebase your local tree and find out which version got applied and then send the diff with a separate patch. Thanks Nicolin
[PATCH v5 00/16] KVM: PPC: Book3S HV: add XIVE native exploitation mode
Hello, On the POWER9 processor, the XIVE interrupt controller can control interrupt sources using MMIOs to trigger events, to EOI or to turn off the sources. Priority management and interrupt acknowledgment is also controlled by MMIO in the CPU presenter sub-engine. PowerNV/baremetal Linux runs natively under XIVE but sPAPR guests need special support from the hypervisor to do the same. This is called the XIVE native exploitation mode and today, it can be activated under the PowerPC Hypervisor, pHyp. However, Linux/KVM lacks XIVE native support and still offers the old interrupt mode interface using a KVM device implementing the XICS hcalls over XIVE. The following series is proposal to add the same support under KVM. A new KVM device is introduced for the XIVE native exploitation mode. It reuses most of the XICS-over-XIVE glue implementation structures which are internal to KVM but has a completely different interface. A set of KVM device ioctls provide support for the hypervisor calls, all handled in QEMU, to configure the sources and the event queues. From there, all interrupt control is transferred to the guest which can use MMIOs. These MMIO regions (ESB and TIMA) are exposed to guests in QEMU, similarly to VFIO, and the associated VMAs are populated dynamically with the appropriate pages using a fault handler. These are now implemented using mmap()s of the KVM device fd. Migration has its own specific needs regarding memory. The patchset provides a specific control to quiesce XIVE before capturing the memory. The save and restore of the internal state is based on the same ioctls used for the hcalls. On a POWER9 sPAPR machine, the Client Architecture Support (CAS) negotiation process determines whether the guest operates with a interrupt controller using the XICS legacy model, as found on POWER8, or in XIVE exploitation mode. Which means that the KVM interrupt device should be created at run-time, after the machine has started. This requires extra support from KVM to destroy KVM devices. It is introduced at the end of the patchset and requires some attention. This is based on Linux 5.1-rc4 and is a candidate for 5.2. The OPAL patches have been merged now. GitHub trees available here : QEMU sPAPR: https://github.com/legoater/qemu/commits/xive-next Linux/KVM: https://github.com/legoater/linux/commits/xive-5.1 Thanks, C. Caveats : - We should introduce a set of definitions common to XIVE and XICS - The XICS-over-XIVE device file book3s_xive.c could be renamed to book3s_xics_on_xive.c or book3s_xics_p9.c - The XICS-over-XIVE device still has locking issues in the setup. - xc->valid is not useful - xc->xive is not very useful either Changes since v4: - add check on EQ page alignment - add requirement on KVM_XIVE_EQ_ALWAYS_NOTIFY - add documentation in Documentation/virtual/kvm/api.txt - remove 'destroy' method - introduce a 'release' device operation called when device fd is closed. - introduce a 'xive_devices' array under the VM to store kvmppc_xive objects until VM is destroyed. Changes since v3: - removed a couple of useless includes - fix the test ont the initial setting of the EQ toggle bit : 0 -> 1 - renamed qsize to qshift - renamed qpage to qaddr - checked host page size - limited flags to KVM_XIVE_EQ_ALWAYS_NOTIFY to fit sPAPR specs - Fixed xive_timaval description in documentation Changes since v2: - removed extra OPAL call definitions - removed ->q_order setting. Only useful in the XICS-on-XIVE KVM device which allocates the EQs on behalf of the guest. - returned -ENXIO when VP base is invalid - made use of the xive_vp() macro to compute VP identifiers - reworked locking in kvmppc_xive_native_connect_vcpu() to fix races - stop advertising KVM_CAP_PPC_IRQ_XIVE as support is not fully available yet - fixed comment on XIVE IRQ number space - removed usage of the __x_* macros - fixed locking on source block - fixed comments on the KVM device attribute definitions - handled MASKED EAS configuration - fixed check on supported EQ size to restrict to 64K pages - checked kvm_eq.flags that need to be zero - removed the OPAL call when EQ qtoggle bit and index are zero. - reduced the size of kvmppc_one_reg timaval attribute to two u64s - stopped returning of the OS CAM line value Changes since v1: - Better documentation (was missing) - Nested support. XIVE not advertised on non PowerNV platforms. This is a good way to test the fallback on QEMU emulated devices. - ESB and TIMA special mapping done using the KVM device fd - All hcalls moved to QEMU. Dropped the patch moving the hcall flags. - Reworked of the KVM device ioctl controls to support hcalls and migration needs to capture/save states - Merged the control syncing XIVE and marking the EQ page dirty - Fixed passthrough support using the KVM device file address_space to clear the ESB pages from the mapping - Misc enhancements and fixes Cédric Le Goat
Re: [PATCH 0/4] Enabling secure boot on PowerNV systems
(Cc:ing Peter Jones) On Tue, Apr 9, 2019 at 3:55 PM Claudio Carvalho wrote: > > > On 4/5/19 7:19 PM, Matthew Garrett wrote: > > Based on our experience doing this in UEFI, that's insufficient - you > > want to be able to block individual binaries or leaf certificates > > without dropping trust in an intermediate certificate entirely. > > > We agree that a dbx would be useful for blacklisting particular kernels > signed with given certificate. However, we have been avoiding doing so for > the initial release of secure boot on OpenPOWER. We don't have individual > firmware binaries in OpenPOWER. Kernels are currently the only concern for > the OS secure boot certificates we're discussing here. Also, we have a very > limited keystore space in POWER9. > > Petitboot doesn't have standardized OS kernel verification at all right > now. Having the capability even without dbx seems valuable. I don't see the benefit in attempting to maintain compatibility with existing tooling unless you're going to be *completely* compatible with existing tooling. That means supporting dbx and dbt. > >> The API is still a work in progress. We are planning to publish a document > >> describing the current API and overall design shortly. > > Ok. How are the attributes interpreted by the API? > > > We support a subset of standard EFI variable attributes, and we only use > EFI variables that relate to secure boot. Our goal is not to implement > UEFI. However, we do seek to be compatible with user space tooling and > reuse as much existing infrastructure as possible. We don’t support the > following: EFI_VARIABLE_HARDWARE_ERROR_RECORD, > EFI_VARIABLE_AUTHENTICATED_WRITE_ACCESS and > EFI_VARIABLE_ENHANCED_AUTHENTICATED_ACCESS. Ok. I think that's realistically fine. > > > > >> Perhaps the biggest departure is that the secure variables are stored in > >> flash memory that is not lockable. In order to protect the secure > >> variables, hashes of the flash regions where they're stored are written to > >> TPM NVRAM indices. The TPM NVRAM indices we use are write locked at > >> runtime. The sysadmin enqueues update commands in flash. During the next > >> boot, the firmware verifies and processes the commands to update the > >> certificate store and accompanying integrity hashes in the TPM NVRAM > >> indices and write locks them. Before certificates read from flash are > >> used, the certificate store is hashed and compared against the hashes > >> stored from the TPM. The one exception is the PK. We store it in a TPM > >> NVRAM index by itself rather than flash because updates to it must be > >> guaranteed to be atomic. > > What's the behaviour if multiple updates are enqueued? Does reading > > back show a mocked up updated variable or the original state? > > > Our secure variable updates are only applied at boot time. If any one of > them fails, they all fail. So I do the following: 1) Boot 2) Extend the contents of db 3) Extend the contents of db again 4) Read back the contents of db through efivarfs 5) Reboot 6) Read back the contents of db through efivarfs Is what I see in (4) and (6) the same? Does it contain the values form both extensions? > > I'm not really clear on the workflow here. Who's the administrator > > authority? When would they be updating the second level of keys? If > > there's no support for revocation, why would distributions need two > > levels of key in the system database rather than just distributing a > > single intermediate and signing their actual signing certs with that? > > > In OpenPOWER systems, we enable our customers and business partners to > establish and manage the platform key certificate, which is the root of our > key hierarchy. From there, through the KEK, they can delegate authority to > intermediate level organizations, e.g. distros or IT departments or > business operations. Those intermediate level organizations then manage the > code signing certificates in the DB. If this answer doesn’t address your > question, can you please rephrase? Why would the intermediate level organisations not just have entries in db? The main reason we don't do it this way in UEFI is because we need to support dbx, and if you're not supporting dbx I'm not sure I see the benefit.
[PATCH v5 12/16] KVM: PPC: Book3S HV: XIVE: add a TIMA mapping
Each thread has an associated Thread Interrupt Management context
composed of a set of registers. These registers let the thread handle
priority management and interrupt acknowledgment. The most important
are :
- Interrupt Pending Buffer (IPB)
- Current Processor Priority (CPPR)
- Notification Source Register (NSR)
They are exposed to software in four different pages each proposing a
view with a different privilege. The first page is for the physical
thread context and the second for the hypervisor. Only the third
(operating system) and the fourth (user level) are exposed the guest.
A custom VM fault handler will populate the VMA with the appropriate
pages, which should only be the OS page for now.
Signed-off-by: Cédric Le Goater
Reviewed-by: David Gibson
---
arch/powerpc/include/asm/xive.h| 1 +
arch/powerpc/include/uapi/asm/kvm.h| 2 ++
arch/powerpc/kvm/book3s_xive_native.c | 39 ++
arch/powerpc/sysdev/xive/native.c | 11 ++
Documentation/virtual/kvm/devices/xive.txt | 23 +
5 files changed, 76 insertions(+)
diff --git a/arch/powerpc/include/asm/xive.h b/arch/powerpc/include/asm/xive.h
index c4e88abd3b67..eaf76f57023a 100644
--- a/arch/powerpc/include/asm/xive.h
+++ b/arch/powerpc/include/asm/xive.h
@@ -23,6 +23,7 @@
* same offset regardless of where the code is executing
*/
extern void __iomem *xive_tima;
+extern unsigned long xive_tima_os;
/*
* Offset in the TM area of our current execution level (provided by
diff --git a/arch/powerpc/include/uapi/asm/kvm.h
b/arch/powerpc/include/uapi/asm/kvm.h
index cd3f16b70a2e..0998e8edc91a 100644
--- a/arch/powerpc/include/uapi/asm/kvm.h
+++ b/arch/powerpc/include/uapi/asm/kvm.h
@@ -720,4 +720,6 @@ struct kvm_ppc_xive_eq {
#define KVM_XIVE_EQ_ALWAYS_NOTIFY 0x0001
+#define KVM_XIVE_TIMA_PAGE_OFFSET 0
+
#endif /* __LINUX_KVM_POWERPC_H */
diff --git a/arch/powerpc/kvm/book3s_xive_native.c
b/arch/powerpc/kvm/book3s_xive_native.c
index 2f9d5e9439a6..f5314da0cb45 100644
--- a/arch/powerpc/kvm/book3s_xive_native.c
+++ b/arch/powerpc/kvm/book3s_xive_native.c
@@ -165,6 +165,44 @@ int kvmppc_xive_native_connect_vcpu(struct kvm_device *dev,
return rc;
}
+static vm_fault_t xive_native_tima_fault(struct vm_fault *vmf)
+{
+ struct vm_area_struct *vma = vmf->vma;
+
+ switch (vmf->pgoff - vma->vm_pgoff) {
+ case 0: /* HW - forbid access */
+ case 1: /* HV - forbid access */
+ return VM_FAULT_SIGBUS;
+ case 2: /* OS */
+ vmf_insert_pfn(vma, vmf->address, xive_tima_os >> PAGE_SHIFT);
+ return VM_FAULT_NOPAGE;
+ case 3: /* USER - TODO */
+ default:
+ return VM_FAULT_SIGBUS;
+ }
+}
+
+static const struct vm_operations_struct xive_native_tima_vmops = {
+ .fault = xive_native_tima_fault,
+};
+
+static int kvmppc_xive_native_mmap(struct kvm_device *dev,
+ struct vm_area_struct *vma)
+{
+ /* We only allow mappings at fixed offset for now */
+ if (vma->vm_pgoff == KVM_XIVE_TIMA_PAGE_OFFSET) {
+ if (vma_pages(vma) > 4)
+ return -EINVAL;
+ vma->vm_ops = &xive_native_tima_vmops;
+ } else {
+ return -EINVAL;
+ }
+
+ vma->vm_flags |= VM_IO | VM_PFNMAP;
+ vma->vm_page_prot = pgprot_noncached_wc(vma->vm_page_prot);
+ return 0;
+}
+
static int kvmppc_xive_native_set_source(struct kvmppc_xive *xive, long irq,
u64 addr)
{
@@ -1050,6 +1088,7 @@ struct kvm_device_ops kvm_xive_native_ops = {
.set_attr = kvmppc_xive_native_set_attr,
.get_attr = kvmppc_xive_native_get_attr,
.has_attr = kvmppc_xive_native_has_attr,
+ .mmap = kvmppc_xive_native_mmap,
};
void kvmppc_xive_native_init_module(void)
diff --git a/arch/powerpc/sysdev/xive/native.c
b/arch/powerpc/sysdev/xive/native.c
index 0c037e933e55..7782201e5fe8 100644
--- a/arch/powerpc/sysdev/xive/native.c
+++ b/arch/powerpc/sysdev/xive/native.c
@@ -521,6 +521,9 @@ u32 xive_native_default_eq_shift(void)
}
EXPORT_SYMBOL_GPL(xive_native_default_eq_shift);
+unsigned long xive_tima_os;
+EXPORT_SYMBOL_GPL(xive_tima_os);
+
bool __init xive_native_init(void)
{
struct device_node *np;
@@ -573,6 +576,14 @@ bool __init xive_native_init(void)
for_each_possible_cpu(cpu)
kvmppc_set_xive_tima(cpu, r.start, tima);
+ /* Resource 2 is OS window */
+ if (of_address_to_resource(np, 2, &r)) {
+ pr_err("Failed to get thread mgmnt area resource\n");
+ return false;
+ }
+
+ xive_tima_os = r.start;
+
/* Grab size of provisionning pages */
xive_parse_provisioning(np);
diff --git a/Documentation/virtual/kvm/devices/xive.txt
b/Documentation/virtual/kvm/devices/xive.txt
index 525d1eebcf34..0cd7847ec38a 100644
--- a/Do
[PATCH v5 08/16] KVM: PPC: Book3S HV: XIVE: add a control to sync the sources
This control will be used by the H_INT_SYNC hcall from QEMU to flush
event notifications on the XIVE IC owning the source.
Signed-off-by: Cédric Le Goater
Reviewed-by: David Gibson
---
arch/powerpc/include/uapi/asm/kvm.h| 1 +
arch/powerpc/kvm/book3s_xive_native.c | 36 ++
Documentation/virtual/kvm/devices/xive.txt | 8 +
3 files changed, 45 insertions(+)
diff --git a/arch/powerpc/include/uapi/asm/kvm.h
b/arch/powerpc/include/uapi/asm/kvm.h
index f045f9dee42e..e4abe30f6fc6 100644
--- a/arch/powerpc/include/uapi/asm/kvm.h
+++ b/arch/powerpc/include/uapi/asm/kvm.h
@@ -683,6 +683,7 @@ struct kvm_ppc_cpu_char {
#define KVM_DEV_XIVE_GRP_SOURCE2 /* 64-bit source
identifier */
#define KVM_DEV_XIVE_GRP_SOURCE_CONFIG 3 /* 64-bit source identifier */
#define KVM_DEV_XIVE_GRP_EQ_CONFIG 4 /* 64-bit EQ identifier */
+#define KVM_DEV_XIVE_GRP_SOURCE_SYNC 5 /* 64-bit source identifier */
/* Layout of 64-bit XIVE source attribute values */
#define KVM_XIVE_LEVEL_SENSITIVE (1ULL << 0)
diff --git a/arch/powerpc/kvm/book3s_xive_native.c
b/arch/powerpc/kvm/book3s_xive_native.c
index b9597d80c95a..65380416d101 100644
--- a/arch/powerpc/kvm/book3s_xive_native.c
+++ b/arch/powerpc/kvm/book3s_xive_native.c
@@ -335,6 +335,38 @@ static int kvmppc_xive_native_set_source_config(struct
kvmppc_xive *xive,
priority, masked, eisn);
}
+static int kvmppc_xive_native_sync_source(struct kvmppc_xive *xive,
+ long irq, u64 addr)
+{
+ struct kvmppc_xive_src_block *sb;
+ struct kvmppc_xive_irq_state *state;
+ struct xive_irq_data *xd;
+ u32 hw_num;
+ u16 src;
+ int rc = 0;
+
+ pr_devel("%s irq=0x%lx", __func__, irq);
+
+ sb = kvmppc_xive_find_source(xive, irq, &src);
+ if (!sb)
+ return -ENOENT;
+
+ state = &sb->irq_state[src];
+
+ rc = -EINVAL;
+
+ arch_spin_lock(&sb->lock);
+
+ if (state->valid) {
+ kvmppc_xive_select_irq(state, &hw_num, &xd);
+ xive_native_sync_source(hw_num);
+ rc = 0;
+ }
+
+ arch_spin_unlock(&sb->lock);
+ return rc;
+}
+
static int xive_native_validate_queue_size(u32 qshift)
{
/*
@@ -670,6 +702,9 @@ static int kvmppc_xive_native_set_attr(struct kvm_device
*dev,
case KVM_DEV_XIVE_GRP_EQ_CONFIG:
return kvmppc_xive_native_set_queue_config(xive, attr->attr,
attr->addr);
+ case KVM_DEV_XIVE_GRP_SOURCE_SYNC:
+ return kvmppc_xive_native_sync_source(xive, attr->attr,
+ attr->addr);
}
return -ENXIO;
}
@@ -699,6 +734,7 @@ static int kvmppc_xive_native_has_attr(struct kvm_device
*dev,
break;
case KVM_DEV_XIVE_GRP_SOURCE:
case KVM_DEV_XIVE_GRP_SOURCE_CONFIG:
+ case KVM_DEV_XIVE_GRP_SOURCE_SYNC:
if (attr->attr >= KVMPPC_XIVE_FIRST_IRQ &&
attr->attr < KVMPPC_XIVE_NR_IRQS)
return 0;
diff --git a/Documentation/virtual/kvm/devices/xive.txt
b/Documentation/virtual/kvm/devices/xive.txt
index 429cbc4cf960..1e7f19d7594b 100644
--- a/Documentation/virtual/kvm/devices/xive.txt
+++ b/Documentation/virtual/kvm/devices/xive.txt
@@ -92,3 +92,11 @@ the legacy interrupt mode, referred as XICS (POWER7/8).
-EINVAL: Invalid queue address
-EFAULT: Invalid user pointer for attr->addr.
-EIO:Configuration of the underlying HW failed
+
+ 5. KVM_DEV_XIVE_GRP_SOURCE_SYNC (write only)
+ Synchronize the source to flush event notifications
+ Attributes:
+Interrupt source number (64-bit)
+ Errors:
+-ENOENT: Unknown source number
+-EINVAL: Not initialized source number
--
2.20.1
[PATCH v5 07/16] KVM: PPC: Book3S HV: XIVE: add a global reset control
This control is to be used by the H_INT_RESET hcall from QEMU. Its
purpose is to clear all configuration of the sources and EQs. This is
necessary in case of a kexec (for a kdump kernel for instance) to make
sure that no remaining configuration is left from the previous boot
setup so that the new kernel can start safely from a clean state.
The queue 7 is ignored when the XIVE device is configured to run in
single escalation mode. Prio 7 is used by escalations.
The XIVE VP is kept enabled as the vCPU is still active and connected
to the XIVE device.
Signed-off-by: Cédric Le Goater
Reviewed-by: David Gibson
---
arch/powerpc/include/uapi/asm/kvm.h| 1 +
arch/powerpc/kvm/book3s_xive_native.c | 85 ++
Documentation/virtual/kvm/devices/xive.txt | 5 ++
3 files changed, 91 insertions(+)
diff --git a/arch/powerpc/include/uapi/asm/kvm.h
b/arch/powerpc/include/uapi/asm/kvm.h
index 85005400fd86..f045f9dee42e 100644
--- a/arch/powerpc/include/uapi/asm/kvm.h
+++ b/arch/powerpc/include/uapi/asm/kvm.h
@@ -679,6 +679,7 @@ struct kvm_ppc_cpu_char {
/* POWER9 XIVE Native Interrupt Controller */
#define KVM_DEV_XIVE_GRP_CTRL 1
+#define KVM_DEV_XIVE_RESET 1
#define KVM_DEV_XIVE_GRP_SOURCE2 /* 64-bit source
identifier */
#define KVM_DEV_XIVE_GRP_SOURCE_CONFIG 3 /* 64-bit source identifier */
#define KVM_DEV_XIVE_GRP_EQ_CONFIG 4 /* 64-bit EQ identifier */
diff --git a/arch/powerpc/kvm/book3s_xive_native.c
b/arch/powerpc/kvm/book3s_xive_native.c
index 3e7cdcacc932..b9597d80c95a 100644
--- a/arch/powerpc/kvm/book3s_xive_native.c
+++ b/arch/powerpc/kvm/book3s_xive_native.c
@@ -572,6 +572,83 @@ static int kvmppc_xive_native_get_queue_config(struct
kvmppc_xive *xive,
return 0;
}
+static void kvmppc_xive_reset_sources(struct kvmppc_xive_src_block *sb)
+{
+ int i;
+
+ for (i = 0; i < KVMPPC_XICS_IRQ_PER_ICS; i++) {
+ struct kvmppc_xive_irq_state *state = &sb->irq_state[i];
+
+ if (!state->valid)
+ continue;
+
+ if (state->act_priority == MASKED)
+ continue;
+
+ state->eisn = 0;
+ state->act_server = 0;
+ state->act_priority = MASKED;
+ xive_vm_esb_load(&state->ipi_data, XIVE_ESB_SET_PQ_01);
+ xive_native_configure_irq(state->ipi_number, 0, MASKED, 0);
+ if (state->pt_number) {
+ xive_vm_esb_load(state->pt_data, XIVE_ESB_SET_PQ_01);
+ xive_native_configure_irq(state->pt_number,
+ 0, MASKED, 0);
+ }
+ }
+}
+
+static int kvmppc_xive_reset(struct kvmppc_xive *xive)
+{
+ struct kvm *kvm = xive->kvm;
+ struct kvm_vcpu *vcpu;
+ unsigned int i;
+
+ pr_devel("%s\n", __func__);
+
+ mutex_lock(&kvm->lock);
+
+ kvm_for_each_vcpu(i, vcpu, kvm) {
+ struct kvmppc_xive_vcpu *xc = vcpu->arch.xive_vcpu;
+ unsigned int prio;
+
+ if (!xc)
+ continue;
+
+ kvmppc_xive_disable_vcpu_interrupts(vcpu);
+
+ for (prio = 0; prio < KVMPPC_XIVE_Q_COUNT; prio++) {
+
+ /* Single escalation, no queue 7 */
+ if (prio == 7 && xive->single_escalation)
+ break;
+
+ if (xc->esc_virq[prio]) {
+ free_irq(xc->esc_virq[prio], vcpu);
+ irq_dispose_mapping(xc->esc_virq[prio]);
+ kfree(xc->esc_virq_names[prio]);
+ xc->esc_virq[prio] = 0;
+ }
+
+ kvmppc_xive_native_cleanup_queue(vcpu, prio);
+ }
+ }
+
+ for (i = 0; i <= xive->max_sbid; i++) {
+ struct kvmppc_xive_src_block *sb = xive->src_blocks[i];
+
+ if (sb) {
+ arch_spin_lock(&sb->lock);
+ kvmppc_xive_reset_sources(sb);
+ arch_spin_unlock(&sb->lock);
+ }
+ }
+
+ mutex_unlock(&kvm->lock);
+
+ return 0;
+}
+
static int kvmppc_xive_native_set_attr(struct kvm_device *dev,
struct kvm_device_attr *attr)
{
@@ -579,6 +656,10 @@ static int kvmppc_xive_native_set_attr(struct kvm_device
*dev,
switch (attr->group) {
case KVM_DEV_XIVE_GRP_CTRL:
+ switch (attr->attr) {
+ case KVM_DEV_XIVE_RESET:
+ return kvmppc_xive_reset(xive);
+ }
break;
case KVM_DEV_XIVE_GRP_SOURCE:
return kvmppc_xive_native_set_source(xive, attr->attr,
@@ -611,6 +692,10 @@ static int kvmppc_xive_native_has_attr(struct kvm_device
*dev,
{
switch (attr->group) {
[PATCH v5 15/16] KVM: PPC: Book3S HV: XIVE: activate XIVE exploitation mode
Full support for the XIVE native exploitation mode is now available, advertise the capability KVM_CAP_PPC_IRQ_XIVE for guests running on PowerNV KVM Hypervisors only. Support for nested guests (pseries KVM Hypervisor) is not yet available. XIVE should also have been activated which is default setting on POWER9 systems running a recent Linux kernel. Signed-off-by: Cédric Le Goater Reviewed-by: David Gibson --- arch/powerpc/kvm/powerpc.c | 7 --- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/arch/powerpc/kvm/powerpc.c b/arch/powerpc/kvm/powerpc.c index b0858ee61460..f54926c78320 100644 --- a/arch/powerpc/kvm/powerpc.c +++ b/arch/powerpc/kvm/powerpc.c @@ -573,10 +573,11 @@ int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext) #ifdef CONFIG_KVM_XIVE case KVM_CAP_PPC_IRQ_XIVE: /* -* Return false until all the XIVE infrastructure is -* in place including support for migration. +* We need XIVE to be enabled on the platform (implies +* a POWER9 processor) and the PowerNV platform, as +* nested is not yet supported. */ - r = 0; + r = xive_enabled() && !!cpu_has_feature(CPU_FTR_HVMODE); break; #endif -- 2.20.1
[PATCH v5 09/16] KVM: PPC: Book3S HV: XIVE: add a control to dirty the XIVE EQ pages
When migration of a VM is initiated, a first copy of the RAM is
transferred to the destination before the VM is stopped, but there is
no guarantee that the EQ pages in which the event notifications are
queued have not been modified.
To make sure migration will capture a consistent memory state, the
XIVE device should perform a XIVE quiesce sequence to stop the flow of
event notifications and stabilize the EQs. This is the purpose of the
KVM_DEV_XIVE_EQ_SYNC control which will also marks the EQ pages dirty
to force their transfer.
Signed-off-by: Cédric Le Goater
Reviewed-by: David Gibson
---
arch/powerpc/include/uapi/asm/kvm.h| 1 +
arch/powerpc/kvm/book3s_xive_native.c | 85 ++
Documentation/virtual/kvm/devices/xive.txt | 29
3 files changed, 115 insertions(+)
diff --git a/arch/powerpc/include/uapi/asm/kvm.h
b/arch/powerpc/include/uapi/asm/kvm.h
index e4abe30f6fc6..12744608a61c 100644
--- a/arch/powerpc/include/uapi/asm/kvm.h
+++ b/arch/powerpc/include/uapi/asm/kvm.h
@@ -680,6 +680,7 @@ struct kvm_ppc_cpu_char {
/* POWER9 XIVE Native Interrupt Controller */
#define KVM_DEV_XIVE_GRP_CTRL 1
#define KVM_DEV_XIVE_RESET 1
+#define KVM_DEV_XIVE_EQ_SYNC 2
#define KVM_DEV_XIVE_GRP_SOURCE2 /* 64-bit source
identifier */
#define KVM_DEV_XIVE_GRP_SOURCE_CONFIG 3 /* 64-bit source identifier */
#define KVM_DEV_XIVE_GRP_EQ_CONFIG 4 /* 64-bit EQ identifier */
diff --git a/arch/powerpc/kvm/book3s_xive_native.c
b/arch/powerpc/kvm/book3s_xive_native.c
index 65380416d101..16d23ef3bd39 100644
--- a/arch/powerpc/kvm/book3s_xive_native.c
+++ b/arch/powerpc/kvm/book3s_xive_native.c
@@ -681,6 +681,88 @@ static int kvmppc_xive_reset(struct kvmppc_xive *xive)
return 0;
}
+static void kvmppc_xive_native_sync_sources(struct kvmppc_xive_src_block *sb)
+{
+ int j;
+
+ for (j = 0; j < KVMPPC_XICS_IRQ_PER_ICS; j++) {
+ struct kvmppc_xive_irq_state *state = &sb->irq_state[j];
+ struct xive_irq_data *xd;
+ u32 hw_num;
+
+ if (!state->valid)
+ continue;
+
+ /*
+* The struct kvmppc_xive_irq_state reflects the state
+* of the EAS configuration and not the state of the
+* source. The source is masked setting the PQ bits to
+* '-Q', which is what is being done before calling
+* the KVM_DEV_XIVE_EQ_SYNC control.
+*
+* If a source EAS is configured, OPAL syncs the XIVE
+* IC of the source and the XIVE IC of the previous
+* target if any.
+*
+* So it should be fine ignoring MASKED sources as
+* they have been synced already.
+*/
+ if (state->act_priority == MASKED)
+ continue;
+
+ kvmppc_xive_select_irq(state, &hw_num, &xd);
+ xive_native_sync_source(hw_num);
+ xive_native_sync_queue(hw_num);
+ }
+}
+
+static int kvmppc_xive_native_vcpu_eq_sync(struct kvm_vcpu *vcpu)
+{
+ struct kvmppc_xive_vcpu *xc = vcpu->arch.xive_vcpu;
+ unsigned int prio;
+
+ if (!xc)
+ return -ENOENT;
+
+ for (prio = 0; prio < KVMPPC_XIVE_Q_COUNT; prio++) {
+ struct xive_q *q = &xc->queues[prio];
+
+ if (!q->qpage)
+ continue;
+
+ /* Mark EQ page dirty for migration */
+ mark_page_dirty(vcpu->kvm, gpa_to_gfn(q->guest_qaddr));
+ }
+ return 0;
+}
+
+static int kvmppc_xive_native_eq_sync(struct kvmppc_xive *xive)
+{
+ struct kvm *kvm = xive->kvm;
+ struct kvm_vcpu *vcpu;
+ unsigned int i;
+
+ pr_devel("%s\n", __func__);
+
+ mutex_lock(&kvm->lock);
+ for (i = 0; i <= xive->max_sbid; i++) {
+ struct kvmppc_xive_src_block *sb = xive->src_blocks[i];
+
+ if (sb) {
+ arch_spin_lock(&sb->lock);
+ kvmppc_xive_native_sync_sources(sb);
+ arch_spin_unlock(&sb->lock);
+ }
+ }
+
+ kvm_for_each_vcpu(i, vcpu, kvm) {
+ kvmppc_xive_native_vcpu_eq_sync(vcpu);
+ }
+ mutex_unlock(&kvm->lock);
+
+ return 0;
+}
+
static int kvmppc_xive_native_set_attr(struct kvm_device *dev,
struct kvm_device_attr *attr)
{
@@ -691,6 +773,8 @@ static int kvmppc_xive_native_set_attr(struct kvm_device
*dev,
switch (attr->attr) {
case KVM_DEV_XIVE_RESET:
return kvmppc_xive_reset(xive);
+ case KVM_DEV_XIVE_EQ_SYNC:
+ return kvmppc_xive_native_eq_sync(xive);
}
break;
case KVM_DEV_XIVE_GRP_SOURCE:
@@ -729,6 +813,7 @@ s
[PATCH v5 02/16] KVM: PPC: Book3S HV: add a new KVM device for the XIVE native exploitation mode
This is the basic framework for the new KVM device supporting the XIVE
native exploitation mode. The user interface exposes a new KVM device
to be created by QEMU, only available when running on a L0 hypervisor.
Support for nested guests is not available yet.
The XIVE device reuses the device structure of the XICS-on-XIVE device
as they have a lot in common. That could possibly change in the future
if the need arise.
Signed-off-by: Cédric Le Goater
Reviewed-by: David Gibson
---
arch/powerpc/include/asm/kvm_host.h| 1 +
arch/powerpc/include/asm/kvm_ppc.h | 8 +
arch/powerpc/include/uapi/asm/kvm.h| 3 +
include/uapi/linux/kvm.h | 2 +
arch/powerpc/kvm/book3s.c | 7 +-
arch/powerpc/kvm/book3s_xive_native.c | 179 +
Documentation/virtual/kvm/devices/xive.txt | 19 +++
arch/powerpc/kvm/Makefile | 2 +-
8 files changed, 219 insertions(+), 2 deletions(-)
create mode 100644 arch/powerpc/kvm/book3s_xive_native.c
create mode 100644 Documentation/virtual/kvm/devices/xive.txt
diff --git a/arch/powerpc/include/asm/kvm_host.h
b/arch/powerpc/include/asm/kvm_host.h
index e6b5bb012ccb..008523224e7a 100644
--- a/arch/powerpc/include/asm/kvm_host.h
+++ b/arch/powerpc/include/asm/kvm_host.h
@@ -222,6 +222,7 @@ extern struct kvm_device_ops kvm_xics_ops;
struct kvmppc_xive;
struct kvmppc_xive_vcpu;
extern struct kvm_device_ops kvm_xive_ops;
+extern struct kvm_device_ops kvm_xive_native_ops;
struct kvmppc_passthru_irqmap;
diff --git a/arch/powerpc/include/asm/kvm_ppc.h
b/arch/powerpc/include/asm/kvm_ppc.h
index ac22b28ae78d..f3383e76017a 100644
--- a/arch/powerpc/include/asm/kvm_ppc.h
+++ b/arch/powerpc/include/asm/kvm_ppc.h
@@ -594,6 +594,10 @@ extern int kvmppc_xive_set_icp(struct kvm_vcpu *vcpu, u64
icpval);
extern int kvmppc_xive_set_irq(struct kvm *kvm, int irq_source_id, u32 irq,
int level, bool line_status);
extern void kvmppc_xive_push_vcpu(struct kvm_vcpu *vcpu);
+
+extern void kvmppc_xive_native_init_module(void);
+extern void kvmppc_xive_native_exit_module(void);
+
#else
static inline int kvmppc_xive_set_xive(struct kvm *kvm, u32 irq, u32 server,
u32 priority) { return -1; }
@@ -617,6 +621,10 @@ static inline int kvmppc_xive_set_icp(struct kvm_vcpu
*vcpu, u64 icpval) { retur
static inline int kvmppc_xive_set_irq(struct kvm *kvm, int irq_source_id, u32
irq,
int level, bool line_status) { return
-ENODEV; }
static inline void kvmppc_xive_push_vcpu(struct kvm_vcpu *vcpu) { }
+
+static inline void kvmppc_xive_native_init_module(void) { }
+static inline void kvmppc_xive_native_exit_module(void) { }
+
#endif /* CONFIG_KVM_XIVE */
#if defined(CONFIG_PPC_POWERNV) && defined(CONFIG_KVM_BOOK3S_64_HANDLER)
diff --git a/arch/powerpc/include/uapi/asm/kvm.h
b/arch/powerpc/include/uapi/asm/kvm.h
index 26ca425f4c2c..be0ce1f17625 100644
--- a/arch/powerpc/include/uapi/asm/kvm.h
+++ b/arch/powerpc/include/uapi/asm/kvm.h
@@ -677,4 +677,7 @@ struct kvm_ppc_cpu_char {
#define KVM_XICS_PRESENTED(1ULL << 43)
#define KVM_XICS_QUEUED (1ULL << 44)
+/* POWER9 XIVE Native Interrupt Controller */
+#define KVM_DEV_XIVE_GRP_CTRL 1
+
#endif /* __LINUX_KVM_POWERPC_H */
diff --git a/include/uapi/linux/kvm.h b/include/uapi/linux/kvm.h
index 6d4ea4b6c922..e6368163d3a0 100644
--- a/include/uapi/linux/kvm.h
+++ b/include/uapi/linux/kvm.h
@@ -1211,6 +1211,8 @@ enum kvm_device_type {
#define KVM_DEV_TYPE_ARM_VGIC_V3 KVM_DEV_TYPE_ARM_VGIC_V3
KVM_DEV_TYPE_ARM_VGIC_ITS,
#define KVM_DEV_TYPE_ARM_VGIC_ITS KVM_DEV_TYPE_ARM_VGIC_ITS
+ KVM_DEV_TYPE_XIVE,
+#define KVM_DEV_TYPE_XIVE KVM_DEV_TYPE_XIVE
KVM_DEV_TYPE_MAX,
};
diff --git a/arch/powerpc/kvm/book3s.c b/arch/powerpc/kvm/book3s.c
index 10c5579d20ce..7c3348fa27e1 100644
--- a/arch/powerpc/kvm/book3s.c
+++ b/arch/powerpc/kvm/book3s.c
@@ -1050,6 +1050,9 @@ static int kvmppc_book3s_init(void)
if (xics_on_xive()) {
kvmppc_xive_init_module();
kvm_register_device_ops(&kvm_xive_ops, KVM_DEV_TYPE_XICS);
+ kvmppc_xive_native_init_module();
+ kvm_register_device_ops(&kvm_xive_native_ops,
+ KVM_DEV_TYPE_XIVE);
} else
#endif
kvm_register_device_ops(&kvm_xics_ops, KVM_DEV_TYPE_XICS);
@@ -1060,8 +1063,10 @@ static int kvmppc_book3s_init(void)
static void kvmppc_book3s_exit(void)
{
#ifdef CONFIG_KVM_XICS
- if (xics_on_xive())
+ if (xics_on_xive()) {
kvmppc_xive_exit_module();
+ kvmppc_xive_native_exit_module();
+ }
#endif
#ifdef CONFIG_KVM_BOOK3S_32_HANDLER
kvmppc_book3s_exit_pr();
diff --git a/arch/powerpc/kvm/book3s_xive_native.c
b/arch/powerpc/kvm/book3s_xive_native.c
new file mode 100644
inde
[PATCH v5 16/16] KVM: PPC: Book3S HV: XIVE: introduce a 'release' device operation
When a P9 sPAPR VM boots, the CAS negotiation process determines which
interrupt mode to use (XICS legacy or XIVE native) and invokes a
machine reset to activate the chosen mode.
To be able to switch from one mode to another, we introduce the
capability to release a KVM device without destroying the VM. The KVM
device interface is extended with a new 'release' operation which is
called when the file descriptor of the device is closed.
Such operations are defined for the XICS-on-XIVE and the XIVE native
KVM devices. They clear the vCPU interrupt presenters that could be
attached and then destroy the device.
This is not considered as a safe operation as the vCPUs are still
running and could be referencing the KVM device through their
presenters. To protect the system from any breakage, the kvmppc_xive
objects representing both KVM devices are now stored in an array under
the VM. Allocation is performed on first usage and memory is freed
only when the VM exits.
Cc: Paolo Bonzini
Signed-off-by: Cédric Le Goater
---
arch/powerpc/include/asm/kvm_host.h | 1 +
arch/powerpc/kvm/book3s_xive.h| 1 +
include/linux/kvm_host.h | 1 +
arch/powerpc/kvm/book3s_xive.c| 99 ++-
arch/powerpc/kvm/book3s_xive_native.c | 45 +++-
virt/kvm/kvm_main.c | 13
6 files changed, 156 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/include/asm/kvm_host.h
b/arch/powerpc/include/asm/kvm_host.h
index 9cc6abdce1b9..ed059c95e56a 100644
--- a/arch/powerpc/include/asm/kvm_host.h
+++ b/arch/powerpc/include/asm/kvm_host.h
@@ -314,6 +314,7 @@ struct kvm_arch {
#ifdef CONFIG_KVM_XICS
struct kvmppc_xics *xics;
struct kvmppc_xive *xive;
+ struct kvmppc_xive *xive_devices[2];
struct kvmppc_passthru_irqmap *pimap;
#endif
struct kvmppc_ops *kvm_ops;
diff --git a/arch/powerpc/kvm/book3s_xive.h b/arch/powerpc/kvm/book3s_xive.h
index e011622dc038..426146332984 100644
--- a/arch/powerpc/kvm/book3s_xive.h
+++ b/arch/powerpc/kvm/book3s_xive.h
@@ -283,6 +283,7 @@ void kvmppc_xive_free_sources(struct kvmppc_xive_src_block
*sb);
int kvmppc_xive_select_target(struct kvm *kvm, u32 *server, u8 prio);
int kvmppc_xive_attach_escalation(struct kvm_vcpu *vcpu, u8 prio,
bool single_escalation);
+struct kvmppc_xive *kvmppc_xive_get_device(struct kvm *kvm, u32 type);
#endif /* CONFIG_KVM_XICS */
#endif /* _KVM_PPC_BOOK3S_XICS_H */
diff --git a/include/linux/kvm_host.h b/include/linux/kvm_host.h
index 831d963451d8..3b444620d8fc 100644
--- a/include/linux/kvm_host.h
+++ b/include/linux/kvm_host.h
@@ -1246,6 +1246,7 @@ struct kvm_device_ops {
long (*ioctl)(struct kvm_device *dev, unsigned int ioctl,
unsigned long arg);
int (*mmap)(struct kvm_device *dev, struct vm_area_struct *vma);
+ void (*release)(struct kvm_device *dev);
};
void kvm_device_get(struct kvm_device *dev);
diff --git a/arch/powerpc/kvm/book3s_xive.c b/arch/powerpc/kvm/book3s_xive.c
index 480a3fc6b9fd..064a9f2ae678 100644
--- a/arch/powerpc/kvm/book3s_xive.c
+++ b/arch/powerpc/kvm/book3s_xive.c
@@ -1100,11 +1100,19 @@ void kvmppc_xive_disable_vcpu_interrupts(struct
kvm_vcpu *vcpu)
void kvmppc_xive_cleanup_vcpu(struct kvm_vcpu *vcpu)
{
struct kvmppc_xive_vcpu *xc = vcpu->arch.xive_vcpu;
- struct kvmppc_xive *xive = xc->xive;
+ struct kvmppc_xive *xive;
int i;
+ if (!kvmppc_xics_enabled(vcpu))
+ return;
+
+ if (!xc)
+ return;
+
pr_devel("cleanup_vcpu(cpu=%d)\n", xc->server_num);
+ xive = xc->xive;
+
/* Ensure no interrupt is still routed to that VP */
xc->valid = false;
kvmppc_xive_disable_vcpu_interrupts(vcpu);
@@ -1141,6 +1149,10 @@ void kvmppc_xive_cleanup_vcpu(struct kvm_vcpu *vcpu)
}
/* Free the VP */
kfree(xc);
+
+ /* Cleanup the vcpu */
+ vcpu->arch.irq_type = KVMPPC_IRQ_DEFAULT;
+ vcpu->arch.xive_vcpu = NULL;
}
int kvmppc_xive_connect_vcpu(struct kvm_device *dev,
@@ -1158,7 +1170,7 @@ int kvmppc_xive_connect_vcpu(struct kvm_device *dev,
}
if (xive->kvm != vcpu->kvm)
return -EPERM;
- if (vcpu->arch.irq_type)
+ if (vcpu->arch.irq_type != KVMPPC_IRQ_DEFAULT)
return -EBUSY;
if (kvmppc_xive_find_server(vcpu->kvm, cpu)) {
pr_devel("Duplicate !\n");
@@ -1824,6 +1836,9 @@ void kvmppc_xive_free_sources(struct
kvmppc_xive_src_block *sb)
}
}
+/*
+ * Called when VM is destroyed
+ */
static void kvmppc_xive_free(struct kvm_device *dev)
{
struct kvmppc_xive *xive = dev->private;
@@ -1851,6 +1866,83 @@ static void kvmppc_xive_free(struct kvm_device *dev)
kfree(dev);
}
+/*
+ * Called when device fd is closed
+ */
+static void kvmppc_xive_release(struct kvm_device *dev)
+{
+ struct kvmppc_xive *xive = dev->privat
[PATCH v5 14/16] KVM: PPC: Book3S HV: XIVE: add passthrough support
The KVM XICS-over-XIVE device and the proposed KVM XIVE native device
implement an IRQ space for the guest using the generic IPI interrupts
of the XIVE IC controller. These interrupts are allocated at the OPAL
level and "mapped" into the guest IRQ number space in the range 0-0x1FFF.
Interrupt management is performed in the XIVE way: using loads and
stores on the addresses of the XIVE IPI interrupt ESB pages.
Both KVM devices share the same internal structure caching information
on the interrupts, among which the xive_irq_data struct containing the
addresses of the IPI ESB pages and an extra one in case of pass-through.
The later contains the addresses of the ESB pages of the underlying HW
controller interrupts, PHB4 in all cases for now.
A guest, when running in the XICS legacy interrupt mode, lets the KVM
XICS-over-XIVE device "handle" interrupt management, that is to
perform the loads and stores on the addresses of the ESB pages of the
guest interrupts. However, when running in XIVE native exploitation
mode, the KVM XIVE native device exposes the interrupt ESB pages to
the guest and lets the guest perform directly the loads and stores.
The VMA exposing the ESB pages make use of a custom VM fault handler
which role is to populate the VMA with appropriate pages. When a fault
occurs, the guest IRQ number is deduced from the offset, and the ESB
pages of associated XIVE IPI interrupt are inserted in the VMA (using
the internal structure caching information on the interrupts).
Supporting device passthrough in the guest running in XIVE native
exploitation mode adds some extra refinements because the ESB pages
of a different HW controller (PHB4) need to be exposed to the guest
along with the initial IPI ESB pages of the XIVE IC controller. But
the overall mechanic is the same.
When the device HW irqs are mapped into or unmapped from the guest
IRQ number space, the passthru_irq helpers, kvmppc_xive_set_mapped()
and kvmppc_xive_clr_mapped(), are called to record or clear the
passthrough interrupt information and to perform the switch.
The approach taken by this patch is to clear the ESB pages of the
guest IRQ number being mapped and let the VM fault handler repopulate.
The handler will insert the ESB page corresponding to the HW interrupt
of the device being passed-through or the initial IPI ESB page if the
device is being removed.
Signed-off-by: Cédric Le Goater
Reviewed-by: David Gibson
---
arch/powerpc/kvm/book3s_xive.h | 9 +
arch/powerpc/kvm/book3s_xive.c | 15
arch/powerpc/kvm/book3s_xive_native.c | 41 ++
Documentation/virtual/kvm/devices/xive.txt | 19 ++
4 files changed, 84 insertions(+)
diff --git a/arch/powerpc/kvm/book3s_xive.h b/arch/powerpc/kvm/book3s_xive.h
index 622f594d93e1..e011622dc038 100644
--- a/arch/powerpc/kvm/book3s_xive.h
+++ b/arch/powerpc/kvm/book3s_xive.h
@@ -94,6 +94,11 @@ struct kvmppc_xive_src_block {
struct kvmppc_xive_irq_state irq_state[KVMPPC_XICS_IRQ_PER_ICS];
};
+struct kvmppc_xive;
+
+struct kvmppc_xive_ops {
+ int (*reset_mapped)(struct kvm *kvm, unsigned long guest_irq);
+};
struct kvmppc_xive {
struct kvm *kvm;
@@ -132,6 +137,10 @@ struct kvmppc_xive {
/* Flags */
u8 single_escalation;
+
+ struct kvmppc_xive_ops *ops;
+ struct address_space *mapping;
+ struct mutex mapping_lock;
};
#define KVMPPC_XIVE_Q_COUNT8
diff --git a/arch/powerpc/kvm/book3s_xive.c b/arch/powerpc/kvm/book3s_xive.c
index c1b7aa7dbc28..480a3fc6b9fd 100644
--- a/arch/powerpc/kvm/book3s_xive.c
+++ b/arch/powerpc/kvm/book3s_xive.c
@@ -937,6 +937,13 @@ int kvmppc_xive_set_mapped(struct kvm *kvm, unsigned long
guest_irq,
/* Turn the IPI hard off */
xive_vm_esb_load(&state->ipi_data, XIVE_ESB_SET_PQ_01);
+ /*
+* Reset ESB guest mapping. Needed when ESB pages are exposed
+* to the guest in XIVE native mode
+*/
+ if (xive->ops && xive->ops->reset_mapped)
+ xive->ops->reset_mapped(kvm, guest_irq);
+
/* Grab info about irq */
state->pt_number = hw_irq;
state->pt_data = irq_data_get_irq_handler_data(host_data);
@@ -1022,6 +1029,14 @@ int kvmppc_xive_clr_mapped(struct kvm *kvm, unsigned
long guest_irq,
state->pt_number = 0;
state->pt_data = NULL;
+ /*
+* Reset ESB guest mapping. Needed when ESB pages are exposed
+* to the guest in XIVE native mode
+*/
+ if (xive->ops && xive->ops->reset_mapped) {
+ xive->ops->reset_mapped(kvm, guest_irq);
+ }
+
/* Reconfigure the IPI */
xive_native_configure_irq(state->ipi_number,
kvmppc_xive_vp(xive, state->act_server),
diff --git a/arch/powerpc/kvm/book3s_xive_native.c
b/arch/powerpc/kvm/book3s_xive_native.c
index 465eb90ff23e..62648f833adf 100644
--- a/arch/powerpc/kvm/book3s_xive_native.c
+++ b/arch/power
[PATCH v5 13/16] KVM: PPC: Book3S HV: XIVE: add a mapping for the source ESB pages
Each source is associated with an Event State Buffer (ESB) with a
even/odd pair of pages which provides commands to manage the source:
to trigger, to EOI, to turn off the source for instance.
The custom VM fault handler will deduce the guest IRQ number from the
offset of the fault, and the ESB page of the associated XIVE interrupt
will be inserted into the VMA using the internal structure caching
information on the interrupts.
Signed-off-by: Cédric Le Goater
Reviewed-by: David Gibson
---
arch/powerpc/include/uapi/asm/kvm.h| 1 +
arch/powerpc/kvm/book3s_xive_native.c | 57 ++
Documentation/virtual/kvm/devices/xive.txt | 7 +++
3 files changed, 65 insertions(+)
diff --git a/arch/powerpc/include/uapi/asm/kvm.h
b/arch/powerpc/include/uapi/asm/kvm.h
index 0998e8edc91a..b0f72dea8b11 100644
--- a/arch/powerpc/include/uapi/asm/kvm.h
+++ b/arch/powerpc/include/uapi/asm/kvm.h
@@ -721,5 +721,6 @@ struct kvm_ppc_xive_eq {
#define KVM_XIVE_EQ_ALWAYS_NOTIFY 0x0001
#define KVM_XIVE_TIMA_PAGE_OFFSET 0
+#define KVM_XIVE_ESB_PAGE_OFFSET 4
#endif /* __LINUX_KVM_POWERPC_H */
diff --git a/arch/powerpc/kvm/book3s_xive_native.c
b/arch/powerpc/kvm/book3s_xive_native.c
index f5314da0cb45..465eb90ff23e 100644
--- a/arch/powerpc/kvm/book3s_xive_native.c
+++ b/arch/powerpc/kvm/book3s_xive_native.c
@@ -165,6 +165,59 @@ int kvmppc_xive_native_connect_vcpu(struct kvm_device *dev,
return rc;
}
+static vm_fault_t xive_native_esb_fault(struct vm_fault *vmf)
+{
+ struct vm_area_struct *vma = vmf->vma;
+ struct kvm_device *dev = vma->vm_file->private_data;
+ struct kvmppc_xive *xive = dev->private;
+ struct kvmppc_xive_src_block *sb;
+ struct kvmppc_xive_irq_state *state;
+ struct xive_irq_data *xd;
+ u32 hw_num;
+ u16 src;
+ u64 page;
+ unsigned long irq;
+ u64 page_offset;
+
+ /*
+* Linux/KVM uses a two pages ESB setting, one for trigger and
+* one for EOI
+*/
+ page_offset = vmf->pgoff - vma->vm_pgoff;
+ irq = page_offset / 2;
+
+ sb = kvmppc_xive_find_source(xive, irq, &src);
+ if (!sb) {
+ pr_devel("%s: source %lx not found !\n", __func__, irq);
+ return VM_FAULT_SIGBUS;
+ }
+
+ state = &sb->irq_state[src];
+ kvmppc_xive_select_irq(state, &hw_num, &xd);
+
+ arch_spin_lock(&sb->lock);
+
+ /*
+* first/even page is for trigger
+* second/odd page is for EOI and management.
+*/
+ page = page_offset % 2 ? xd->eoi_page : xd->trig_page;
+ arch_spin_unlock(&sb->lock);
+
+ if (WARN_ON(!page)) {
+ pr_err("%s: acessing invalid ESB page for source %lx !\n",
+ __func__, irq);
+ return VM_FAULT_SIGBUS;
+ }
+
+ vmf_insert_pfn(vma, vmf->address, page >> PAGE_SHIFT);
+ return VM_FAULT_NOPAGE;
+}
+
+static const struct vm_operations_struct xive_native_esb_vmops = {
+ .fault = xive_native_esb_fault,
+};
+
static vm_fault_t xive_native_tima_fault(struct vm_fault *vmf)
{
struct vm_area_struct *vma = vmf->vma;
@@ -194,6 +247,10 @@ static int kvmppc_xive_native_mmap(struct kvm_device *dev,
if (vma_pages(vma) > 4)
return -EINVAL;
vma->vm_ops = &xive_native_tima_vmops;
+ } else if (vma->vm_pgoff == KVM_XIVE_ESB_PAGE_OFFSET) {
+ if (vma_pages(vma) > KVMPPC_XIVE_NR_IRQS * 2)
+ return -EINVAL;
+ vma->vm_ops = &xive_native_esb_vmops;
} else {
return -EINVAL;
}
diff --git a/Documentation/virtual/kvm/devices/xive.txt
b/Documentation/virtual/kvm/devices/xive.txt
index 0cd7847ec38a..69ee62d3d4dc 100644
--- a/Documentation/virtual/kvm/devices/xive.txt
+++ b/Documentation/virtual/kvm/devices/xive.txt
@@ -36,6 +36,13 @@ the legacy interrupt mode, referred as XICS (POWER7/8).
third (operating system) and the fourth (user level) are exposed the
guest.
+ 2. Event State Buffer (ESB)
+
+ Each source is associated with an Event State Buffer (ESB) with
+ either a pair of even/odd pair of pages which provides commands to
+ manage the source: to trigger, to EOI, to turn off the source for
+ instance.
+
* Groups:
1. KVM_DEV_XIVE_GRP_CTRL
--
2.20.1
[PATCH v5 11/16] KVM: introduce a 'mmap' method for KVM devices
Some KVM devices will want to handle special mappings related to the
underlying HW. For instance, the XIVE interrupt controller of the
POWER9 processor has MMIO pages for thread interrupt management and
for interrupt source control that need to be exposed to the guest when
the OS has the required support.
Cc: Paolo Bonzini
Signed-off-by: Cédric Le Goater
Reviewed-by: David Gibson
---
include/linux/kvm_host.h | 1 +
virt/kvm/kvm_main.c | 11 +++
2 files changed, 12 insertions(+)
diff --git a/include/linux/kvm_host.h b/include/linux/kvm_host.h
index 9d55c63db09b..831d963451d8 100644
--- a/include/linux/kvm_host.h
+++ b/include/linux/kvm_host.h
@@ -1245,6 +1245,7 @@ struct kvm_device_ops {
int (*has_attr)(struct kvm_device *dev, struct kvm_device_attr *attr);
long (*ioctl)(struct kvm_device *dev, unsigned int ioctl,
unsigned long arg);
+ int (*mmap)(struct kvm_device *dev, struct vm_area_struct *vma);
};
void kvm_device_get(struct kvm_device *dev);
diff --git a/virt/kvm/kvm_main.c b/virt/kvm/kvm_main.c
index 55fe8e20d8fd..ea2018ae1cd7 100644
--- a/virt/kvm/kvm_main.c
+++ b/virt/kvm/kvm_main.c
@@ -2884,6 +2884,16 @@ static long kvm_vcpu_compat_ioctl(struct file *filp,
}
#endif
+static int kvm_device_mmap(struct file *filp, struct vm_area_struct *vma)
+{
+ struct kvm_device *dev = filp->private_data;
+
+ if (dev->ops->mmap)
+ return dev->ops->mmap(dev, vma);
+
+ return -ENODEV;
+}
+
static int kvm_device_ioctl_attr(struct kvm_device *dev,
int (*accessor)(struct kvm_device *dev,
struct kvm_device_attr *attr),
@@ -2936,6 +2946,7 @@ static const struct file_operations kvm_device_fops = {
.unlocked_ioctl = kvm_device_ioctl,
.release = kvm_device_release,
KVM_COMPAT(kvm_device_ioctl),
+ .mmap = kvm_device_mmap,
};
struct kvm_device *kvm_device_from_filp(struct file *filp)
--
2.20.1
[PATCH v5 10/16] KVM: PPC: Book3S HV: XIVE: add get/set accessors for the VP XIVE state
The state of the thread interrupt management registers needs to be
collected for migration. These registers are cached under the
'xive_saved_state.w01' field of the VCPU when the VPCU context is
pulled from the HW thread. An OPAL call retrieves the backup of the
IPB register in the underlying XIVE NVT structure and merges it in the
KVM state.
Signed-off-by: Cédric Le Goater
Reviewed-by: David Gibson
---
Changes since v4:
- add documentation in Documentation/virtual/kvm/api.txt
arch/powerpc/include/asm/kvm_ppc.h | 11
arch/powerpc/include/uapi/asm/kvm.h| 2 +
arch/powerpc/kvm/book3s.c | 24 +++
arch/powerpc/kvm/book3s_xive_native.c | 76 ++
Documentation/virtual/kvm/api.txt | 1 +
Documentation/virtual/kvm/devices/xive.txt | 17 +
6 files changed, 131 insertions(+)
diff --git a/arch/powerpc/include/asm/kvm_ppc.h
b/arch/powerpc/include/asm/kvm_ppc.h
index 6928a35ac3c7..0579c9b253db 100644
--- a/arch/powerpc/include/asm/kvm_ppc.h
+++ b/arch/powerpc/include/asm/kvm_ppc.h
@@ -273,6 +273,7 @@ union kvmppc_one_reg {
u64 addr;
u64 length;
} vpaval;
+ u64 xive_timaval[2];
};
struct kvmppc_ops {
@@ -605,6 +606,10 @@ extern int kvmppc_xive_native_connect_vcpu(struct
kvm_device *dev,
extern void kvmppc_xive_native_cleanup_vcpu(struct kvm_vcpu *vcpu);
extern void kvmppc_xive_native_init_module(void);
extern void kvmppc_xive_native_exit_module(void);
+extern int kvmppc_xive_native_get_vp(struct kvm_vcpu *vcpu,
+union kvmppc_one_reg *val);
+extern int kvmppc_xive_native_set_vp(struct kvm_vcpu *vcpu,
+union kvmppc_one_reg *val);
#else
static inline int kvmppc_xive_set_xive(struct kvm *kvm, u32 irq, u32 server,
@@ -637,6 +642,12 @@ static inline int kvmppc_xive_native_connect_vcpu(struct
kvm_device *dev,
static inline void kvmppc_xive_native_cleanup_vcpu(struct kvm_vcpu *vcpu) { }
static inline void kvmppc_xive_native_init_module(void) { }
static inline void kvmppc_xive_native_exit_module(void) { }
+static inline int kvmppc_xive_native_get_vp(struct kvm_vcpu *vcpu,
+ union kvmppc_one_reg *val)
+{ return 0; }
+static inline int kvmppc_xive_native_set_vp(struct kvm_vcpu *vcpu,
+ union kvmppc_one_reg *val)
+{ return -ENOENT; }
#endif /* CONFIG_KVM_XIVE */
diff --git a/arch/powerpc/include/uapi/asm/kvm.h
b/arch/powerpc/include/uapi/asm/kvm.h
index 12744608a61c..cd3f16b70a2e 100644
--- a/arch/powerpc/include/uapi/asm/kvm.h
+++ b/arch/powerpc/include/uapi/asm/kvm.h
@@ -482,6 +482,8 @@ struct kvm_ppc_cpu_char {
#define KVM_REG_PPC_ICP_PPRI_SHIFT16 /* pending irq priority */
#define KVM_REG_PPC_ICP_PPRI_MASK 0xff
+#define KVM_REG_PPC_VP_STATE (KVM_REG_PPC | KVM_REG_SIZE_U128 | 0x8d)
+
/* Device control API: PPC-specific devices */
#define KVM_DEV_MPIC_GRP_MISC 1
#define KVM_DEV_MPIC_BASE_ADDR 0 /* 64-bit */
diff --git a/arch/powerpc/kvm/book3s.c b/arch/powerpc/kvm/book3s.c
index 7c3348fa27e1..efd15101eef0 100644
--- a/arch/powerpc/kvm/book3s.c
+++ b/arch/powerpc/kvm/book3s.c
@@ -651,6 +651,18 @@ int kvmppc_get_one_reg(struct kvm_vcpu *vcpu, u64 id,
*val = get_reg_val(id,
kvmppc_xics_get_icp(vcpu));
break;
#endif /* CONFIG_KVM_XICS */
+#ifdef CONFIG_KVM_XIVE
+ case KVM_REG_PPC_VP_STATE:
+ if (!vcpu->arch.xive_vcpu) {
+ r = -ENXIO;
+ break;
+ }
+ if (xive_enabled())
+ r = kvmppc_xive_native_get_vp(vcpu, val);
+ else
+ r = -ENXIO;
+ break;
+#endif /* CONFIG_KVM_XIVE */
case KVM_REG_PPC_FSCR:
*val = get_reg_val(id, vcpu->arch.fscr);
break;
@@ -724,6 +736,18 @@ int kvmppc_set_one_reg(struct kvm_vcpu *vcpu, u64 id,
r = kvmppc_xics_set_icp(vcpu, set_reg_val(id,
*val));
break;
#endif /* CONFIG_KVM_XICS */
+#ifdef CONFIG_KVM_XIVE
+ case KVM_REG_PPC_VP_STATE:
+ if (!vcpu->arch.xive_vcpu) {
+ r = -ENXIO;
+ break;
+ }
+ if (xive_enabled())
+ r = kvmppc_xive_native_set_vp(vcpu, val);
+ else
+ r = -ENXIO;
+ break;
+#endif /* CONFIG_KVM_XIVE */
case KVM_REG_PPC_FSCR:
vcpu->arch.fscr = set_reg_val(id, *val);
break;
diff --git a/arch/powerpc/kvm/book3s_xi
[PATCH v5 06/16] KVM: PPC: Book3S HV: XIVE: add controls for the EQ configuration
These controls will be used by the H_INT_SET_QUEUE_CONFIG and
H_INT_GET_QUEUE_CONFIG hcalls from QEMU to configure the underlying
Event Queue in the XIVE IC. They will also be used to restore the
configuration of the XIVE EQs and to capture the internal run-time
state of the EQs. Both 'get' and 'set' rely on an OPAL call to access
the EQ toggle bit and EQ index which are updated by the XIVE IC when
event notifications are enqueued in the EQ.
The value of the guest physical address of the event queue is saved in
the XIVE internal xive_q structure for later use. That is when
migration needs to mark the EQ pages dirty to capture a consistent
memory state of the VM.
To be noted that H_INT_SET_QUEUE_CONFIG does not require the extra
OPAL call setting the EQ toggle bit and EQ index to configure the EQ,
but restoring the EQ state will.
Signed-off-by: Cédric Le Goater
---
Changes since v4 :
- add check on EQ page alignment
- add requirement on KVM_XIVE_EQ_ALWAYS_NOTIFY
arch/powerpc/include/asm/xive.h| 2 +
arch/powerpc/include/uapi/asm/kvm.h| 19 ++
arch/powerpc/kvm/book3s_xive.h | 2 +
arch/powerpc/kvm/book3s_xive.c | 15 +-
arch/powerpc/kvm/book3s_xive_native.c | 249 +
Documentation/virtual/kvm/devices/xive.txt | 34 +++
6 files changed, 315 insertions(+), 6 deletions(-)
diff --git a/arch/powerpc/include/asm/xive.h b/arch/powerpc/include/asm/xive.h
index b579a943407b..c4e88abd3b67 100644
--- a/arch/powerpc/include/asm/xive.h
+++ b/arch/powerpc/include/asm/xive.h
@@ -73,6 +73,8 @@ struct xive_q {
u32 esc_irq;
atomic_tcount;
atomic_tpending_count;
+ u64 guest_qaddr;
+ u32 guest_qshift;
};
/* Global enable flags for the XIVE support */
diff --git a/arch/powerpc/include/uapi/asm/kvm.h
b/arch/powerpc/include/uapi/asm/kvm.h
index e8161e21629b..85005400fd86 100644
--- a/arch/powerpc/include/uapi/asm/kvm.h
+++ b/arch/powerpc/include/uapi/asm/kvm.h
@@ -681,6 +681,7 @@ struct kvm_ppc_cpu_char {
#define KVM_DEV_XIVE_GRP_CTRL 1
#define KVM_DEV_XIVE_GRP_SOURCE2 /* 64-bit source
identifier */
#define KVM_DEV_XIVE_GRP_SOURCE_CONFIG 3 /* 64-bit source identifier */
+#define KVM_DEV_XIVE_GRP_EQ_CONFIG 4 /* 64-bit EQ identifier */
/* Layout of 64-bit XIVE source attribute values */
#define KVM_XIVE_LEVEL_SENSITIVE (1ULL << 0)
@@ -696,4 +697,22 @@ struct kvm_ppc_cpu_char {
#define KVM_XIVE_SOURCE_EISN_SHIFT 33
#define KVM_XIVE_SOURCE_EISN_MASK 0xfffeULL
+/* Layout of 64-bit EQ identifier */
+#define KVM_XIVE_EQ_PRIORITY_SHIFT 0
+#define KVM_XIVE_EQ_PRIORITY_MASK 0x7
+#define KVM_XIVE_EQ_SERVER_SHIFT 3
+#define KVM_XIVE_EQ_SERVER_MASK0xfff8ULL
+
+/* Layout of EQ configuration values (64 bytes) */
+struct kvm_ppc_xive_eq {
+ __u32 flags;
+ __u32 qshift;
+ __u64 qaddr;
+ __u32 qtoggle;
+ __u32 qindex;
+ __u8 pad[40];
+};
+
+#define KVM_XIVE_EQ_ALWAYS_NOTIFY 0x0001
+
#endif /* __LINUX_KVM_POWERPC_H */
diff --git a/arch/powerpc/kvm/book3s_xive.h b/arch/powerpc/kvm/book3s_xive.h
index ae26fe653d98..622f594d93e1 100644
--- a/arch/powerpc/kvm/book3s_xive.h
+++ b/arch/powerpc/kvm/book3s_xive.h
@@ -272,6 +272,8 @@ struct kvmppc_xive_src_block *kvmppc_xive_create_src_block(
struct kvmppc_xive *xive, int irq);
void kvmppc_xive_free_sources(struct kvmppc_xive_src_block *sb);
int kvmppc_xive_select_target(struct kvm *kvm, u32 *server, u8 prio);
+int kvmppc_xive_attach_escalation(struct kvm_vcpu *vcpu, u8 prio,
+ bool single_escalation);
#endif /* CONFIG_KVM_XICS */
#endif /* _KVM_PPC_BOOK3S_XICS_H */
diff --git a/arch/powerpc/kvm/book3s_xive.c b/arch/powerpc/kvm/book3s_xive.c
index e09f3addffe5..c1b7aa7dbc28 100644
--- a/arch/powerpc/kvm/book3s_xive.c
+++ b/arch/powerpc/kvm/book3s_xive.c
@@ -166,7 +166,8 @@ static irqreturn_t xive_esc_irq(int irq, void *data)
return IRQ_HANDLED;
}
-static int xive_attach_escalation(struct kvm_vcpu *vcpu, u8 prio)
+int kvmppc_xive_attach_escalation(struct kvm_vcpu *vcpu, u8 prio,
+ bool single_escalation)
{
struct kvmppc_xive_vcpu *xc = vcpu->arch.xive_vcpu;
struct xive_q *q = &xc->queues[prio];
@@ -185,7 +186,7 @@ static int xive_attach_escalation(struct kvm_vcpu *vcpu, u8
prio)
return -EIO;
}
- if (xc->xive->single_escalation)
+ if (single_escalation)
name = kasprintf(GFP_KERNEL, "kvm-%d-%d",
vcpu->kvm->arch.lpid, xc->server_num);
else
@@ -217,7 +218,7 @@ static int xive_attach_escalation(struct kvm_vcpu *vcpu, u8
prio)
* interrupt, thus leaving it effectively masked after
* it fires once.
*/
- i
[PATCH v5 05/16] KVM: PPC: Book3S HV: XIVE: add a control to configure a source
This control will be used by the H_INT_SET_SOURCE_CONFIG hcall from
QEMU to configure the target of a source and also to restore the
configuration of a source when migrating the VM.
The XIVE source interrupt structure is extended with the value of the
Effective Interrupt Source Number. The EISN is the interrupt number
pushed in the event queue that the guest OS will use to dispatch
events internally. Caching the EISN value in KVM eases the test when
checking if a reconfiguration is indeed needed.
Signed-off-by: Cédric Le Goater
Reviewed-by: David Gibson
---
arch/powerpc/include/uapi/asm/kvm.h| 11 +++
arch/powerpc/kvm/book3s_xive.h | 4 +
arch/powerpc/kvm/book3s_xive.c | 5 +-
arch/powerpc/kvm/book3s_xive_native.c | 97 ++
Documentation/virtual/kvm/devices/xive.txt | 21 +
5 files changed, 136 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/include/uapi/asm/kvm.h
b/arch/powerpc/include/uapi/asm/kvm.h
index d468294c2a67..e8161e21629b 100644
--- a/arch/powerpc/include/uapi/asm/kvm.h
+++ b/arch/powerpc/include/uapi/asm/kvm.h
@@ -680,9 +680,20 @@ struct kvm_ppc_cpu_char {
/* POWER9 XIVE Native Interrupt Controller */
#define KVM_DEV_XIVE_GRP_CTRL 1
#define KVM_DEV_XIVE_GRP_SOURCE2 /* 64-bit source
identifier */
+#define KVM_DEV_XIVE_GRP_SOURCE_CONFIG 3 /* 64-bit source identifier */
/* Layout of 64-bit XIVE source attribute values */
#define KVM_XIVE_LEVEL_SENSITIVE (1ULL << 0)
#define KVM_XIVE_LEVEL_ASSERTED(1ULL << 1)
+/* Layout of 64-bit XIVE source configuration attribute values */
+#define KVM_XIVE_SOURCE_PRIORITY_SHIFT 0
+#define KVM_XIVE_SOURCE_PRIORITY_MASK 0x7
+#define KVM_XIVE_SOURCE_SERVER_SHIFT 3
+#define KVM_XIVE_SOURCE_SERVER_MASK0xfff8ULL
+#define KVM_XIVE_SOURCE_MASKED_SHIFT 32
+#define KVM_XIVE_SOURCE_MASKED_MASK0x1ULL
+#define KVM_XIVE_SOURCE_EISN_SHIFT 33
+#define KVM_XIVE_SOURCE_EISN_MASK 0xfffeULL
+
#endif /* __LINUX_KVM_POWERPC_H */
diff --git a/arch/powerpc/kvm/book3s_xive.h b/arch/powerpc/kvm/book3s_xive.h
index 1be921cb5dcb..ae26fe653d98 100644
--- a/arch/powerpc/kvm/book3s_xive.h
+++ b/arch/powerpc/kvm/book3s_xive.h
@@ -61,6 +61,9 @@ struct kvmppc_xive_irq_state {
bool saved_p;
bool saved_q;
u8 saved_scan_prio;
+
+ /* Xive native */
+ u32 eisn; /* Guest Effective IRQ number */
};
/* Select the "right" interrupt (IPI vs. passthrough) */
@@ -268,6 +271,7 @@ int kvmppc_xive_debug_show_queues(struct seq_file *m,
struct kvm_vcpu *vcpu);
struct kvmppc_xive_src_block *kvmppc_xive_create_src_block(
struct kvmppc_xive *xive, int irq);
void kvmppc_xive_free_sources(struct kvmppc_xive_src_block *sb);
+int kvmppc_xive_select_target(struct kvm *kvm, u32 *server, u8 prio);
#endif /* CONFIG_KVM_XICS */
#endif /* _KVM_PPC_BOOK3S_XICS_H */
diff --git a/arch/powerpc/kvm/book3s_xive.c b/arch/powerpc/kvm/book3s_xive.c
index 6c9f9fd0855f..e09f3addffe5 100644
--- a/arch/powerpc/kvm/book3s_xive.c
+++ b/arch/powerpc/kvm/book3s_xive.c
@@ -342,7 +342,7 @@ static int xive_try_pick_queue(struct kvm_vcpu *vcpu, u8
prio)
return atomic_add_unless(&q->count, 1, max) ? 0 : -EBUSY;
}
-static int xive_select_target(struct kvm *kvm, u32 *server, u8 prio)
+int kvmppc_xive_select_target(struct kvm *kvm, u32 *server, u8 prio)
{
struct kvm_vcpu *vcpu;
int i, rc;
@@ -530,7 +530,7 @@ static int xive_target_interrupt(struct kvm *kvm,
* priority. The count for that new target will have
* already been incremented.
*/
- rc = xive_select_target(kvm, &server, prio);
+ rc = kvmppc_xive_select_target(kvm, &server, prio);
/*
* We failed to find a target ? Not much we can do
@@ -1504,6 +1504,7 @@ struct kvmppc_xive_src_block
*kvmppc_xive_create_src_block(
for (i = 0; i < KVMPPC_XICS_IRQ_PER_ICS; i++) {
sb->irq_state[i].number = (bid << KVMPPC_XICS_ICS_SHIFT) | i;
+ sb->irq_state[i].eisn = 0;
sb->irq_state[i].guest_priority = MASKED;
sb->irq_state[i].saved_priority = MASKED;
sb->irq_state[i].act_priority = MASKED;
diff --git a/arch/powerpc/kvm/book3s_xive_native.c
b/arch/powerpc/kvm/book3s_xive_native.c
index 5f2bd6c137b7..492825a35958 100644
--- a/arch/powerpc/kvm/book3s_xive_native.c
+++ b/arch/powerpc/kvm/book3s_xive_native.c
@@ -242,6 +242,99 @@ static int kvmppc_xive_native_set_source(struct
kvmppc_xive *xive, long irq,
return rc;
}
+static int kvmppc_xive_native_update_source_config(struct kvmppc_xive *xive,
+ struct kvmppc_xive_src_block *sb,
+ struct kvmppc_xive_irq_state *state,
+ u32 server, u8 priority, bool masked,
+ u32 ei
[PATCH v5 04/16] KVM: PPC: Book3S HV: XIVE: add a control to initialize a source
The XIVE KVM device maintains a list of interrupt sources for the VM
which are allocated in the pool of generic interrupts (IPIs) of the
main XIVE IC controller. These are used for the CPU IPIs as well as
for virtual device interrupts. The IRQ number space is defined by
QEMU.
The XIVE device reuses the source structures of the XICS-on-XIVE
device for the source blocks (2-level tree) and for the source
interrupts. Under XIVE native, the source interrupt caches mostly
configuration information and is less used than under the XICS-on-XIVE
device in which hcalls are still necessary at run-time.
When a source is initialized in KVM, an IPI interrupt source is simply
allocated at the OPAL level and then MASKED. KVM only needs to know
about its type: LSI or MSI.
Signed-off-by: Cédric Le Goater
Reviewed-by: David Gibson
---
arch/powerpc/include/uapi/asm/kvm.h| 5 +
arch/powerpc/kvm/book3s_xive.h | 10 ++
arch/powerpc/kvm/book3s_xive.c | 8 +-
arch/powerpc/kvm/book3s_xive_native.c | 106 +
Documentation/virtual/kvm/devices/xive.txt | 15 +++
5 files changed, 140 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/include/uapi/asm/kvm.h
b/arch/powerpc/include/uapi/asm/kvm.h
index be0ce1f17625..d468294c2a67 100644
--- a/arch/powerpc/include/uapi/asm/kvm.h
+++ b/arch/powerpc/include/uapi/asm/kvm.h
@@ -679,5 +679,10 @@ struct kvm_ppc_cpu_char {
/* POWER9 XIVE Native Interrupt Controller */
#define KVM_DEV_XIVE_GRP_CTRL 1
+#define KVM_DEV_XIVE_GRP_SOURCE2 /* 64-bit source
identifier */
+
+/* Layout of 64-bit XIVE source attribute values */
+#define KVM_XIVE_LEVEL_SENSITIVE (1ULL << 0)
+#define KVM_XIVE_LEVEL_ASSERTED(1ULL << 1)
#endif /* __LINUX_KVM_POWERPC_H */
diff --git a/arch/powerpc/kvm/book3s_xive.h b/arch/powerpc/kvm/book3s_xive.h
index d366df69b9cb..1be921cb5dcb 100644
--- a/arch/powerpc/kvm/book3s_xive.h
+++ b/arch/powerpc/kvm/book3s_xive.h
@@ -12,6 +12,13 @@
#ifdef CONFIG_KVM_XICS
#include "book3s_xics.h"
+/*
+ * The XIVE Interrupt source numbers are within the range 0 to
+ * KVMPPC_XICS_NR_IRQS.
+ */
+#define KVMPPC_XIVE_FIRST_IRQ 0
+#define KVMPPC_XIVE_NR_IRQSKVMPPC_XICS_NR_IRQS
+
/*
* State for one guest irq source.
*
@@ -258,6 +265,9 @@ extern int (*__xive_vm_h_eoi)(struct kvm_vcpu *vcpu,
unsigned long xirr);
*/
void kvmppc_xive_disable_vcpu_interrupts(struct kvm_vcpu *vcpu);
int kvmppc_xive_debug_show_queues(struct seq_file *m, struct kvm_vcpu *vcpu);
+struct kvmppc_xive_src_block *kvmppc_xive_create_src_block(
+ struct kvmppc_xive *xive, int irq);
+void kvmppc_xive_free_sources(struct kvmppc_xive_src_block *sb);
#endif /* CONFIG_KVM_XICS */
#endif /* _KVM_PPC_BOOK3S_XICS_H */
diff --git a/arch/powerpc/kvm/book3s_xive.c b/arch/powerpc/kvm/book3s_xive.c
index e7f1ada1c3de..6c9f9fd0855f 100644
--- a/arch/powerpc/kvm/book3s_xive.c
+++ b/arch/powerpc/kvm/book3s_xive.c
@@ -1480,8 +1480,8 @@ static int xive_get_source(struct kvmppc_xive *xive, long
irq, u64 addr)
return 0;
}
-static struct kvmppc_xive_src_block *xive_create_src_block(struct kvmppc_xive
*xive,
- int irq)
+struct kvmppc_xive_src_block *kvmppc_xive_create_src_block(
+ struct kvmppc_xive *xive, int irq)
{
struct kvm *kvm = xive->kvm;
struct kvmppc_xive_src_block *sb;
@@ -1560,7 +1560,7 @@ static int xive_set_source(struct kvmppc_xive *xive, long
irq, u64 addr)
sb = kvmppc_xive_find_source(xive, irq, &idx);
if (!sb) {
pr_devel("No source, creating source block...\n");
- sb = xive_create_src_block(xive, irq);
+ sb = kvmppc_xive_create_src_block(xive, irq);
if (!sb) {
pr_devel("Failed to create block...\n");
return -ENOMEM;
@@ -1784,7 +1784,7 @@ static void kvmppc_xive_cleanup_irq(u32 hw_num, struct
xive_irq_data *xd)
xive_cleanup_irq_data(xd);
}
-static void kvmppc_xive_free_sources(struct kvmppc_xive_src_block *sb)
+void kvmppc_xive_free_sources(struct kvmppc_xive_src_block *sb)
{
int i;
diff --git a/arch/powerpc/kvm/book3s_xive_native.c
b/arch/powerpc/kvm/book3s_xive_native.c
index 6fa73cfd9d9c..5f2bd6c137b7 100644
--- a/arch/powerpc/kvm/book3s_xive_native.c
+++ b/arch/powerpc/kvm/book3s_xive_native.c
@@ -26,6 +26,17 @@
#include "book3s_xive.h"
+static u8 xive_vm_esb_load(struct xive_irq_data *xd, u32 offset)
+{
+ u64 val;
+
+ if (xd->flags & XIVE_IRQ_FLAG_SHIFT_BUG)
+ offset |= offset << 4;
+
+ val = in_be64(xd->eoi_mmio + offset);
+ return (u8)val;
+}
+
static void kvmppc_xive_native_cleanup_queue(struct kvm_vcpu *vcpu, int prio)
{
struct kvmppc_xive_vcpu *xc = vcpu->arch.xive_vcpu;
@@ -154,12 +165,94 @@ int kvmppc_xive_native_connect_vcpu(struct kvm_device
*dev,
return rc;
}
+static
[PATCH v5 03/16] KVM: PPC: Book3S HV: XIVE: introduce a new capability KVM_CAP_PPC_IRQ_XIVE
The user interface exposes a new capability KVM_CAP_PPC_IRQ_XIVE to
let QEMU connect the vCPU presenters to the XIVE KVM device if
required. The capability is not advertised for now as the full support
for the XIVE native exploitation mode is not yet available. When this
is case, the capability will be advertised on PowerNV Hypervisors
only. Nested guests (pseries KVM Hypervisor) are not supported.
Internally, the interface to the new KVM device is protected with a
new interrupt mode: KVMPPC_IRQ_XIVE.
Signed-off-by: Cédric Le Goater
Reviewed-by: David Gibson
---
arch/powerpc/include/asm/kvm_host.h | 1 +
arch/powerpc/include/asm/kvm_ppc.h| 13 +++
arch/powerpc/kvm/book3s_xive.h| 11 ++
include/uapi/linux/kvm.h | 1 +
arch/powerpc/kvm/book3s_xive.c| 88 ---
arch/powerpc/kvm/book3s_xive_native.c | 150 ++
arch/powerpc/kvm/powerpc.c| 36 +++
Documentation/virtual/kvm/api.txt | 9 ++
8 files changed, 268 insertions(+), 41 deletions(-)
diff --git a/arch/powerpc/include/asm/kvm_host.h
b/arch/powerpc/include/asm/kvm_host.h
index 008523224e7a..9cc6abdce1b9 100644
--- a/arch/powerpc/include/asm/kvm_host.h
+++ b/arch/powerpc/include/asm/kvm_host.h
@@ -450,6 +450,7 @@ struct kvmppc_passthru_irqmap {
#define KVMPPC_IRQ_DEFAULT 0
#define KVMPPC_IRQ_MPIC1
#define KVMPPC_IRQ_XICS2 /* Includes a XIVE option */
+#define KVMPPC_IRQ_XIVE3 /* XIVE native exploitation mode */
#define MMIO_HPTE_CACHE_SIZE 4
diff --git a/arch/powerpc/include/asm/kvm_ppc.h
b/arch/powerpc/include/asm/kvm_ppc.h
index f3383e76017a..6928a35ac3c7 100644
--- a/arch/powerpc/include/asm/kvm_ppc.h
+++ b/arch/powerpc/include/asm/kvm_ppc.h
@@ -595,6 +595,14 @@ extern int kvmppc_xive_set_irq(struct kvm *kvm, int
irq_source_id, u32 irq,
int level, bool line_status);
extern void kvmppc_xive_push_vcpu(struct kvm_vcpu *vcpu);
+static inline int kvmppc_xive_enabled(struct kvm_vcpu *vcpu)
+{
+ return vcpu->arch.irq_type == KVMPPC_IRQ_XIVE;
+}
+
+extern int kvmppc_xive_native_connect_vcpu(struct kvm_device *dev,
+ struct kvm_vcpu *vcpu, u32 cpu);
+extern void kvmppc_xive_native_cleanup_vcpu(struct kvm_vcpu *vcpu);
extern void kvmppc_xive_native_init_module(void);
extern void kvmppc_xive_native_exit_module(void);
@@ -622,6 +630,11 @@ static inline int kvmppc_xive_set_irq(struct kvm *kvm, int
irq_source_id, u32 ir
int level, bool line_status) { return
-ENODEV; }
static inline void kvmppc_xive_push_vcpu(struct kvm_vcpu *vcpu) { }
+static inline int kvmppc_xive_enabled(struct kvm_vcpu *vcpu)
+ { return 0; }
+static inline int kvmppc_xive_native_connect_vcpu(struct kvm_device *dev,
+ struct kvm_vcpu *vcpu, u32 cpu) { return -EBUSY; }
+static inline void kvmppc_xive_native_cleanup_vcpu(struct kvm_vcpu *vcpu) { }
static inline void kvmppc_xive_native_init_module(void) { }
static inline void kvmppc_xive_native_exit_module(void) { }
diff --git a/arch/powerpc/kvm/book3s_xive.h b/arch/powerpc/kvm/book3s_xive.h
index a08ae6fd4c51..d366df69b9cb 100644
--- a/arch/powerpc/kvm/book3s_xive.h
+++ b/arch/powerpc/kvm/book3s_xive.h
@@ -198,6 +198,11 @@ static inline struct kvmppc_xive_src_block
*kvmppc_xive_find_source(struct kvmpp
return xive->src_blocks[bid];
}
+static inline u32 kvmppc_xive_vp(struct kvmppc_xive *xive, u32 server)
+{
+ return xive->vp_base + kvmppc_pack_vcpu_id(xive->kvm, server);
+}
+
/*
* Mapping between guest priorities and host priorities
* is as follow.
@@ -248,5 +253,11 @@ extern int (*__xive_vm_h_ipi)(struct kvm_vcpu *vcpu,
unsigned long server,
extern int (*__xive_vm_h_cppr)(struct kvm_vcpu *vcpu, unsigned long cppr);
extern int (*__xive_vm_h_eoi)(struct kvm_vcpu *vcpu, unsigned long xirr);
+/*
+ * Common Xive routines for XICS-over-XIVE and XIVE native
+ */
+void kvmppc_xive_disable_vcpu_interrupts(struct kvm_vcpu *vcpu);
+int kvmppc_xive_debug_show_queues(struct seq_file *m, struct kvm_vcpu *vcpu);
+
#endif /* CONFIG_KVM_XICS */
#endif /* _KVM_PPC_BOOK3S_XICS_H */
diff --git a/include/uapi/linux/kvm.h b/include/uapi/linux/kvm.h
index e6368163d3a0..52bf74a1616e 100644
--- a/include/uapi/linux/kvm.h
+++ b/include/uapi/linux/kvm.h
@@ -988,6 +988,7 @@ struct kvm_ppc_resize_hpt {
#define KVM_CAP_ARM_VM_IPA_SIZE 165
#define KVM_CAP_MANUAL_DIRTY_LOG_PROTECT 166
#define KVM_CAP_HYPERV_CPUID 167
+#define KVM_CAP_PPC_IRQ_XIVE 168
#ifdef KVM_CAP_IRQ_ROUTING
diff --git a/arch/powerpc/kvm/book3s_xive.c b/arch/powerpc/kvm/book3s_xive.c
index f78d002f0fe0..e7f1ada1c3de 100644
--- a/arch/powerpc/kvm/book3s_xive.c
+++ b/arch/powerpc/kvm/book3s_xive.c
@@ -380,11 +380,6 @@ static int xive_select_target(struct kvm *kvm, u32
*server, u8 prio)
return -EBUSY;
}
-static u32 xive_vp(struct kvmppc_xive *x
[PATCH v5 01/16] powerpc/xive: add OPAL extensions for the XIVE native exploitation support
The support for XIVE native exploitation mode in Linux/KVM needs a
couple more OPAL calls to get and set the state of the XIVE internal
structures being used by a sPAPR guest.
Signed-off-by: Cédric Le Goater
Reviewed-by: David Gibson
---
arch/powerpc/include/asm/opal-api.h| 7 +-
arch/powerpc/include/asm/opal.h| 7 ++
arch/powerpc/include/asm/xive.h| 14 +++
arch/powerpc/platforms/powernv/opal-call.c | 3 +
arch/powerpc/sysdev/xive/native.c | 99 ++
5 files changed, 127 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/include/asm/opal-api.h
b/arch/powerpc/include/asm/opal-api.h
index 870fb7b239ea..e1d118ac61dc 100644
--- a/arch/powerpc/include/asm/opal-api.h
+++ b/arch/powerpc/include/asm/opal-api.h
@@ -186,8 +186,8 @@
#define OPAL_XIVE_FREE_IRQ 140
#define OPAL_XIVE_SYNC 141
#define OPAL_XIVE_DUMP 142
-#define OPAL_XIVE_RESERVED3143
-#define OPAL_XIVE_RESERVED4144
+#define OPAL_XIVE_GET_QUEUE_STATE 143
+#define OPAL_XIVE_SET_QUEUE_STATE 144
#define OPAL_SIGNAL_SYSTEM_RESET 145
#define OPAL_NPU_INIT_CONTEXT 146
#define OPAL_NPU_DESTROY_CONTEXT 147
@@ -210,7 +210,8 @@
#define OPAL_PCI_GET_PBCQ_TUNNEL_BAR 164
#define OPAL_PCI_SET_PBCQ_TUNNEL_BAR 165
#defineOPAL_NX_COPROC_INIT 167
-#define OPAL_LAST 167
+#define OPAL_XIVE_GET_VP_STATE 170
+#define OPAL_LAST 170
#define QUIESCE_HOLD 1 /* Spin all calls at entry */
#define QUIESCE_REJECT 2 /* Fail all calls with OPAL_BUSY */
diff --git a/arch/powerpc/include/asm/opal.h b/arch/powerpc/include/asm/opal.h
index a55b01c90bb1..4e978d4dea5c 100644
--- a/arch/powerpc/include/asm/opal.h
+++ b/arch/powerpc/include/asm/opal.h
@@ -279,6 +279,13 @@ int64_t opal_xive_allocate_irq(uint32_t chip_id);
int64_t opal_xive_free_irq(uint32_t girq);
int64_t opal_xive_sync(uint32_t type, uint32_t id);
int64_t opal_xive_dump(uint32_t type, uint32_t id);
+int64_t opal_xive_get_queue_state(uint64_t vp, uint32_t prio,
+ __be32 *out_qtoggle,
+ __be32 *out_qindex);
+int64_t opal_xive_set_queue_state(uint64_t vp, uint32_t prio,
+ uint32_t qtoggle,
+ uint32_t qindex);
+int64_t opal_xive_get_vp_state(uint64_t vp, __be64 *out_w01);
int64_t opal_pci_set_p2p(uint64_t phb_init, uint64_t phb_target,
uint64_t desc, uint16_t pe_number);
diff --git a/arch/powerpc/include/asm/xive.h b/arch/powerpc/include/asm/xive.h
index 3c704f5dd3ae..b579a943407b 100644
--- a/arch/powerpc/include/asm/xive.h
+++ b/arch/powerpc/include/asm/xive.h
@@ -109,12 +109,26 @@ extern int xive_native_configure_queue(u32 vp_id, struct
xive_q *q, u8 prio,
extern void xive_native_disable_queue(u32 vp_id, struct xive_q *q, u8 prio);
extern void xive_native_sync_source(u32 hw_irq);
+extern void xive_native_sync_queue(u32 hw_irq);
extern bool is_xive_irq(struct irq_chip *chip);
extern int xive_native_enable_vp(u32 vp_id, bool single_escalation);
extern int xive_native_disable_vp(u32 vp_id);
extern int xive_native_get_vp_info(u32 vp_id, u32 *out_cam_id, u32
*out_chip_id);
extern bool xive_native_has_single_escalation(void);
+extern int xive_native_get_queue_info(u32 vp_id, uint32_t prio,
+ u64 *out_qpage,
+ u64 *out_qsize,
+ u64 *out_qeoi_page,
+ u32 *out_escalate_irq,
+ u64 *out_qflags);
+
+extern int xive_native_get_queue_state(u32 vp_id, uint32_t prio, u32 *qtoggle,
+ u32 *qindex);
+extern int xive_native_set_queue_state(u32 vp_id, uint32_t prio, u32 qtoggle,
+ u32 qindex);
+extern int xive_native_get_vp_state(u32 vp_id, u64 *out_state);
+
#else
static inline bool xive_enabled(void) { return false; }
diff --git a/arch/powerpc/platforms/powernv/opal-call.c
b/arch/powerpc/platforms/powernv/opal-call.c
index daad8c45c8e7..7472244e7f30 100644
--- a/arch/powerpc/platforms/powernv/opal-call.c
+++ b/arch/powerpc/platforms/powernv/opal-call.c
@@ -260,6 +260,9 @@ OPAL_CALL(opal_xive_get_vp_info,
OPAL_XIVE_GET_VP_INFO);
OPAL_CALL(opal_xive_set_vp_info, OPAL_XIVE_SET_VP_INFO);
OPAL_CALL(opal_xive_sync, OPAL_XIVE_SYNC);
OPAL_CALL(opal_xive_dump, OPAL_XIVE_DUMP);
+OPAL_CALL(opal_xive_get_queue_state, OPAL_XIVE_GET_QUEUE_STATE);
+OPAL_CALL(opal_xive_set_queue_state, OPAL_XIVE_SET_QUEUE_STATE);
+OPAL_CALL(opal_xive_get
Re: [PATCH-tip 00/22] locking/rwsem: Rework rwsem-xadd & enable new rwsem features
On 04/10/2019 04:15 AM, huang ying wrote: > Hi, Waiman, > > What's the status of this patchset? And its merging plan? > > Best Regards, > Huang, Ying I have broken the patch into 3 parts (0/1/2) and rewritten some of them. Part 0 has been merged into tip. Parts 1 and 2 are still under testing. Cheers, Longman
Re: [PATCH 21/21] docs: hwmon: Add an index file and rename docs to *.rst
Hello, On Wed, Apr 10, 2019 at 08:12:11AM -0300, Mauro Carvalho Chehab wrote: > Now that all files were converted to ReST format, rename them > and add an index. > > Signed-off-by: Mauro Carvalho Chehab > --- [...] > diff --git a/Documentation/hwmon/submitting-patches > b/Documentation/hwmon/submitting-patches.rst > similarity index 99% > rename from Documentation/hwmon/submitting-patches > rename to Documentation/hwmon/submitting-patches.rst > index 12540b7d9b50..6120db7556aa 100644 > --- a/Documentation/hwmon/submitting-patches > +++ b/Documentation/hwmon/submitting-patches.rst I'd additionally suggest: diff --git a/Documentation/hwmon/submitting-patches b/Documentation/hwmon/submitting-patches.rst index f88221b46153..a86be4b9 100644 --- a/Documentation/hwmon/submitting-patches +++ b/Documentation/hwmon/submitting-patches.rst @@ -38,7 +38,7 @@ increase the chances of your change being accepted. 2. Adding functionality to existing drivers --- -* Make sure the documentation in Documentation/hwmon/ is up to +* Make sure the documentation in Documentation/hwmon/.rst is up to date. * Make sure the information in Kconfig is up to date. @@ -60,7 +60,7 @@ increase the chances of your change being accepted. * Consider adding yourself to MAINTAINERS. -* Document the driver in Documentation/hwmon/. +* Document the driver in Documentation/hwmon/.rst. * Add the driver to Kconfig and Makefile in alphabetical order. Thanks, Jonathan Neuschäfer signature.asc Description: PGP signature
Re: [PATCH V2] ASoC: fsl_esai: replace fall-through with break
On 4/9/19 9:42 PM, S.j. Wang wrote:
> case ESAI_HCKT_EXTAL and case ESAI_HCKR_EXTAL should be independent of
> each other, so replace fall-through with break.
>
I think you should change the subject line to:
fix missing break in switch statement
...because you are fixing a bug, and it's important to put emphasis on
that in the subject line.
Also, notice that this bug has been out there for more than 5 years now,
so you should also tag this for stable.
Thanks
--
Gustavo
> Fixes: 43d24e76b698 ("ASoC: fsl_esai: Add ESAI CPU DAI driver")
>
> Signed-off-by: Shengjiu Wang
> ---
> Changes in v2
> - fix the fixes tag.
>
> sound/soc/fsl/fsl_esai.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/sound/soc/fsl/fsl_esai.c b/sound/soc/fsl/fsl_esai.c
> index c7410bbfd2af..bad0dfed6b68 100644
> --- a/sound/soc/fsl/fsl_esai.c
> +++ b/sound/soc/fsl/fsl_esai.c
> @@ -251,7 +251,7 @@ static int fsl_esai_set_dai_sysclk(struct snd_soc_dai
> *dai, int clk_id,
> break;
> case ESAI_HCKT_EXTAL:
> ecr |= ESAI_ECR_ETI;
> - /* fall through */
> + break;
> case ESAI_HCKR_EXTAL:
> ecr |= esai_priv->synchronous ? ESAI_ECR_ETI : ESAI_ECR_ERI;
> break;
>
Re: powerpc/mm: Define MAX_PHYSMEM_BITS for all 64-bit configs
On Tue, 2019-04-09 at 06:03:24 UTC, Michael Ellerman wrote:
> The recent commit 8bc086899816 ("powerpc/mm: Only define
> MAX_PHYSMEM_BITS in SPARSEMEM configurations") removed our definition
> of MAX_PHYSMEM_BITS when SPARSEMEM is disabled.
>
> This inadvertently broke some 64-bit FLATMEM using configs with eg:
>
> arch/powerpc/include/asm/book3s/64/mmu-hash.h:584:6: error:
> "MAX_PHYSMEM_BITS" is not defined, evaluates to 0
>#if (MAX_PHYSMEM_BITS > MAX_EA_BITS_PER_CONTEXT)
> ^~~~
>
> Fix it by making sure we define MAX_PHYSMEM_BITS for all 64-bit
> configs regardless of SPARSEMEM.
>
> Fixes: 8bc086899816 ("powerpc/mm: Only define MAX_PHYSMEM_BITS in SPARSEMEM
> configurations")
> Reported-by: Andreas Schwab
> Reported-by: Hugh Dickins
> Signed-off-by: Michael Ellerman
> Reviewed-by: Aneesh Kumar K.V
Applied to powerpc fixes.
https://git.kernel.org/powerpc/c/cf7cf6977f531acd5dfe55250d0ee8cb
cheers
Re: powerpc/64s/radix: Fix radix segment exception handling
On Fri, 2019-03-29 at 07:42:57 UTC, Nicholas Piggin wrote:
> Commit 48e7b76957 ("powerpc/64s/hash: Convert SLB miss handlers to C")
> broke the radix-mode segment exception handler. In radix mode, this is
> exception is not an SLB miss, rather it signals that the EA is outside
> the range translated by any page table.
>
> The commit lost the radix feature alternate code patch, which can
> cause faults to some EAs to kernel BUG at arch/powerpc/mm/slb.c:639!
>
> The original radix code would send faults to slb_miss_large_addr,
> which would end up faulting due to slb_addr_limit being 0. This patch
> sends radix directly to do_bad_slb_fault, which is a bit clearer.
>
> Fixes: 48e7b76957 ("powerpc/64s/hash: Convert SLB miss handlers to C")
> Cc: Aneesh Kumar K.V
> Reported-by: Anton Blanchard
> Signed-off-by: Nicholas Piggin
> Reviewed-by: Aneesh Kumar K.V
Applied to powerpc fixes, thanks.
https://git.kernel.org/powerpc/c/7100e8704b61247649c50551b965e71d
cheers
Re: [PATCH v4 3/4] ASoC: imx-audmix: fix object reference leaks in probe
On Wed, Apr 10, 2019 at 8:06 AM Viorel Suman wrote: > > Release the reference to the underlying device taken > by of_find_device_by_node() call. > > Signed-off-by: Viorel Suman > Reported-by: Julia Lawall > Acked-by: Nicolin Chen Please provide a Fixes tag.
Re: [PATCH v4 2/4] ASoC: fsl_audmix: remove "model" attribute from DT document
On Wed, Apr 10, 2019 at 8:06 AM Viorel Suman wrote: > > Remove "model" attribute from fsl_audmix DT document. Please provide the reasoning.
Re: [PATCH RFC 1/5] cpu/speculation: Add 'cpu_spec_mitigations=' cmdline options
On Wed, 10 Apr 2019, Michael Ellerman wrote: > Josh Poimboeuf writes: > > > On Fri, Apr 05, 2019 at 06:01:36PM +0200, Borislav Petkov wrote: > >> Thinking about this more, we can shave off the first 4 chars and have it > >> be: > >> > >> spec_mitigations= > >> > >> I think it is painfully clear which speculation mitigations we mean. And > >> the other switches don't have "cpu_" prefixes too so... > > > > Sure, I'm ok with renaming it to that, if there are no objections. > > What about when we have a mitigation for a non-speculation related bug :) Those kind of silicon bugs are usually mitigated unconditionally. Thanks, tglx
Re: [PATCH v5 4/6] s390/pci: add support for generic boot option iommu.dma_mode
On Tue, 9 Apr 2019, Zhen Lei wrote: > s390_iommu=strict is equivalent to iommu.dma_mode=strict. > > Signed-off-by: Zhen Lei Acked-by: Sebastian Ott
Re: [PATCH V2] ASoC: fsl_esai: replace fall-through with break
On Wed, Apr 10, 2019 at 02:42:45AM +, S.j. Wang wrote: > case ESAI_HCKT_EXTAL and case ESAI_HCKR_EXTAL should be independent of > each other, so replace fall-through with break. This doesn't apply against current code, please check and resend. signature.asc Description: PGP signature
[PATCH 21/21] docs: hwmon: Add an index file and rename docs to *.rst
Now that all files were converted to ReST format, rename them
and add an index.
Signed-off-by: Mauro Carvalho Chehab
---
.../devicetree/bindings/hwmon/g762.txt| 2 +-
Documentation/hwmon/{ab8500 => ab8500.rst}| 2 +-
...guru-datasheet => abituguru-datasheet.rst} | 0
.../hwmon/{abituguru => abituguru.rst}| 0
.../hwmon/{abituguru3 => abituguru3.rst} | 0
Documentation/hwmon/{abx500 => abx500.rst}| 0
...{acpi_power_meter => acpi_power_meter.rst} | 2 +-
Documentation/hwmon/{ad7314 => ad7314.rst}| 0
.../hwmon/{adc128d818 => adc128d818.rst} | 0
Documentation/hwmon/{adm1021 => adm1021.rst} | 0
Documentation/hwmon/{adm1025 => adm1025.rst} | 0
Documentation/hwmon/{adm1026 => adm1026.rst} | 0
Documentation/hwmon/{adm1031 => adm1031.rst} | 0
Documentation/hwmon/{adm1275 => adm1275.rst} | 4 +-
Documentation/hwmon/{adm9240 => adm9240.rst} | 0
Documentation/hwmon/{ads1015 => ads1015.rst} | 0
Documentation/hwmon/{ads7828 => ads7828.rst} | 0
Documentation/hwmon/{adt7410 => adt7410.rst} | 0
Documentation/hwmon/{adt7411 => adt7411.rst} | 0
Documentation/hwmon/{adt7462 => adt7462.rst} | 0
Documentation/hwmon/{adt7470 => adt7470.rst} | 0
Documentation/hwmon/{adt7475 => adt7475.rst} | 0
Documentation/hwmon/{amc6821 => amc6821.rst} | 0
Documentation/hwmon/{asb100 => asb100.rst}| 0
Documentation/hwmon/{asc7621 => asc7621.rst} | 0
...{aspeed-pwm-tacho => aspeed-pwm-tacho.rst} | 0
.../hwmon/{coretemp => coretemp.rst} | 0
Documentation/hwmon/{da9052 => da9052.rst}| 0
Documentation/hwmon/{da9055 => da9055.rst}| 0
Documentation/hwmon/{dme1737 => dme1737.rst} | 0
Documentation/hwmon/{ds1621 => ds1621.rst}| 0
Documentation/hwmon/{ds620 => ds620.rst} | 0
Documentation/hwmon/{emc1403 => emc1403.rst} | 0
Documentation/hwmon/{emc2103 => emc2103.rst} | 0
.../hwmon/{emc6w201 => emc6w201.rst} | 0
Documentation/hwmon/{f71805f => f71805f.rst} | 0
.../hwmon/{f71882fg => f71882fg.rst} | 0
.../hwmon/{fam15h_power => fam15h_power.rst} | 0
.../hwmon/{ftsteutates => ftsteutates.rst}| 0
Documentation/hwmon/{g760a => g760a.rst} | 0
Documentation/hwmon/{g762 => g762.rst}| 2 +-
Documentation/hwmon/{gl518sm => gl518sm.rst} | 0
Documentation/hwmon/{hih6130 => hih6130.rst} | 0
...on-kernel-api.txt => hwmon-kernel-api.rst} | 4 +-
.../hwmon/{ibm-cffps => ibm-cffps.rst}| 0
Documentation/hwmon/{ibmaem => ibmaem.rst}| 0
.../hwmon/{ibmpowernv => ibmpowernv.rst} | 0
Documentation/hwmon/{ina209 => ina209.rst}| 0
Documentation/hwmon/{ina2xx => ina2xx.rst}| 2 +-
Documentation/hwmon/{ina3221 => ina3221.rst} | 0
Documentation/hwmon/index.rst | 179 ++
Documentation/hwmon/{ir35221 => ir35221.rst} | 0
Documentation/hwmon/{it87 => it87.rst}| 0
Documentation/hwmon/{jc42 => jc42.rst}| 0
Documentation/hwmon/{k10temp => k10temp.rst} | 0
Documentation/hwmon/{k8temp => k8temp.rst}| 0
.../hwmon/{lineage-pem => lineage-pem.rst}| 0
Documentation/hwmon/{lm25066 => lm25066.rst} | 2 +-
Documentation/hwmon/{lm63 => lm63.rst}| 0
Documentation/hwmon/{lm70 => lm70.rst}| 0
Documentation/hwmon/{lm73 => lm73.rst}| 0
Documentation/hwmon/{lm75 => lm75.rst}| 0
Documentation/hwmon/{lm77 => lm77.rst}| 0
Documentation/hwmon/{lm78 => lm78.rst}| 0
Documentation/hwmon/{lm80 => lm80.rst}| 0
Documentation/hwmon/{lm83 => lm83.rst}| 0
Documentation/hwmon/{lm85 => lm85.rst}| 0
Documentation/hwmon/{lm87 => lm87.rst}| 0
Documentation/hwmon/{lm90 => lm90.rst}| 0
Documentation/hwmon/{lm92 => lm92.rst}| 0
Documentation/hwmon/{lm93 => lm93.rst}| 0
Documentation/hwmon/{lm95234 => lm95234.rst} | 0
Documentation/hwmon/{lm95245 => lm95245.rst} | 0
Documentation/hwmon/{ltc2945 => ltc2945.rst} | 0
Documentation/hwmon/{ltc2978 => ltc2978.rst} | 0
Documentation/hwmon/{ltc2990 => ltc2990.rst} | 0
Documentation/hwmon/{ltc3815 => ltc3815.rst} | 0
Documentation/hwmon/{ltc4151 => ltc4151.rst} | 0
Documentation/hwmon/{ltc4215 => ltc4215.rst} | 0
Documentation/hwmon/{ltc4245 => ltc4245.rst} | 0
Documentation/hwmon/{ltc4260 => ltc4260.rst} | 0
Documentation/hwmon/{ltc4261 => ltc4261.rst} | 0
.../hwmon/{max16064 => max16064.rst} | 2 +-
.../hwmon/{max16065 => max16065.rst} | 0
Documentation/hwmon/{max1619 => max1619.rst} | 0
Documentation/hwmon/{max1668 => max1668.rst} | 0
Documentation/hwmon/{max197 => max197.rst}| 0
.../hwmon/{max20751 => max20751.rst} | 2 +-
.../hwmon/{max31722 => max31722.rst} | 0
.../hwmon/{max31785 => max31785.rst} | 0
.../hwmon/{max31790 => max31790.rst} | 0
...
[PATCH 11/21] docs: hwmon: ibmpowernv: convert to ReST format
Convert ibmpowernv to ReST format, in order to allow it to be parsed by Sphinx. Signed-off-by: Mauro Carvalho Chehab --- Documentation/hwmon/ibmpowernv | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/hwmon/ibmpowernv b/Documentation/hwmon/ibmpowernv index 56468258711f..3f1feae3901c 100644 --- a/Documentation/hwmon/ibmpowernv +++ b/Documentation/hwmon/ibmpowernv @@ -2,6 +2,7 @@ Kernel Driver IBMPOWERNV Supported systems: + * Any recent IBM P servers based on POWERNV platform Author: Neelesh Gupta @@ -29,6 +30,7 @@ CONFIG_SENSORS_IBMPOWERNV. It can also be built as module 'ibmpowernv'. Sysfs attributes +=== === fanX_input Measured RPM value. fanX_min Threshold RPM for alert generation. fanX_fault 0: No fail condition @@ -78,3 +80,4 @@ currX_enable Enable/disable all current sensors belonging to the 0: Disable energyX_input Cumulative energy (microJoule) +=== === -- 2.20.1
Re: [PATCH v4 0/4] ASoC: fsl: audmix: remove "model" attribute and fix ref leaks
On Wed, Apr 10, 2019 at 11:06:35AM +, Viorel Suman wrote: > The latest audmix patch-set (v5) had the "model" attribute removed as > requested by Nicolin Chen, but looks like (v4) version of DAI driver > reached "for-next" branch - fix this by removing "model" attribute. > Asside of this fix object reference leaks in machine probe reported by > Julia Lawall. This is the second version sent out in the past hour or so :( Please allow a bit more time for review and comments, people might still be looking at the earlier versions so any additional changes they spot will result in yet another resend and more noise in people's inboxes. signature.asc Description: PGP signature
[PATCH 00/21] Convert hwmon documentation to ReST
This series converts the contents of Documentation/hwmon to ReST
format.
PS.: I opted to group the conversion files per groups of maintainer
set, as, if I were to generate one patch per file, it would give around
160 patches.
I also added those patches to my development tree at:
https://git.linuxtv.org/mchehab/experimental.git/log/?h=hwmon
If you want to see the results, they're at:
https://www.infradead.org/~mchehab/hwmon/
Mauro Carvalho Chehab (21):
docs: hwmon: k10temp: convert to ReST format
docs: hwmon: vexpress: convert to ReST format
docs: hwmon: menf21bmc: convert to ReST format
docs: hwmon: sch5627: convert to ReST format
docs: hwmon: emc2103: convert to ReST format
docs: hwmon: pc87360: convert to ReST format
docs: hwmon: fam15h_power: convert to ReST format
docs: hwmon: w83791d: convert to ReST format
docs: hwmon: coretemp: convert to ReST format
docs: hwmon: aspeed-pwm-tacho: convert to ReST format
docs: hwmon: ibmpowernv: convert to ReST format
docs: hwmon: asc7621: convert to ReST format
docs: hwmon: ads1015: convert to ReST format
docs: hwmon: dme1737, vt1211: convert to ReST format
docs: hwmon: wm831x, wm8350: convert to ReST format
docs: hwmon: da9052, da9055: convert to ReST format
docs: hwmon: k8temp, w83793: convert to ReST format
docs: hwmon: pmbus files: convert to ReST format
docs: hwmon: misc files: convert to ReST format
docs: hwmon: convert remaining files to ReST format
docs: hwmon: Add an index file and rename docs to *.rst
.../devicetree/bindings/hwmon/g762.txt| 2 +-
Documentation/hwmon/{ab8500 => ab8500.rst}| 10 +-
Documentation/hwmon/abituguru | 92 ---
...guru-datasheet => abituguru-datasheet.rst} | 160 ++--
Documentation/hwmon/abituguru.rst | 113 +++
.../hwmon/{abituguru3 => abituguru3.rst} | 36 +-
Documentation/hwmon/{abx500 => abx500.rst}| 8 +-
...{acpi_power_meter => acpi_power_meter.rst} | 25 +-
Documentation/hwmon/{ad7314 => ad7314.rst}| 9 +
.../hwmon/{adc128d818 => adc128d818.rst} | 7 +-
Documentation/hwmon/{adm1021 => adm1021.rst} | 44 +-
Documentation/hwmon/{adm1025 => adm1025.rst} | 13 +-
Documentation/hwmon/{adm1026 => adm1026.rst} | 24 +-
Documentation/hwmon/{adm1031 => adm1031.rst} | 16 +-
Documentation/hwmon/{adm1275 => adm1275.rst} | 30 +-
Documentation/hwmon/{adm9240 => adm9240.rst} | 50 +-
Documentation/hwmon/{ads1015 => ads1015.rst} | 72 +-
Documentation/hwmon/{ads7828 => ads7828.rst} | 29 +-
Documentation/hwmon/{adt7410 => adt7410.rst} | 49 +-
Documentation/hwmon/{adt7411 => adt7411.rst} | 20 +-
Documentation/hwmon/{adt7462 => adt7462.rst} | 10 +-
Documentation/hwmon/{adt7470 => adt7470.rst} | 8 +-
Documentation/hwmon/{adt7475 => adt7475.rst} | 38 +-
Documentation/hwmon/{amc6821 => amc6821.rst} | 19 +-
Documentation/hwmon/{asb100 => asb100.rst}| 50 +-
Documentation/hwmon/{asc7621 => asc7621.rst} | 146 ++--
...{aspeed-pwm-tacho => aspeed-pwm-tacho.rst} | 2 +
.../hwmon/{coretemp => coretemp.rst} | 46 +-
Documentation/hwmon/{da9052 => da9052.rst}| 40 +-
Documentation/hwmon/{da9055 => da9055.rst}| 20 +-
Documentation/hwmon/{dme1737 => dme1737.rst} | 88 ++-
Documentation/hwmon/{ds1621 => ds1621.rst}| 154 ++--
Documentation/hwmon/{ds620 => ds620.rst} | 12 +-
Documentation/hwmon/{emc1403 => emc1403.rst} | 33 +-
Documentation/hwmon/{emc2103 => emc2103.rst} | 6 +-
.../hwmon/{emc6w201 => emc6w201.rst} | 5 +
Documentation/hwmon/{f71805f => f71805f.rst} | 36 +-
.../hwmon/{f71882fg => f71882fg.rst} | 56 +-
.../hwmon/{fam15h_power => fam15h_power.rst} | 85 ++-
.../hwmon/{ftsteutates => ftsteutates.rst}| 14 +-
Documentation/hwmon/{g760a => g760a.rst} | 4 +
Documentation/hwmon/{g762 => g762.rst}| 67 +-
Documentation/hwmon/{gl518sm => gl518sm.rst} | 21 +-
Documentation/hwmon/{hih6130 => hih6130.rst} | 14 +-
...on-kernel-api.txt => hwmon-kernel-api.rst} | 298
.../hwmon/{ibm-cffps => ibm-cffps.rst}| 3 +
Documentation/hwmon/{ibmaem => ibmaem.rst}| 10 +-
.../hwmon/{ibmpowernv => ibmpowernv.rst} | 3 +
Documentation/hwmon/{ina209 => ina209.rst}| 18 +-
Documentation/hwmon/{ina2xx => ina2xx.rst}| 41 +-
Documentation/hwmon/{ina3221 => ina3221.rst} | 17 +-
Documentation/hwmon/index.rst | 179 +
Documentation/hwmon/{ir35221 => ir35221.rst} | 12 +-
Documentation/hwmon/{it87 => it87.rst}| 102 ++-
Documentation/hwmon/{jc42 => jc42.rst}| 55 +-
Documentation/hwmon/{k10temp => k10temp.rst} | 37 +-
Documentation/hwmon/{k8temp => k8temp.rst}| 17 +-
.../hwmon/{lineage-pem => lineage-pem.rst}| 16 +-
Documentation/hwmon/{lm25066 => lm25066.rst} | 32 +-
Documentation/hwmon/{lm63 => lm63.rst}| 24 +-
Documentation/hwmon/{lm70 => lm70.rst}| 13 +-
Documentation/hwmon/{lm73 =>
[PATCH v4 4/4] ASoC: fsl_audmix: cache pdev->dev pointer
There should be no trouble to understand dev = pdev->dev.
This can save some space to have more print info or save
some wrapped lines.
Signed-off-by: Viorel Suman
Suggested-by: Nicolin Chen
---
sound/soc/fsl/fsl_audmix.c | 27 +--
1 file changed, 13 insertions(+), 14 deletions(-)
diff --git a/sound/soc/fsl/fsl_audmix.c b/sound/soc/fsl/fsl_audmix.c
index dc802d5..3897a54 100644
--- a/sound/soc/fsl/fsl_audmix.c
+++ b/sound/soc/fsl/fsl_audmix.c
@@ -456,6 +456,7 @@ MODULE_DEVICE_TABLE(of, fsl_audmix_ids);
static int fsl_audmix_probe(struct platform_device *pdev)
{
+ struct device *dev = &pdev->dev;
struct fsl_audmix *priv;
struct resource *res;
const char *mdrv;
@@ -463,52 +464,50 @@ static int fsl_audmix_probe(struct platform_device *pdev)
void __iomem *regs;
int ret;
- of_id = of_match_device(fsl_audmix_ids, &pdev->dev);
+ of_id = of_match_device(fsl_audmix_ids, dev);
if (!of_id || !of_id->data)
return -EINVAL;
mdrv = of_id->data;
- priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
/* Get the addresses */
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- regs = devm_ioremap_resource(&pdev->dev, res);
+ regs = devm_ioremap_resource(dev, res);
if (IS_ERR(regs))
return PTR_ERR(regs);
- priv->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "ipg", regs,
+ priv->regmap = devm_regmap_init_mmio_clk(dev, "ipg", regs,
&fsl_audmix_regmap_config);
if (IS_ERR(priv->regmap)) {
- dev_err(&pdev->dev, "failed to init regmap\n");
+ dev_err(dev, "failed to init regmap\n");
return PTR_ERR(priv->regmap);
}
- priv->ipg_clk = devm_clk_get(&pdev->dev, "ipg");
+ priv->ipg_clk = devm_clk_get(dev, "ipg");
if (IS_ERR(priv->ipg_clk)) {
- dev_err(&pdev->dev, "failed to get ipg clock\n");
+ dev_err(dev, "failed to get ipg clock\n");
return PTR_ERR(priv->ipg_clk);
}
platform_set_drvdata(pdev, priv);
- pm_runtime_enable(&pdev->dev);
+ pm_runtime_enable(dev);
- ret = devm_snd_soc_register_component(&pdev->dev, &fsl_audmix_component,
+ ret = devm_snd_soc_register_component(dev, &fsl_audmix_component,
fsl_audmix_dai,
ARRAY_SIZE(fsl_audmix_dai));
if (ret) {
- dev_err(&pdev->dev, "failed to register ASoC DAI\n");
+ dev_err(dev, "failed to register ASoC DAI\n");
return ret;
}
- priv->pdev = platform_device_register_data(&pdev->dev, mdrv, 0, NULL,
- 0);
+ priv->pdev = platform_device_register_data(dev, mdrv, 0, NULL, 0);
if (IS_ERR(priv->pdev)) {
ret = PTR_ERR(priv->pdev);
- dev_err(&pdev->dev, "failed to register platform %s: %d\n",
- mdrv, ret);
+ dev_err(dev, "failed to register platform %s: %d\n", mdrv, ret);
}
return ret;
--
2.7.4
[PATCH v4 3/4] ASoC: imx-audmix: fix object reference leaks in probe
Release the reference to the underlying device taken
by of_find_device_by_node() call.
Signed-off-by: Viorel Suman
Reported-by: Julia Lawall
Acked-by: Nicolin Chen
---
sound/soc/fsl/imx-audmix.c | 4
1 file changed, 4 insertions(+)
diff --git a/sound/soc/fsl/imx-audmix.c b/sound/soc/fsl/imx-audmix.c
index 7983bd3..9aaf3e5 100644
--- a/sound/soc/fsl/imx-audmix.c
+++ b/sound/soc/fsl/imx-audmix.c
@@ -171,6 +171,7 @@ static int imx_audmix_probe(struct platform_device *pdev)
np->full_name);
return -EINVAL;
}
+ put_device(&audmix_pdev->dev);
num_dai = of_count_phandle_with_args(audmix_np, "dais", NULL);
if (num_dai != FSL_AUDMIX_MAX_DAIS) {
@@ -216,6 +217,7 @@ static int imx_audmix_probe(struct platform_device *pdev)
dev_err(&pdev->dev, "failed to find SAI platform
device\n");
return -EINVAL;
}
+ put_device(&cpu_pdev->dev);
dai_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s%s",
fe_name_pref, args.np->full_name + 1);
@@ -280,6 +282,8 @@ static int imx_audmix_probe(struct platform_device *pdev)
dev_err(&pdev->dev, "failed to find SAI platform device\n");
return -EINVAL;
}
+ put_device(&cpu_pdev->dev);
+
priv->cpu_mclk = devm_clk_get(&cpu_pdev->dev, "mclk1");
if (IS_ERR(priv->cpu_mclk)) {
ret = PTR_ERR(priv->cpu_mclk);
--
2.7.4
[PATCH v4 2/4] ASoC: fsl_audmix: remove "model" attribute from DT document
Remove "model" attribute from fsl_audmix DT document.
Signed-off-by: Viorel Suman
Acked-by: Nicolin Chen
---
Documentation/devicetree/bindings/sound/fsl,audmix.txt | 4
1 file changed, 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/sound/fsl,audmix.txt
b/Documentation/devicetree/bindings/sound/fsl,audmix.txt
index 45f807e..840b7e0 100644
--- a/Documentation/devicetree/bindings/sound/fsl,audmix.txt
+++ b/Documentation/devicetree/bindings/sound/fsl,audmix.txt
@@ -38,9 +38,6 @@ Device driver required properties:
to SAI interfaces to be provided, the first SAI in the
list being used to route the AUDMIX output.
- - model : Must contain machine driver name which will configure
- and instantiate the appropriate audio card.
-
Device driver configuration example:
==
audmix: audmix@5984 {
@@ -50,5 +47,4 @@ Device driver configuration example:
clock-names = "ipg";
power-domains = <&pd_audmix>;
dais = <&sai4>, <&sai5>;
-model = "imx-audmix";
};
--
2.7.4
[PATCH v4 1/4] ASoC: fsl_audmix: remove "model" attribute
Use "of_device_id.data" to specify the machine driver
instead of "model" DTS attribute.
Signed-off-by: Viorel Suman
Acked-by: Nicolin Chen
---
sound/soc/fsl/fsl_audmix.c | 43 +++
1 file changed, 23 insertions(+), 20 deletions(-)
diff --git a/sound/soc/fsl/fsl_audmix.c b/sound/soc/fsl/fsl_audmix.c
index dabde03..dc802d5 100644
--- a/sound/soc/fsl/fsl_audmix.c
+++ b/sound/soc/fsl/fsl_audmix.c
@@ -445,13 +445,29 @@ static const struct regmap_config
fsl_audmix_regmap_config = {
.cache_type = REGCACHE_FLAT,
};
+static const struct of_device_id fsl_audmix_ids[] = {
+ {
+ .compatible = "fsl,imx8qm-audmix",
+ .data = "imx-audmix",
+ },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, fsl_audmix_ids);
+
static int fsl_audmix_probe(struct platform_device *pdev)
{
struct fsl_audmix *priv;
struct resource *res;
+ const char *mdrv;
+ const struct of_device_id *of_id;
void __iomem *regs;
int ret;
- const char *sprop;
+
+ of_id = of_match_device(fsl_audmix_ids, &pdev->dev);
+ if (!of_id || !of_id->data)
+ return -EINVAL;
+
+ mdrv = of_id->data;
priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
@@ -487,19 +503,12 @@ static int fsl_audmix_probe(struct platform_device *pdev)
return ret;
}
- sprop = of_get_property(pdev->dev.of_node, "model", NULL);
- if (sprop) {
- priv->pdev = platform_device_register_data(&pdev->dev, sprop, 0,
- NULL, 0);
- if (IS_ERR(priv->pdev)) {
- ret = PTR_ERR(priv->pdev);
- dev_err(&pdev->dev,
- "failed to register platform %s: %d\n", sprop,
-ret);
- }
- } else {
- dev_err(&pdev->dev, "[model] attribute missing.\n");
- ret = -EINVAL;
+ priv->pdev = platform_device_register_data(&pdev->dev, mdrv, 0, NULL,
+ 0);
+ if (IS_ERR(priv->pdev)) {
+ ret = PTR_ERR(priv->pdev);
+ dev_err(&pdev->dev, "failed to register platform %s: %d\n",
+ mdrv, ret);
}
return ret;
@@ -553,12 +562,6 @@ static const struct dev_pm_ops fsl_audmix_pm = {
pm_runtime_force_resume)
};
-static const struct of_device_id fsl_audmix_ids[] = {
- { .compatible = "fsl,imx8qm-audmix", },
- { /* sentinel */ }
-};
-MODULE_DEVICE_TABLE(of, fsl_audmix_ids);
-
static struct platform_driver fsl_audmix_driver = {
.probe = fsl_audmix_probe,
.remove = fsl_audmix_remove,
--
2.7.4
[PATCH v4 0/4] ASoC: fsl: audmix: remove "model" attribute and fix ref leaks
The latest audmix patch-set (v5) had the "model" attribute removed as requested by Nicolin Chen, but looks like (v4) version of DAI driver reached "for-next" branch - fix this by removing "model" attribute. Asside of this fix object reference leaks in machine probe reported by Julia Lawall. Viorel Suman (4): ASoC: fsl_audmix: remove "model" attribute ASoC: fsl_audmix: remove "model" attribute from DT document ASoC: imx-audmix: fix object reference leaks in probe ASoC: fsl_audmix: cache pdev->dev pointer Changes since V1: a) Removed "model" attribute from dt-bindings documentation b) Adressed Daniel's comments Changes since V2: a) Cache pdev->dev pointer in fsl_audmix probe as suggested by Nicolin Changes since V3: a) Use subject lines matching the style for the subsystem. .../devicetree/bindings/sound/fsl,audmix.txt | 4 -- sound/soc/fsl/fsl_audmix.c | 60 +++--- sound/soc/fsl/imx-audmix.c | 4 ++ 3 files changed, 35 insertions(+), 33 deletions(-) -- 2.7.4
Re: [EXT] Re: [PATCH v3 2/4] dt-bindings: fsl, audmix: remove "model" attribute
Hi Mark, On Mi, 2019-04-10 at 11:39 +0100, Mark Brown wrote: > On Wed, Apr 10, 2019 at 10:37:30AM +, Viorel Suman wrote: > > > > Remove "model" attribute. > > > > Signed-off-by: Viorel Suman > > Acked-by: Nicolin Chen > Please use subject lines matching the style for the subsystem. This > makes it easier for people to identify relevant patches. Sure, thank you, do I have to send V4 with subject fixed ?
Re: [PATCH v3 2/4] dt-bindings: fsl,audmix: remove "model" attribute
On Wed, Apr 10, 2019 at 10:37:30AM +, Viorel Suman wrote: > Remove "model" attribute. > > Signed-off-by: Viorel Suman > Acked-by: Nicolin Chen Please use subject lines matching the style for the subsystem. This makes it easier for people to identify relevant patches. signature.asc Description: PGP signature
[PATCH v3 4/4] ASoC: fsl_audmix: cache pdev->dev pointer
There should be no trouble to understand dev = pdev->dev.
This can save some space to have more print info or save
some wrapped lines.
Signed-off-by: Viorel Suman
Suggested-by: Nicolin Chen
---
sound/soc/fsl/fsl_audmix.c | 26 +-
1 file changed, 13 insertions(+), 13 deletions(-)
diff --git a/sound/soc/fsl/fsl_audmix.c b/sound/soc/fsl/fsl_audmix.c
index dc802d5..2d10d8b 100644
--- a/sound/soc/fsl/fsl_audmix.c
+++ b/sound/soc/fsl/fsl_audmix.c
@@ -456,6 +456,7 @@ MODULE_DEVICE_TABLE(of, fsl_audmix_ids);
static int fsl_audmix_probe(struct platform_device *pdev)
{
+ struct device *dev = &pdev->dev;
struct fsl_audmix *priv;
struct resource *res;
const char *mdrv;
@@ -463,51 +464,50 @@ static int fsl_audmix_probe(struct platform_device *pdev)
void __iomem *regs;
int ret;
- of_id = of_match_device(fsl_audmix_ids, &pdev->dev);
+ of_id = of_match_device(fsl_audmix_ids, dev);
if (!of_id || !of_id->data)
return -EINVAL;
mdrv = of_id->data;
- priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
/* Get the addresses */
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- regs = devm_ioremap_resource(&pdev->dev, res);
+ regs = devm_ioremap_resource(dev, res);
if (IS_ERR(regs))
return PTR_ERR(regs);
- priv->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "ipg", regs,
+ priv->regmap = devm_regmap_init_mmio_clk(dev, "ipg", regs,
&fsl_audmix_regmap_config);
if (IS_ERR(priv->regmap)) {
- dev_err(&pdev->dev, "failed to init regmap\n");
+ dev_err(dev, "failed to init regmap\n");
return PTR_ERR(priv->regmap);
}
- priv->ipg_clk = devm_clk_get(&pdev->dev, "ipg");
+ priv->ipg_clk = devm_clk_get(dev, "ipg");
if (IS_ERR(priv->ipg_clk)) {
- dev_err(&pdev->dev, "failed to get ipg clock\n");
+ dev_err(dev, "failed to get ipg clock\n");
return PTR_ERR(priv->ipg_clk);
}
platform_set_drvdata(pdev, priv);
- pm_runtime_enable(&pdev->dev);
+ pm_runtime_enable(dev);
- ret = devm_snd_soc_register_component(&pdev->dev, &fsl_audmix_component,
+ ret = devm_snd_soc_register_component(dev, &fsl_audmix_component,
fsl_audmix_dai,
ARRAY_SIZE(fsl_audmix_dai));
if (ret) {
- dev_err(&pdev->dev, "failed to register ASoC DAI\n");
+ dev_err(dev, "failed to register ASoC DAI\n");
return ret;
}
- priv->pdev = platform_device_register_data(&pdev->dev, mdrv, 0, NULL,
- 0);
+ priv->pdev = platform_device_register_data(dev, mdrv, 0, NULL, 0);
if (IS_ERR(priv->pdev)) {
ret = PTR_ERR(priv->pdev);
- dev_err(&pdev->dev, "failed to register platform %s: %d\n",
+ dev_err(dev, "failed to register platform %s: %d\n",
mdrv, ret);
}
--
2.7.4
[PATCH v3 3/4] ASoC: imx-audmix: fix object reference leaks in probe
Release the reference to the underlying device taken
by of_find_device_by_node() call.
Signed-off-by: Viorel Suman
Reported-by: Julia Lawall
Acked-by: Nicolin Chen
---
sound/soc/fsl/imx-audmix.c | 4
1 file changed, 4 insertions(+)
diff --git a/sound/soc/fsl/imx-audmix.c b/sound/soc/fsl/imx-audmix.c
index 7983bd3..9aaf3e5 100644
--- a/sound/soc/fsl/imx-audmix.c
+++ b/sound/soc/fsl/imx-audmix.c
@@ -171,6 +171,7 @@ static int imx_audmix_probe(struct platform_device *pdev)
np->full_name);
return -EINVAL;
}
+ put_device(&audmix_pdev->dev);
num_dai = of_count_phandle_with_args(audmix_np, "dais", NULL);
if (num_dai != FSL_AUDMIX_MAX_DAIS) {
@@ -216,6 +217,7 @@ static int imx_audmix_probe(struct platform_device *pdev)
dev_err(&pdev->dev, "failed to find SAI platform
device\n");
return -EINVAL;
}
+ put_device(&cpu_pdev->dev);
dai_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s%s",
fe_name_pref, args.np->full_name + 1);
@@ -280,6 +282,8 @@ static int imx_audmix_probe(struct platform_device *pdev)
dev_err(&pdev->dev, "failed to find SAI platform device\n");
return -EINVAL;
}
+ put_device(&cpu_pdev->dev);
+
priv->cpu_mclk = devm_clk_get(&cpu_pdev->dev, "mclk1");
if (IS_ERR(priv->cpu_mclk)) {
ret = PTR_ERR(priv->cpu_mclk);
--
2.7.4
[PATCH v3 2/4] dt-bindings: fsl,audmix: remove "model" attribute
Remove "model" attribute.
Signed-off-by: Viorel Suman
Acked-by: Nicolin Chen
---
Documentation/devicetree/bindings/sound/fsl,audmix.txt | 4
1 file changed, 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/sound/fsl,audmix.txt
b/Documentation/devicetree/bindings/sound/fsl,audmix.txt
index 45f807e..840b7e0 100644
--- a/Documentation/devicetree/bindings/sound/fsl,audmix.txt
+++ b/Documentation/devicetree/bindings/sound/fsl,audmix.txt
@@ -38,9 +38,6 @@ Device driver required properties:
to SAI interfaces to be provided, the first SAI in the
list being used to route the AUDMIX output.
- - model : Must contain machine driver name which will configure
- and instantiate the appropriate audio card.
-
Device driver configuration example:
==
audmix: audmix@5984 {
@@ -50,5 +47,4 @@ Device driver configuration example:
clock-names = "ipg";
power-domains = <&pd_audmix>;
dais = <&sai4>, <&sai5>;
-model = "imx-audmix";
};
--
2.7.4
[PATCH v3 1/4] ASoC: fsl_audmix: remove "model" attribute
Use "of_device_id.data" to specify the machine driver
instead of "model" DTS attribute.
Signed-off-by: Viorel Suman
Acked-by: Nicolin Chen
---
sound/soc/fsl/fsl_audmix.c | 43 +++
1 file changed, 23 insertions(+), 20 deletions(-)
diff --git a/sound/soc/fsl/fsl_audmix.c b/sound/soc/fsl/fsl_audmix.c
index dabde03..dc802d5 100644
--- a/sound/soc/fsl/fsl_audmix.c
+++ b/sound/soc/fsl/fsl_audmix.c
@@ -445,13 +445,29 @@ static const struct regmap_config
fsl_audmix_regmap_config = {
.cache_type = REGCACHE_FLAT,
};
+static const struct of_device_id fsl_audmix_ids[] = {
+ {
+ .compatible = "fsl,imx8qm-audmix",
+ .data = "imx-audmix",
+ },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, fsl_audmix_ids);
+
static int fsl_audmix_probe(struct platform_device *pdev)
{
struct fsl_audmix *priv;
struct resource *res;
+ const char *mdrv;
+ const struct of_device_id *of_id;
void __iomem *regs;
int ret;
- const char *sprop;
+
+ of_id = of_match_device(fsl_audmix_ids, &pdev->dev);
+ if (!of_id || !of_id->data)
+ return -EINVAL;
+
+ mdrv = of_id->data;
priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
@@ -487,19 +503,12 @@ static int fsl_audmix_probe(struct platform_device *pdev)
return ret;
}
- sprop = of_get_property(pdev->dev.of_node, "model", NULL);
- if (sprop) {
- priv->pdev = platform_device_register_data(&pdev->dev, sprop, 0,
- NULL, 0);
- if (IS_ERR(priv->pdev)) {
- ret = PTR_ERR(priv->pdev);
- dev_err(&pdev->dev,
- "failed to register platform %s: %d\n", sprop,
-ret);
- }
- } else {
- dev_err(&pdev->dev, "[model] attribute missing.\n");
- ret = -EINVAL;
+ priv->pdev = platform_device_register_data(&pdev->dev, mdrv, 0, NULL,
+ 0);
+ if (IS_ERR(priv->pdev)) {
+ ret = PTR_ERR(priv->pdev);
+ dev_err(&pdev->dev, "failed to register platform %s: %d\n",
+ mdrv, ret);
}
return ret;
@@ -553,12 +562,6 @@ static const struct dev_pm_ops fsl_audmix_pm = {
pm_runtime_force_resume)
};
-static const struct of_device_id fsl_audmix_ids[] = {
- { .compatible = "fsl,imx8qm-audmix", },
- { /* sentinel */ }
-};
-MODULE_DEVICE_TABLE(of, fsl_audmix_ids);
-
static struct platform_driver fsl_audmix_driver = {
.probe = fsl_audmix_probe,
.remove = fsl_audmix_remove,
--
2.7.4
[PATCH v3 0/4] ASoC: fsl: audmix: remove "model" attribute and fix ref leaks
The latest audmix patch-set (v5) had the "model" attribute removed as requested by Nicolin Chen, but looks like (v4) version of DAI driver reached "for-next" branch - fix this by removing "model" attribute. Asside of this fix object reference leaks in machine probe reported by Julia Lawall. Viorel Suman (4): ASoC: fsl_audmix: remove "model" attribute dt-bindings: fsl,audmix: remove "model" attribute ASoC: imx-audmix: fix object reference leaks in probe ASoC: fsl_audmix: cache pdev->dev pointer Changes since V1: a) Removed "model" attribute from dt-bindings documentation b) Adressed Daniel's comments Changes since V2: a) Cache pdev->dev pointer in fsl_audmix probe as suggested by Nicolin .../devicetree/bindings/sound/fsl,audmix.txt | 4 -- sound/soc/fsl/fsl_audmix.c | 61 -- sound/soc/fsl/imx-audmix.c | 4 ++ 3 files changed, 36 insertions(+), 33 deletions(-) -- 2.7.4
Re: [EXT] Re: [PATCH v2 1/3] ASoC: fsl_audmix: remove "model" attribute
Hi Nicolin, On Ma, 2019-04-09 at 21:29 -0700, Nicolin Chen wrote: > WARNING: This email was created outside of NXP. DO NOT CLICK links or > attachments unless you recognize the sender and know the content is > safe. > > > > On Tue, Apr 09, 2019 at 11:27:39AM +, Viorel Suman wrote: > > > > Use "of_device_id.data" to specify the machine driver > > instead of "model" DTS attribute. > > > > Signed-off-by: Viorel Suman > Acked-by: Nicolin Chen > > > > > --- > > sound/soc/fsl/fsl_audmix.c | 43 +++--- > > - > > 1 file changed, 23 insertions(+), 20 deletions(-) > > > > + priv->pdev = platform_device_register_data(&pdev->dev, mdrv, > > 0, NULL, > > +0); > Would you please send a separate patch to replace "pdev->dev"? Thank you for review. Yes, will send V3. /Viorel
RE: [EXT] Re: [PATCH] ASoC: fsl_asrc: replace the process_option table with function
Hi > > > On Wed, Apr 10, 2019 at 08:26:59AM +, S.j. Wang wrote: > > > Is it possible to update the table? It'd be way quicker to use > > > lookup table than real-time calculation all the time. I believe you > > > can simply calculate all the values out for 12KHz and 24KHz since > > > you have the function. If there are certain combinations of these > > > two not being supported, then we could mark it with a special value and > add an if-check to error out. > > > > > > > Yes, but I think the function should be more flexible, if someday we > > need to support Other sample rate, only need to update the list. > > Given the fact that the owner of the function cannot give more comments, I > feel the function wouldn't be very maintainable as none of us understands it > well. On the other hand, you'll need to update the supported I/O rate lists > anyway, so why not just update the table as well? The supported sample > rates from ALSA are limited too. Overall, I think that continue using a lookup > table wins. Alsa support SNDRV_PCM_RATE_KNOT, we can define the rate that we want To support, and use function is more flexible, and we have use the function Internally for long time, it is stable😊
Re: [EXT] Re: [PATCH] ASoC: fsl_asrc: replace the process_option table with function
On Wed, Apr 10, 2019 at 08:26:59AM +, S.j. Wang wrote: > > Is it possible to update the table? It'd be way quicker to use lookup table > > than real-time calculation all the time. I believe you can simply calculate > > all > > the values out for 12KHz and 24KHz since you have the function. If there are > > certain combinations of these two not being supported, then we could mark > > it with a special value and add an if-check to error out. > > > > Yes, but I think the function should be more flexible, if someday we need to > support > Other sample rate, only need to update the list. Given the fact that the owner of the function cannot give more comments, I feel the function wouldn't be very maintainable as none of us understands it well. On the other hand, you'll need to update the supported I/O rate lists anyway, so why not just update the table as well? The supported sample rates from ALSA are limited too. Overall, I think that continue using a lookup table wins.
Re: [PATCH] powerpc/pseries: Provide verbose info about HPT resizing attempt
On Wed, Apr 10, 2019 at 08:20:53PM +1000, Michael Ellerman wrote: > Bharata B Rao writes: > > > When HPT resizing is attempted in response to memory hotplug, we see > > the following messages from the kernel: > > > > lpar: Attempting to resize HPT to shift 23 > > Unable to resize hash page table to target order 23: -28 > > > > This gives a feeling as though we are trying to grow HPT but failed and > > hence bad things might happen in future. Improve the message a bit > > by explicitly printing the existing HPT shift value in addtion to > > the newly targeted value so that it is clear that we haven't failed > > to grow HPT. After this commit, the same message will appear like this: > > > > lpar: Attempting to resize HPT from shift 25 to 23 > > Unable to resize hash page table to target order 23: -28 > > > > Signed-off-by: Bharata B Rao > > I'd be inclined to just remove the "Attempting .." message. > > But I have this patch from Laurent queued, which already reworks things: > > https://patchwork.ozlabs.org/patch/1055996/ > > > Does that address your problem? Yes, I should have seen this earlier. Regards, Bharata.
Re: [PATCH] powerpc/pseries: Provide verbose info about HPT resizing attempt
Bharata B Rao writes:
> When HPT resizing is attempted in response to memory hotplug, we see
> the following messages from the kernel:
>
> lpar: Attempting to resize HPT to shift 23
> Unable to resize hash page table to target order 23: -28
>
> This gives a feeling as though we are trying to grow HPT but failed and
> hence bad things might happen in future. Improve the message a bit
> by explicitly printing the existing HPT shift value in addtion to
> the newly targeted value so that it is clear that we haven't failed
> to grow HPT. After this commit, the same message will appear like this:
>
> lpar: Attempting to resize HPT from shift 25 to 23
> Unable to resize hash page table to target order 23: -28
>
> Signed-off-by: Bharata B Rao
I'd be inclined to just remove the "Attempting .." message.
But I have this patch from Laurent queued, which already reworks things:
https://patchwork.ozlabs.org/patch/1055996/
Does that address your problem?
cheers
> diff --git a/arch/powerpc/platforms/pseries/lpar.c
> b/arch/powerpc/platforms/pseries/lpar.c
> index f2a9f0adc2d3..ecc7fa1876a9 100644
> --- a/arch/powerpc/platforms/pseries/lpar.c
> +++ b/arch/powerpc/platforms/pseries/lpar.c
> @@ -875,7 +875,8 @@ static int pseries_lpar_resize_hpt(unsigned long shift)
> if (!firmware_has_feature(FW_FEATURE_HPT_RESIZE))
> return -ENODEV;
>
> - pr_info("Attempting to resize HPT to shift %lu\n", shift);
> + pr_info("Attempting to resize HPT from shift %llu to %lu\n",
> ppc64_pft_size,
> + shift);
>
> t0 = ktime_get();
>
> --
> 2.17.1
Re: [PATCH-tip 00/22] locking/rwsem: Rework rwsem-xadd & enable new rwsem features
Hi, Waiman, What's the status of this patchset? And its merging plan? Best Regards, Huang, Ying
Re: [PATCH RFC 1/5] cpu/speculation: Add 'cpu_spec_mitigations=' cmdline options
On Wed, Apr 10, 2019 at 03:48:48PM +1000, Michael Ellerman wrote: > What about when we have a mitigation for a non-speculation related bug :) Like that is *ever* going to happen... :-P -- Regards/Gruss, Boris. Good mailing practices for 400: avoid top-posting and trim the reply.
RE: [EXT] Re: [PATCH] ASoC: fsl_asrc: replace the process_option table with function
> -Original Message- > From: Nicolin Chen > Sent: Wednesday, April 10, 2019 4:01 PM > To: S.j. Wang > Cc: ti...@kernel.org; xiubo@gmail.com; feste...@gmail.com; > broo...@kernel.org; alsa-de...@alsa-project.org; linuxppc- > d...@lists.ozlabs.org > Subject: Re: [EXT] Re: [PATCH] ASoC: fsl_asrc: replace the process_option > table with function > > WARNING: This email was created outside of NXP. DO NOT CLICK links or > attachments unless you recognize the sender and know the content is safe. > > > > On Wed, Apr 10, 2019 at 07:22:31AM +, S.j. Wang wrote: > > > The table was copied directly from the Reference Manual. We also > > > have listed all supported input and output sample rates just right behind > that table. > > > If there're missing rates, we probably should update those two lists also? > > > Otherwise, how could we have a driver limiting both I/O sample rates > > > while we still see something not in the table? > > > > > > > Yes, I plan to send another patch to update the in/out rate list. Do > > I need To merge that to this commit? Actually we want to support 12k > > and 24KHz > > Please send separate patches but in one series. And a question: > > Is it possible to update the table? It'd be way quicker to use lookup table > than real-time calculation all the time. I believe you can simply calculate > all > the values out for 12KHz and 24KHz since you have the function. If there are > certain combinations of these two not being supported, then we could mark > it with a special value and add an if-check to error out. > Yes, but I think the function should be more flexible, if someday we need to support Other sample rate, only need to update the list. > > > > +static int proc_autosel(int Fsin, int Fsout, int *pre_proc, int > > > > +*post_proc) > > > > > > Please add some comments to this function to explain what it does, > > > and how it works. And better to rename it to something like > "fsl_asrc_sel_proc". > > > > > Yes, some comments should be added, but not so detail, because this > > function > > As much comments as possible. > > > Is get from the design team, but the owner has left. > > OK...that's sad... > > > > Another thing confuses me: so we could have supported sample rates > > > in the list but the hardware might not support some of them because > > > we couldn't calculate their processing options? > > > > No, just want to support 12k, 24KHz, or others as customer like. > > I was confused because the I/O rate lists not getting updated. > It makes sense now if you are abort to update them.
Re: [EXT] Re: [PATCH] ASoC: fsl_asrc: replace the process_option table with function
On Wed, Apr 10, 2019 at 07:22:31AM +, S.j. Wang wrote: > > The table was copied directly from the Reference Manual. We also have > > listed all supported input and output sample rates just right behind that > > table. > > If there're missing rates, we probably should update those two lists also? > > Otherwise, how could we have a driver limiting both I/O sample rates while > > we still see something not in the table? > > > > Yes, I plan to send another patch to update the in/out rate list. Do I need > To merge that to this commit? Actually we want to support 12k and 24KHz Please send separate patches but in one series. And a question: Is it possible to update the table? It'd be way quicker to use lookup table than real-time calculation all the time. I believe you can simply calculate all the values out for 12KHz and 24KHz since you have the function. If there are certain combinations of these two not being supported, then we could mark it with a special value and add an if-check to error out. > > > +static int proc_autosel(int Fsin, int Fsout, int *pre_proc, int > > > +*post_proc) > > > > Please add some comments to this function to explain what it does, and how > > it works. And better to rename it to something like "fsl_asrc_sel_proc". > > > Yes, some comments should be added, but not so detail, because this function As much comments as possible. > Is get from the design team, but the owner has left. OK...that's sad... > > Another thing confuses me: so we could have supported sample rates in the > > list but the hardware might not support some of them because we couldn't > > calculate their processing options? > > No, just want to support 12k, 24KHz, or others as customer like. I was confused because the I/O rate lists not getting updated. It makes sense now if you are abort to update them.
[PATCH] powerpc/pseries: Provide verbose info about HPT resizing attempt
When HPT resizing is attempted in response to memory hotplug, we see
the following messages from the kernel:
lpar: Attempting to resize HPT to shift 23
Unable to resize hash page table to target order 23: -28
This gives a feeling as though we are trying to grow HPT but failed and
hence bad things might happen in future. Improve the message a bit
by explicitly printing the existing HPT shift value in addtion to
the newly targeted value so that it is clear that we haven't failed
to grow HPT. After this commit, the same message will appear like this:
lpar: Attempting to resize HPT from shift 25 to 23
Unable to resize hash page table to target order 23: -28
Signed-off-by: Bharata B Rao
---
arch/powerpc/platforms/pseries/lpar.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/platforms/pseries/lpar.c
b/arch/powerpc/platforms/pseries/lpar.c
index f2a9f0adc2d3..ecc7fa1876a9 100644
--- a/arch/powerpc/platforms/pseries/lpar.c
+++ b/arch/powerpc/platforms/pseries/lpar.c
@@ -875,7 +875,8 @@ static int pseries_lpar_resize_hpt(unsigned long shift)
if (!firmware_has_feature(FW_FEATURE_HPT_RESIZE))
return -ENODEV;
- pr_info("Attempting to resize HPT to shift %lu\n", shift);
+ pr_info("Attempting to resize HPT from shift %llu to %lu\n",
ppc64_pft_size,
+ shift);
t0 = ktime_get();
--
2.17.1
Re: [PATCH net] vhost: flush dcache page when logging dirty pages
On 2019/4/9 下午9:14, Michael S. Tsirkin wrote:
On Tue, Apr 09, 2019 at 12:16:47PM +0800, Jason Wang wrote:
We set dirty bit through setting up kmaps and access them through
kernel virtual address, this may result alias in virtually tagged
caches that require a dcache flush afterwards.
Cc: Christoph Hellwig
Cc: James Bottomley
Cc: Andrea Arcangeli
Fixes: 3a4d5c94e9593 ("vhost_net: a kernel-level virtio server")
This is like saying "everyone with vhost needs this".
In practice only might affect some architectures.
For the archs that does need dcache flushing, the function is just a nop.
Which ones?
There're more than 10 archs that have ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE
defined, just cc some maintainers of some more influenced ones.
You want to Cc the relevant maintainers
who understand this...
Signed-off-by: Jason Wang
I am not sure this is a good idea.
The region in question is supposed to be accessed
by userspace at the same time, through atomic operations.
How do we know userspace didn't access it just before?
get_user_pages() will do both flush_annon_page() to make sure the
userspace write is visible to kernel.
Is that an issue at all given we use
atomics for access? Documentation/core-api/cachetlb.rst does
not mention atomics.
Which architectures are affected?
Assuming atomics actually do need a flush, then don't we need
a flush in the other direction too? How are atomics
supposed to work at all?
It's the issue of visibility, atomic operation is just one of the
possible operations. If we can finally makes the write visible to each
other, there will be no issue.
It looks to me we could still end up alias if userspace is accessing the
dirty log between get_user_pages_fast() and flush_dcache_page(). But the
flush_dcache_page() can guarantee what kernel wrote is visible to
userspace finally though some bits cleared by userspace might still
there. We may end up with more dirty pages noticed by userspace which
should be harmless.
I really think we need new APIs along the lines of
set_bit_to_user.
Can we simply do:
get_user()
set bit
put_user()
instead?
---
drivers/vhost/vhost.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/vhost/vhost.c b/drivers/vhost/vhost.c
index 351af88231ad..34a1cedbc5ba 100644
--- a/drivers/vhost/vhost.c
+++ b/drivers/vhost/vhost.c
@@ -1711,6 +1711,7 @@ static int set_bit_to_user(int nr, void __user *addr)
base = kmap_atomic(page);
set_bit(bit, base);
kunmap_atomic(base);
+ flush_dcache_page(page);
set_page_dirty_lock(page);
put_page(page);
return 0;
Ignoring the question of whether this actually helps, I doubt
flush_dcache_page is appropriate here. Pls take a look at
Documentation/core-api/cachetlb.rst as well as the actual
implementation.
I think you meant flush_kernel_dcache_page, and IIUC it must happen
before kunmap, not after (which you still have the va locked).
Looks like you're right.
Thanks
--
2.19.1
RE: [EXT] Re: [PATCH] ASoC: fsl_asrc: replace the process_option table with function
Hi
>
> On Wed, Apr 10, 2019 at 03:15:26AM +, S.j. Wang wrote:
> > The table is not flexible if supported sample rate is not in the
> > table, so use a function to replace it.
>
> Could you please elaborate a bit the special use case here?
>
> The table was copied directly from the Reference Manual. We also have
> listed all supported input and output sample rates just right behind that
> table.
> If there're missing rates, we probably should update those two lists also?
> Otherwise, how could we have a driver limiting both I/O sample rates while
> we still see something not in the table?
>
Yes, I plan to send another patch to update the in/out rate list. Do I need
To merge that to this commit? Actually we want to support 12k and 24kHz
> > +static int proc_autosel(int Fsin, int Fsout, int *pre_proc, int
> > +*post_proc)
>
> Please add some comments to this function to explain what it does, and how
> it works. And better to rename it to something like "fsl_asrc_sel_proc".
>
Yes, some comments should be added, but not so detail, because this function
Is get from the design team, but the owner has left.
> > +{
> > + bool det_out_op2_cond;
> > + bool det_out_op0_cond;
> > +
> > + det_out_op2_cond = (((Fsin * 15 > Fsout * 16) & (Fsout < 56000)) |
> > + ((Fsin > 56000) & (Fsout < 56000)));
> > + det_out_op0_cond = (Fsin * 23 < Fsout * 8);
>
> "detect output option condition"? Please explain a bit or add comments to
> explain.
>
> > +
> > + /*
> > + * Not supported case: Tsout>16.125*Tsin, and Tsout>8.125*Tsin.
>
> Could be "unsupported". And it should fit within one line:
> /* Unsupported case: Tsout > 16.125 * Tsin, and Tsout > 8.125 * Tsin
> */
>
> > + */
> > + if (Fsin * 8 > 129 * Fsout)
> > + *pre_proc = 5;
> > + else if (Fsin * 8 > 65 * Fsout)
> > + *pre_proc = 4;
> > + else if (Fsin * 8 > 33 * Fsout)
> > + *pre_proc = 2;
> > + else if (Fsin * 8 > 15 * Fsout) {
> > + if (Fsin > 152000)
> > + *pre_proc = 2;
> > + else
> > + *pre_proc = 1;
> > + } else if (Fsin < 76000)
> > + *pre_proc = 0;
> > + else if (Fsin > 152000)
> > + *pre_proc = 2;
> > + else
> > + *pre_proc = 1;
> > +
> > + if (det_out_op2_cond)
> > + *post_proc = 2;
> > + else if (det_out_op0_cond)
> > + *post_proc = 0;
> > + else
> > + *post_proc = 1;
> > +
> > + if (*pre_proc == 4 || *pre_proc == 5)
> > + return -EINVAL;
>
> I think you'd better add some necessary comments here too.
>
> > @@ -377,11 +404,17 @@ static int fsl_asrc_config_pair(struct fsl_asrc_pair
> *pair)
> > ASRCTR_IDRi_MASK(index) | ASRCTR_USRi_MASK(index),
> > ASRCTR_IDR(index) | ASRCTR_USR(index));
> >
> > + ret = proc_autosel(inrate, outrate, &pre_proc, &post_proc);
> > + if (ret) {
> > + pair_err("No supported pre-processing options\n");
> > + return ret;
> > + }
>
> I think we should do this earlier in this function, once We know the inrate
> and outrate, instead of having all register being configured then going for an
> error-out.
Ok.
>
> Another thing confuses me: so we could have supported sample rates in the
> list but the hardware might not support some of them because we couldn't
> calculate their processing options?
No, just want to support 12k, 24KHz, or others as customer like.
Re: [PATCH] crypto: vmx - fix copy-paste error in CTR mode
Hi Daniel, On Fri, Mar 15, 2019 at 04:23:02PM +1100, Daniel Axtens wrote: > Eric Biggers writes: > > > Hi Daniel, > > > > On Fri, Mar 15, 2019 at 03:24:35PM +1100, Daniel Axtens wrote: > >> Hi Eric, > >> > >> >> The original assembly imported from OpenSSL has two copy-paste > >> >> errors in handling CTR mode. When dealing with a 2 or 3 block tail, > >> >> the code branches to the CBC decryption exit path, rather than to > >> >> the CTR exit path. > >> > > >> > So does this need to be fixed in OpenSSL too? > >> > >> Yes, I'm getting in touch with some people internally (at IBM) about > >> doing that. > >> > >> >> This leads to corruption of the IV, which leads to subsequent blocks > >> >> being corrupted. > >> >> > >> >> This can be detected with libkcapi test suite, which is available at > >> >> https://github.com/smuellerDD/libkcapi > >> >> > >> > > >> > Is this also detected by the kernel's crypto self-tests, and if not why > >> > not? > >> > What about with the new option CONFIG_CRYPTO_MANAGER_EXTRA_TESTS=y? > >> > >> It seems the self-tests do not catch it. To catch it, there has to be a > >> test where the blkcipher_walk creates a walk.nbytes such that > >> [(the number of AES blocks) mod 8] is either 2 or 3. This happens with > >> AF_ALG pretty frequently, but when I booted with self-tests it only hit > >> 1, 4, 5, 6 and 7 - it missed 0, 2 and 3. > >> > >> I don't have the EXTRA_TESTS option - I'm testing with 5.0-rc6. Is it in > >> -next? > >> > >> Regards, > >> Daniel > > > > The improvements I recently made to the self-tests are intended to catch > > exactly > > this sort of bug. They were just merged for v5.1, so try the latest > > mainline. > > This almost certainly would be caught by EXTRA_TESTS (and if not I'd want to > > know), but it may be caught by the regular self-tests now too. > > Well, even the patched code fails with the new self-tests, so clearly > they're catching something! I'll investigate in more detail next week. > > Regards, > Daniel > > > > > - Eric Are you still planning to fix the remaining bug? I booted a ppc64le VM, and I see the same test failure (I think) you were referring to: alg: skcipher: p8_aes_ctr encryption test failed (wrong result) on test vector 3, cfg="uneven misaligned splits, may sleep" - Eric
